1 | |
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2 | /* cpu_asm.s 1.1 - 95/12/04 |
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3 | * |
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4 | * This file contains the assembly code for the PowerPC implementation |
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5 | * of RTEMS. |
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6 | * |
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7 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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8 | * |
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9 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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10 | * |
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11 | * To anyone who acknowledges that this file is provided "AS IS" |
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12 | * without any express or implied warranty: |
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13 | * permission to use, copy, modify, and distribute this file |
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14 | * for any purpose is hereby granted without fee, provided that |
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15 | * the above copyright notice and this notice appears in all |
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16 | * copies, and that the name of i-cubed limited not be used in |
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17 | * advertising or publicity pertaining to distribution of the |
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18 | * software without specific, written prior permission. |
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19 | * i-cubed limited makes no representations about the suitability |
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20 | * of this software for any purpose. |
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21 | * |
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22 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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23 | * |
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24 | * COPYRIGHT (c) 1989-1997. |
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25 | * On-Line Applications Research Corporation (OAR). |
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26 | * |
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27 | * Copyright (c) 2011 embedded brains GmbH. |
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28 | * |
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29 | * The license and distribution terms for this file may in |
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30 | * the file LICENSE in this distribution or at |
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31 | * http://www.rtems.com/license/LICENSE. |
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32 | * |
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33 | * $Id$ |
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34 | */ |
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35 | |
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36 | #include <rtems/asm.h> |
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37 | #include <rtems/powerpc/powerpc.h> |
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38 | #include <rtems/score/cpu.h> |
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39 | #include <bspopts.h> |
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40 | |
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41 | #if BSP_DATA_CACHE_ENABLED && PPC_CACHE_ALIGNMENT == 32 |
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42 | #define DATA_CACHE_ALIGNMENT(reg) \ |
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43 | li reg, PPC_CACHE_ALIGNMENT |
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44 | #define DATA_CACHE_ZERO(rega, regb) \ |
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45 | dcbz rega, regb |
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46 | #define DATA_CACHE_TOUCH(rega, regb) \ |
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47 | dcbt rega, regb |
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48 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) \ |
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49 | li reg, offset; dcbz reg, r3; dcbt reg, r4 |
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50 | #else |
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51 | #define DATA_CACHE_ALIGNMENT(reg) |
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52 | #define DATA_CACHE_ZERO(rega, regb) |
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53 | #define DATA_CACHE_TOUCH(rega, regb) |
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54 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) \ |
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55 | li reg, offset |
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56 | #endif |
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57 | |
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58 | /* |
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59 | * Offsets for various Contexts |
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60 | */ |
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61 | .set GP_1, 0 |
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62 | .set GP_2, (GP_1 + 4) |
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63 | .set GP_13, (GP_2 + 4) |
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64 | .set GP_14, (GP_13 + 4) |
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65 | |
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66 | .set GP_15, (GP_14 + 4) |
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67 | .set GP_16, (GP_15 + 4) |
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68 | .set GP_17, (GP_16 + 4) |
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69 | .set GP_18, (GP_17 + 4) |
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70 | |
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71 | .set GP_19, (GP_18 + 4) |
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72 | .set GP_20, (GP_19 + 4) |
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73 | .set GP_21, (GP_20 + 4) |
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74 | .set GP_22, (GP_21 + 4) |
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75 | |
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76 | .set GP_23, (GP_22 + 4) |
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77 | .set GP_24, (GP_23 + 4) |
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78 | .set GP_25, (GP_24 + 4) |
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79 | .set GP_26, (GP_25 + 4) |
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80 | |
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81 | .set GP_27, (GP_26 + 4) |
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82 | .set GP_28, (GP_27 + 4) |
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83 | .set GP_29, (GP_28 + 4) |
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84 | .set GP_30, (GP_29 + 4) |
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85 | |
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86 | .set GP_31, (GP_30 + 4) |
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87 | .set GP_CR, (GP_31 + 4) |
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88 | .set GP_PC, (GP_CR + 4) |
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89 | .set GP_MSR, (GP_PC + 4) |
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90 | |
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91 | #if (PPC_HAS_DOUBLE==1) |
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92 | .set FP_SIZE, 8 |
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93 | #define LDF lfd |
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94 | #define STF stfd |
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95 | #else |
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96 | .set FP_SIZE, 4 |
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97 | #define LDF lfs |
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98 | #define STF stfs |
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99 | #endif |
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100 | |
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101 | .set FP_0, 0 |
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102 | .set FP_1, (FP_0 + FP_SIZE) |
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103 | .set FP_2, (FP_1 + FP_SIZE) |
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104 | .set FP_3, (FP_2 + FP_SIZE) |
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105 | .set FP_4, (FP_3 + FP_SIZE) |
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106 | .set FP_5, (FP_4 + FP_SIZE) |
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107 | .set FP_6, (FP_5 + FP_SIZE) |
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108 | .set FP_7, (FP_6 + FP_SIZE) |
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109 | .set FP_8, (FP_7 + FP_SIZE) |
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110 | .set FP_9, (FP_8 + FP_SIZE) |
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111 | .set FP_10, (FP_9 + FP_SIZE) |
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112 | .set FP_11, (FP_10 + FP_SIZE) |
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113 | .set FP_12, (FP_11 + FP_SIZE) |
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114 | .set FP_13, (FP_12 + FP_SIZE) |
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115 | .set FP_14, (FP_13 + FP_SIZE) |
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116 | .set FP_15, (FP_14 + FP_SIZE) |
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117 | .set FP_16, (FP_15 + FP_SIZE) |
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118 | .set FP_17, (FP_16 + FP_SIZE) |
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119 | .set FP_18, (FP_17 + FP_SIZE) |
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120 | .set FP_19, (FP_18 + FP_SIZE) |
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121 | .set FP_20, (FP_19 + FP_SIZE) |
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122 | .set FP_21, (FP_20 + FP_SIZE) |
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123 | .set FP_22, (FP_21 + FP_SIZE) |
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124 | .set FP_23, (FP_22 + FP_SIZE) |
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125 | .set FP_24, (FP_23 + FP_SIZE) |
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126 | .set FP_25, (FP_24 + FP_SIZE) |
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127 | .set FP_26, (FP_25 + FP_SIZE) |
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128 | .set FP_27, (FP_26 + FP_SIZE) |
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129 | .set FP_28, (FP_27 + FP_SIZE) |
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130 | .set FP_29, (FP_28 + FP_SIZE) |
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131 | .set FP_30, (FP_29 + FP_SIZE) |
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132 | .set FP_31, (FP_30 + FP_SIZE) |
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133 | .set FP_FPSCR, (FP_31 + FP_SIZE) |
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134 | |
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135 | .set IP_LINK, 0 |
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136 | .set IP_0, (IP_LINK + 8) |
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137 | .set IP_2, (IP_0 + 4) |
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138 | |
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139 | .set IP_3, (IP_2 + 4) |
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140 | .set IP_4, (IP_3 + 4) |
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141 | .set IP_5, (IP_4 + 4) |
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142 | .set IP_6, (IP_5 + 4) |
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143 | |
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144 | .set IP_7, (IP_6 + 4) |
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145 | .set IP_8, (IP_7 + 4) |
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146 | .set IP_9, (IP_8 + 4) |
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147 | .set IP_10, (IP_9 + 4) |
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148 | |
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149 | .set IP_11, (IP_10 + 4) |
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150 | .set IP_12, (IP_11 + 4) |
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151 | .set IP_13, (IP_12 + 4) |
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152 | .set IP_28, (IP_13 + 4) |
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153 | |
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154 | .set IP_29, (IP_28 + 4) |
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155 | .set IP_30, (IP_29 + 4) |
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156 | .set IP_31, (IP_30 + 4) |
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157 | .set IP_CR, (IP_31 + 4) |
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158 | |
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159 | .set IP_CTR, (IP_CR + 4) |
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160 | .set IP_XER, (IP_CTR + 4) |
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161 | .set IP_LR, (IP_XER + 4) |
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162 | .set IP_PC, (IP_LR + 4) |
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163 | |
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164 | .set IP_MSR, (IP_PC + 4) |
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165 | .set IP_END, (IP_MSR + 16) |
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166 | |
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167 | BEGIN_CODE |
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168 | /* |
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169 | * _CPU_Context_save_fp_context |
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170 | * |
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171 | * This routine is responsible for saving the FP context |
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172 | * at *fp_context_ptr. If the point to load the FP context |
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173 | * from is changed then the pointer is modified by this routine. |
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174 | * |
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175 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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176 | * the ** and a similarly named routine in this file is passed something |
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177 | * like a (Context_Control_fp *). The general rule on making this decision |
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178 | * is to avoid writing assembly language. |
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179 | */ |
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180 | |
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181 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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182 | PUBLIC_PROC (_CPU_Context_save_fp) |
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183 | PROC (_CPU_Context_save_fp): |
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184 | #if (PPC_HAS_FPU == 1) |
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185 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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186 | * available. Therefore, we must explicitely enable it here! |
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187 | */ |
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188 | mfmsr r4 |
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189 | andi. r5,r4,MSR_FP |
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190 | bne 1f |
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191 | ori r5,r4,MSR_FP |
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192 | mtmsr r5 |
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193 | isync |
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194 | 1: |
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195 | lwz r3, 0(r3) |
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196 | STF f0, FP_0(r3) |
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197 | STF f1, FP_1(r3) |
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198 | STF f2, FP_2(r3) |
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199 | STF f3, FP_3(r3) |
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200 | STF f4, FP_4(r3) |
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201 | STF f5, FP_5(r3) |
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202 | STF f6, FP_6(r3) |
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203 | STF f7, FP_7(r3) |
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204 | STF f8, FP_8(r3) |
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205 | STF f9, FP_9(r3) |
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206 | STF f10, FP_10(r3) |
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207 | STF f11, FP_11(r3) |
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208 | STF f12, FP_12(r3) |
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209 | STF f13, FP_13(r3) |
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210 | STF f14, FP_14(r3) |
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211 | STF f15, FP_15(r3) |
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212 | STF f16, FP_16(r3) |
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213 | STF f17, FP_17(r3) |
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214 | STF f18, FP_18(r3) |
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215 | STF f19, FP_19(r3) |
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216 | STF f20, FP_20(r3) |
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217 | STF f21, FP_21(r3) |
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218 | STF f22, FP_22(r3) |
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219 | STF f23, FP_23(r3) |
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220 | STF f24, FP_24(r3) |
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221 | STF f25, FP_25(r3) |
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222 | STF f26, FP_26(r3) |
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223 | STF f27, FP_27(r3) |
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224 | STF f28, FP_28(r3) |
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225 | STF f29, FP_29(r3) |
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226 | STF f30, FP_30(r3) |
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227 | STF f31, FP_31(r3) |
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228 | mffs f2 |
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229 | STF f2, FP_FPSCR(r3) |
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230 | bne 1f |
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231 | mtmsr r4 |
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232 | isync |
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233 | 1: |
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234 | #endif |
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235 | blr |
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236 | |
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237 | /* |
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238 | * _CPU_Context_restore_fp_context |
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239 | * |
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240 | * This routine is responsible for restoring the FP context |
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241 | * at *fp_context_ptr. If the point to load the FP context |
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242 | * from is changed then the pointer is modified by this routine. |
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243 | * |
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244 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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245 | * the ** and a similarly named routine in this file is passed something |
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246 | * like a (Context_Control_fp *). The general rule on making this decision |
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247 | * is to avoid writing assembly language. |
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248 | */ |
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249 | |
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250 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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251 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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252 | PROC (_CPU_Context_restore_fp): |
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253 | #if (PPC_HAS_FPU == 1) |
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254 | lwz r3, 0(r3) |
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255 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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256 | * available. Therefore, we must explicitely enable it here! |
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257 | */ |
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258 | mfmsr r4 |
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259 | andi. r5,r4,MSR_FP |
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260 | bne 1f |
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261 | ori r5,r4,MSR_FP |
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262 | mtmsr r5 |
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263 | isync |
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264 | 1: |
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265 | LDF f2, FP_FPSCR(r3) |
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266 | mtfsf 255, f2 |
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267 | LDF f0, FP_0(r3) |
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268 | LDF f1, FP_1(r3) |
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269 | LDF f2, FP_2(r3) |
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270 | LDF f3, FP_3(r3) |
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271 | LDF f4, FP_4(r3) |
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272 | LDF f5, FP_5(r3) |
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273 | LDF f6, FP_6(r3) |
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274 | LDF f7, FP_7(r3) |
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275 | LDF f8, FP_8(r3) |
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276 | LDF f9, FP_9(r3) |
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277 | LDF f10, FP_10(r3) |
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278 | LDF f11, FP_11(r3) |
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279 | LDF f12, FP_12(r3) |
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280 | LDF f13, FP_13(r3) |
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281 | LDF f14, FP_14(r3) |
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282 | LDF f15, FP_15(r3) |
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283 | LDF f16, FP_16(r3) |
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284 | LDF f17, FP_17(r3) |
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285 | LDF f18, FP_18(r3) |
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286 | LDF f19, FP_19(r3) |
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287 | LDF f20, FP_20(r3) |
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288 | LDF f21, FP_21(r3) |
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289 | LDF f22, FP_22(r3) |
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290 | LDF f23, FP_23(r3) |
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291 | LDF f24, FP_24(r3) |
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292 | LDF f25, FP_25(r3) |
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293 | LDF f26, FP_26(r3) |
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294 | LDF f27, FP_27(r3) |
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295 | LDF f28, FP_28(r3) |
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296 | LDF f29, FP_29(r3) |
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297 | LDF f30, FP_30(r3) |
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298 | LDF f31, FP_31(r3) |
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299 | bne 1f |
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300 | mtmsr r4 |
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301 | isync |
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302 | 1: |
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303 | #endif |
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304 | blr |
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305 | |
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306 | /* _CPU_Context_switch |
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307 | * |
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308 | * This routine performs a normal non-FP context switch. |
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309 | */ |
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310 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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311 | PUBLIC_PROC (_CPU_Context_switch) |
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312 | PROC (_CPU_Context_switch): |
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313 | #ifndef __SPE__ |
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314 | sync |
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315 | isync |
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316 | /* This assumes that all the registers are in the given order */ |
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317 | DATA_CACHE_ALIGNMENT(r5) |
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318 | addi r9,r3,-4 |
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319 | DATA_CACHE_ZERO(r5, r9) |
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320 | #ifdef RTEMS_MULTIPROCESSING |
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321 | /* |
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322 | * We have to clear the reservation of the executing thread. See also |
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323 | * Book E section 6.1.6.2 "Atomic Update Primitives". |
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324 | */ |
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325 | li r10, GP_1 + 4 |
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326 | stwcx. r1, r9, r10 |
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327 | #endif |
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328 | stw r1, GP_1+4(r9) |
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329 | stw r2, GP_2+4(r9) |
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330 | #if (PPC_USE_MULTIPLE == 1) |
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331 | addi r9, r9, GP_18+4 |
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332 | DATA_CACHE_ZERO(r5, r9) |
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333 | stmw r13, GP_13-GP_18(r9) |
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334 | #else |
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335 | stw r13, GP_13+4(r9) |
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336 | stw r14, GP_14+4(r9) |
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337 | stw r15, GP_15+4(r9) |
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338 | stw r16, GP_16+4(r9) |
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339 | stw r17, GP_17+4(r9) |
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340 | stwu r18, GP_18+4(r9) |
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341 | DATA_CACHE_ZERO(r5, r9) |
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342 | stw r19, GP_19-GP_18(r9) |
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343 | stw r20, GP_20-GP_18(r9) |
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344 | stw r21, GP_21-GP_18(r9) |
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345 | stw r22, GP_22-GP_18(r9) |
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346 | stw r23, GP_23-GP_18(r9) |
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347 | stw r24, GP_24-GP_18(r9) |
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348 | stw r25, GP_25-GP_18(r9) |
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349 | stw r26, GP_26-GP_18(r9) |
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350 | stw r27, GP_27-GP_18(r9) |
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351 | stw r28, GP_28-GP_18(r9) |
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352 | stw r29, GP_29-GP_18(r9) |
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353 | stw r30, GP_30-GP_18(r9) |
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354 | stw r31, GP_31-GP_18(r9) |
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355 | #endif |
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356 | DATA_CACHE_TOUCH(r0, r4) |
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357 | mfcr r6 |
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358 | stw r6, GP_CR-GP_18(r9) |
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359 | mflr r7 |
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360 | stw r7, GP_PC-GP_18(r9) |
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361 | mfmsr r8 |
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362 | stw r8, GP_MSR-GP_18(r9) |
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363 | |
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364 | #ifdef __ALTIVEC__ |
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365 | mr r14, r4 |
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366 | EXTERN_PROC(_CPU_Context_switch_altivec) |
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367 | bl _CPU_Context_switch_altivec |
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368 | mr r4, r14 |
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369 | DATA_CACHE_ALIGNMENT(r5) |
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370 | #endif |
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371 | |
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372 | DATA_CACHE_TOUCH(r5, r4) |
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373 | lwz r1, GP_1(r4) |
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374 | lwz r2, GP_2(r4) |
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375 | #if (PPC_USE_MULTIPLE == 1) |
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376 | addi r4, r4, GP_19 |
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377 | DATA_CACHE_TOUCH(r5, r4) |
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378 | lmw r13, GP_13-GP_19(r4) |
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379 | #else |
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380 | lwz r13, GP_13(r4) |
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381 | lwz r14, GP_14(r4) |
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382 | lwz r15, GP_15(r4) |
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383 | lwz r16, GP_16(r4) |
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384 | lwz r17, GP_17(r4) |
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385 | lwz r18, GP_18(r4) |
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386 | lwzu r19, GP_19(r4) |
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387 | DATA_CACHE_TOUCH(r5, r4) |
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388 | lwz r20, GP_20-GP_19(r4) |
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389 | lwz r21, GP_21-GP_19(r4) |
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390 | lwz r22, GP_22-GP_19(r4) |
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391 | lwz r23, GP_23-GP_19(r4) |
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392 | lwz r24, GP_24-GP_19(r4) |
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393 | lwz r25, GP_25-GP_19(r4) |
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394 | lwz r26, GP_26-GP_19(r4) |
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395 | lwz r27, GP_27-GP_19(r4) |
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396 | lwz r28, GP_28-GP_19(r4) |
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397 | lwz r29, GP_29-GP_19(r4) |
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398 | lwz r30, GP_30-GP_19(r4) |
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399 | lwz r31, GP_31-GP_19(r4) |
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400 | #endif |
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401 | lwz r6, GP_CR-GP_19(r4) |
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402 | lwz r7, GP_PC-GP_19(r4) |
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403 | lwz r8, GP_MSR-GP_19(r4) |
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404 | mtcrf 255, r6 |
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405 | mtlr r7 |
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406 | mtmsr r8 |
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407 | isync |
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408 | |
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409 | blr |
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410 | #else /* __SPE__ */ |
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411 | /* Align to a cache line */ |
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412 | clrrwi r3, r3, 5 |
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413 | clrrwi r4, r4, 5 |
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414 | |
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415 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_0) |
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416 | DATA_CACHE_ZERO_AND_TOUCH(r11, PPC_CONTEXT_CACHE_LINE_1) |
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417 | |
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418 | /* Save context to r3 */ |
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419 | |
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420 | mfmsr r5 |
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421 | mflr r6 |
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422 | mfcr r7 |
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423 | #ifdef RTEMS_MULTIPROCESSING |
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424 | /* |
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425 | * We have to clear the reservation of the executing thread. See also |
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426 | * Book E section 6.1.6.2 "Atomic Update Primitives". |
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427 | * |
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428 | * Here we assume PPC_CONTEXT_OFFSET_SP == PPC_CONTEXT_CACHE_LINE_0. |
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429 | */ |
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430 | stwcx. r1, r3, r10 |
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431 | #endif |
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432 | stw r1, PPC_CONTEXT_OFFSET_SP(r3) |
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433 | stw r5, PPC_CONTEXT_OFFSET_MSR(r3) |
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434 | stw r6, PPC_CONTEXT_OFFSET_LR(r3) |
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435 | stw r7, PPC_CONTEXT_OFFSET_CR(r3) |
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436 | evstdd r14, PPC_CONTEXT_OFFSET_GPR14(r3) |
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437 | evstdd r15, PPC_CONTEXT_OFFSET_GPR15(r3) |
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438 | |
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439 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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440 | |
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441 | evstdd r16, PPC_CONTEXT_OFFSET_GPR16(r3) |
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442 | evstdd r17, PPC_CONTEXT_OFFSET_GPR17(r3) |
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443 | evstdd r18, PPC_CONTEXT_OFFSET_GPR18(r3) |
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444 | evstdd r19, PPC_CONTEXT_OFFSET_GPR19(r3) |
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445 | |
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446 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_3) |
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447 | |
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448 | evstdd r20, PPC_CONTEXT_OFFSET_GPR20(r3) |
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449 | evstdd r21, PPC_CONTEXT_OFFSET_GPR21(r3) |
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450 | evstdd r22, PPC_CONTEXT_OFFSET_GPR22(r3) |
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451 | evstdd r23, PPC_CONTEXT_OFFSET_GPR23(r3) |
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452 | |
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453 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_4) |
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454 | |
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455 | evstdd r24, PPC_CONTEXT_OFFSET_GPR24(r3) |
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456 | evstdd r25, PPC_CONTEXT_OFFSET_GPR25(r3) |
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457 | evstdd r26, PPC_CONTEXT_OFFSET_GPR26(r3) |
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458 | evstdd r27, PPC_CONTEXT_OFFSET_GPR27(r3) |
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459 | |
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460 | evstdd r28, PPC_CONTEXT_OFFSET_GPR28(r3) |
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461 | evstdd r29, PPC_CONTEXT_OFFSET_GPR29(r3) |
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462 | evstdd r30, PPC_CONTEXT_OFFSET_GPR30(r3) |
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463 | evstdd r31, PPC_CONTEXT_OFFSET_GPR31(r3) |
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464 | |
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465 | /* Restore context from r4 */ |
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466 | restore_context: |
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467 | |
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468 | lwz r1, PPC_CONTEXT_OFFSET_SP(r4) |
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469 | lwz r5, PPC_CONTEXT_OFFSET_MSR(r4) |
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470 | lwz r6, PPC_CONTEXT_OFFSET_LR(r4) |
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471 | lwz r7, PPC_CONTEXT_OFFSET_CR(r4) |
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472 | |
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473 | evldd r14, PPC_CONTEXT_OFFSET_GPR14(r4) |
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474 | evldd r15, PPC_CONTEXT_OFFSET_GPR15(r4) |
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475 | |
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476 | DATA_CACHE_TOUCH(r0, r1) |
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477 | |
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478 | evldd r16, PPC_CONTEXT_OFFSET_GPR16(r4) |
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479 | evldd r17, PPC_CONTEXT_OFFSET_GPR17(r4) |
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480 | evldd r18, PPC_CONTEXT_OFFSET_GPR18(r4) |
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481 | evldd r19, PPC_CONTEXT_OFFSET_GPR19(r4) |
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482 | |
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483 | evldd r20, PPC_CONTEXT_OFFSET_GPR20(r4) |
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484 | evldd r21, PPC_CONTEXT_OFFSET_GPR21(r4) |
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485 | evldd r22, PPC_CONTEXT_OFFSET_GPR22(r4) |
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486 | evldd r23, PPC_CONTEXT_OFFSET_GPR23(r4) |
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487 | |
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488 | evldd r24, PPC_CONTEXT_OFFSET_GPR24(r4) |
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489 | evldd r25, PPC_CONTEXT_OFFSET_GPR25(r4) |
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490 | evldd r26, PPC_CONTEXT_OFFSET_GPR26(r4) |
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491 | evldd r27, PPC_CONTEXT_OFFSET_GPR27(r4) |
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492 | |
---|
493 | evldd r28, PPC_CONTEXT_OFFSET_GPR28(r4) |
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494 | evldd r29, PPC_CONTEXT_OFFSET_GPR29(r4) |
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495 | evldd r30, PPC_CONTEXT_OFFSET_GPR30(r4) |
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496 | evldd r31, PPC_CONTEXT_OFFSET_GPR31(r4) |
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497 | |
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498 | mtcr r7 |
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499 | mtlr r6 |
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500 | mtmsr r5 |
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501 | |
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502 | blr |
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503 | #endif /* __SPE__ */ |
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504 | |
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505 | /* |
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506 | * _CPU_Context_restore |
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507 | * |
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508 | * This routine is generallu used only to restart self in an |
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509 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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510 | * |
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511 | * NOTE: May be unnecessary to reload some registers. |
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512 | */ |
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513 | /* |
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514 | * ACB: Don't worry about cache optimisation here - this is not THAT critical. |
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515 | */ |
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516 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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517 | PUBLIC_PROC (_CPU_Context_restore) |
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518 | PROC (_CPU_Context_restore): |
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519 | #ifndef __SPE__ |
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520 | lwz r5, GP_CR(r3) |
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521 | lwz r6, GP_PC(r3) |
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522 | lwz r7, GP_MSR(r3) |
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523 | mtcrf 255, r5 |
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524 | mtlr r6 |
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525 | mtmsr r7 |
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526 | isync |
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527 | lwz r1, GP_1(r3) |
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528 | lwz r2, GP_2(r3) |
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529 | #if (PPC_USE_MULTIPLE == 1) |
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530 | lmw r13, GP_13(r3) |
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531 | #else |
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532 | lwz r13, GP_13(r3) |
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533 | lwz r14, GP_14(r3) |
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534 | lwz r15, GP_15(r3) |
---|
535 | lwz r16, GP_16(r3) |
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536 | lwz r17, GP_17(r3) |
---|
537 | lwz r18, GP_18(r3) |
---|
538 | lwz r19, GP_19(r3) |
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539 | lwz r20, GP_20(r3) |
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540 | lwz r21, GP_21(r3) |
---|
541 | lwz r22, GP_22(r3) |
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542 | lwz r23, GP_23(r3) |
---|
543 | lwz r24, GP_24(r3) |
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544 | lwz r25, GP_25(r3) |
---|
545 | lwz r26, GP_26(r3) |
---|
546 | lwz r27, GP_27(r3) |
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547 | lwz r28, GP_28(r3) |
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548 | lwz r29, GP_29(r3) |
---|
549 | lwz r30, GP_30(r3) |
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550 | lwz r31, GP_31(r3) |
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551 | #endif |
---|
552 | #ifdef __ALTIVEC__ |
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553 | EXTERN_PROC(_CPU_Context_restore_altivec) |
---|
554 | b _CPU_Context_restore_altivec |
---|
555 | #endif |
---|
556 | blr |
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557 | #else /* __SPE__ */ |
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558 | /* Align to a cache line */ |
---|
559 | clrrwi r4, r3, 5 |
---|
560 | |
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561 | b restore_context |
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562 | #endif /* __SPE__ */ |
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