1 | /* cpu_asm.s 1.1 - 95/12/04 |
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2 | * |
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3 | * This file contains the assembly code for the PowerPC implementation |
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4 | * of RTEMS. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * |
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26 | * Copyright (c) 2011, 2016 embedded brains GmbH |
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27 | * |
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28 | * The license and distribution terms for this file may in |
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29 | * the file LICENSE in this distribution or at |
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30 | * http://www.rtems.org/license/LICENSE. |
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31 | */ |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | #include <rtems/powerpc/powerpc.h> |
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35 | #include <rtems/score/percpu.h> |
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36 | #include <libcpu/powerpc-utility.h> |
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37 | #include <bspopts.h> |
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38 | |
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39 | #ifdef BSP_USE_DATA_CACHE_BLOCK_TOUCH |
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40 | #define DATA_CACHE_TOUCH(rega, regb) \ |
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41 | dcbt rega, regb |
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42 | #else |
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43 | #define DATA_CACHE_TOUCH(rega, regb) |
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44 | #endif |
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45 | |
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46 | #if BSP_DATA_CACHE_ENABLED && PPC_DEFAULT_CACHE_LINE_SIZE == 32 |
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47 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) \ |
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48 | li reg, offset; dcbz reg, r3; DATA_CACHE_TOUCH(reg, r4) |
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49 | #else |
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50 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) |
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51 | #endif |
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52 | |
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53 | #define PPC_CONTEXT_CACHE_LINE_0 (1 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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54 | #define PPC_CONTEXT_CACHE_LINE_1 (2 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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55 | #define PPC_CONTEXT_CACHE_LINE_2 (3 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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56 | #define PPC_CONTEXT_CACHE_LINE_3 (4 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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57 | #define PPC_CONTEXT_CACHE_LINE_4 (5 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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58 | #define PPC_CONTEXT_CACHE_LINE_5 (6 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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59 | |
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60 | BEGIN_CODE |
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61 | |
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62 | #if PPC_HAS_FPU == 1 |
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63 | |
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64 | /* |
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65 | * Offsets for Context_Control_fp |
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66 | */ |
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67 | |
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68 | #if (PPC_HAS_DOUBLE==1) |
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69 | .set FP_SIZE, 8 |
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70 | #define LDF lfd |
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71 | #define STF stfd |
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72 | #else |
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73 | .set FP_SIZE, 4 |
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74 | #define LDF lfs |
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75 | #define STF stfs |
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76 | #endif |
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77 | |
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78 | .set FP_0, 0 |
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79 | .set FP_1, (FP_0 + FP_SIZE) |
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80 | .set FP_2, (FP_1 + FP_SIZE) |
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81 | .set FP_3, (FP_2 + FP_SIZE) |
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82 | .set FP_4, (FP_3 + FP_SIZE) |
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83 | .set FP_5, (FP_4 + FP_SIZE) |
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84 | .set FP_6, (FP_5 + FP_SIZE) |
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85 | .set FP_7, (FP_6 + FP_SIZE) |
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86 | .set FP_8, (FP_7 + FP_SIZE) |
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87 | .set FP_9, (FP_8 + FP_SIZE) |
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88 | .set FP_10, (FP_9 + FP_SIZE) |
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89 | .set FP_11, (FP_10 + FP_SIZE) |
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90 | .set FP_12, (FP_11 + FP_SIZE) |
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91 | .set FP_13, (FP_12 + FP_SIZE) |
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92 | .set FP_14, (FP_13 + FP_SIZE) |
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93 | .set FP_15, (FP_14 + FP_SIZE) |
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94 | .set FP_16, (FP_15 + FP_SIZE) |
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95 | .set FP_17, (FP_16 + FP_SIZE) |
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96 | .set FP_18, (FP_17 + FP_SIZE) |
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97 | .set FP_19, (FP_18 + FP_SIZE) |
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98 | .set FP_20, (FP_19 + FP_SIZE) |
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99 | .set FP_21, (FP_20 + FP_SIZE) |
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100 | .set FP_22, (FP_21 + FP_SIZE) |
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101 | .set FP_23, (FP_22 + FP_SIZE) |
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102 | .set FP_24, (FP_23 + FP_SIZE) |
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103 | .set FP_25, (FP_24 + FP_SIZE) |
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104 | .set FP_26, (FP_25 + FP_SIZE) |
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105 | .set FP_27, (FP_26 + FP_SIZE) |
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106 | .set FP_28, (FP_27 + FP_SIZE) |
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107 | .set FP_29, (FP_28 + FP_SIZE) |
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108 | .set FP_30, (FP_29 + FP_SIZE) |
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109 | .set FP_31, (FP_30 + FP_SIZE) |
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110 | .set FP_FPSCR, (FP_31 + FP_SIZE) |
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111 | |
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112 | /* |
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113 | * _CPU_Context_save_fp_context |
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114 | * |
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115 | * This routine is responsible for saving the FP context |
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116 | * at *fp_context_ptr. If the point to load the FP context |
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117 | * from is changed then the pointer is modified by this routine. |
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118 | * |
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119 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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120 | * the ** and a similarly named routine in this file is passed something |
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121 | * like a (Context_Control_fp *). The general rule on making this decision |
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122 | * is to avoid writing assembly language. |
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123 | */ |
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124 | |
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125 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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126 | PUBLIC_PROC (_CPU_Context_save_fp) |
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127 | PROC (_CPU_Context_save_fp): |
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128 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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129 | * available. Therefore, we must explicitely enable it here! |
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130 | */ |
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131 | mfmsr r4 |
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132 | andi. r5,r4,MSR_FP |
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133 | bne 1f |
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134 | ori r5,r4,MSR_FP |
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135 | mtmsr r5 |
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136 | isync |
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137 | 1: |
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138 | lwz r3, 0(r3) |
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139 | STF f0, FP_0(r3) |
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140 | STF f1, FP_1(r3) |
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141 | STF f2, FP_2(r3) |
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142 | STF f3, FP_3(r3) |
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143 | STF f4, FP_4(r3) |
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144 | STF f5, FP_5(r3) |
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145 | STF f6, FP_6(r3) |
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146 | STF f7, FP_7(r3) |
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147 | STF f8, FP_8(r3) |
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148 | STF f9, FP_9(r3) |
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149 | STF f10, FP_10(r3) |
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150 | STF f11, FP_11(r3) |
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151 | STF f12, FP_12(r3) |
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152 | STF f13, FP_13(r3) |
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153 | STF f14, FP_14(r3) |
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154 | STF f15, FP_15(r3) |
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155 | STF f16, FP_16(r3) |
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156 | STF f17, FP_17(r3) |
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157 | STF f18, FP_18(r3) |
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158 | STF f19, FP_19(r3) |
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159 | STF f20, FP_20(r3) |
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160 | STF f21, FP_21(r3) |
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161 | STF f22, FP_22(r3) |
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162 | STF f23, FP_23(r3) |
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163 | STF f24, FP_24(r3) |
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164 | STF f25, FP_25(r3) |
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165 | STF f26, FP_26(r3) |
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166 | STF f27, FP_27(r3) |
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167 | STF f28, FP_28(r3) |
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168 | STF f29, FP_29(r3) |
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169 | STF f30, FP_30(r3) |
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170 | STF f31, FP_31(r3) |
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171 | mffs f2 |
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172 | STF f2, FP_FPSCR(r3) |
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173 | bne 1f |
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174 | mtmsr r4 |
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175 | isync |
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176 | 1: |
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177 | blr |
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178 | |
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179 | /* |
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180 | * _CPU_Context_restore_fp_context |
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181 | * |
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182 | * This routine is responsible for restoring the FP context |
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183 | * at *fp_context_ptr. If the point to load the FP context |
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184 | * from is changed then the pointer is modified by this routine. |
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185 | * |
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186 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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187 | * the ** and a similarly named routine in this file is passed something |
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188 | * like a (Context_Control_fp *). The general rule on making this decision |
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189 | * is to avoid writing assembly language. |
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190 | */ |
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191 | |
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192 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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193 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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194 | PROC (_CPU_Context_restore_fp): |
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195 | lwz r3, 0(r3) |
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196 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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197 | * available. Therefore, we must explicitely enable it here! |
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198 | */ |
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199 | mfmsr r4 |
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200 | andi. r5,r4,MSR_FP |
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201 | bne 1f |
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202 | ori r5,r4,MSR_FP |
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203 | mtmsr r5 |
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204 | isync |
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205 | 1: |
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206 | LDF f2, FP_FPSCR(r3) |
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207 | mtfsf 255, f2 |
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208 | LDF f0, FP_0(r3) |
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209 | LDF f1, FP_1(r3) |
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210 | LDF f2, FP_2(r3) |
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211 | LDF f3, FP_3(r3) |
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212 | LDF f4, FP_4(r3) |
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213 | LDF f5, FP_5(r3) |
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214 | LDF f6, FP_6(r3) |
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215 | LDF f7, FP_7(r3) |
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216 | LDF f8, FP_8(r3) |
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217 | LDF f9, FP_9(r3) |
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218 | LDF f10, FP_10(r3) |
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219 | LDF f11, FP_11(r3) |
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220 | LDF f12, FP_12(r3) |
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221 | LDF f13, FP_13(r3) |
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222 | LDF f14, FP_14(r3) |
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223 | LDF f15, FP_15(r3) |
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224 | LDF f16, FP_16(r3) |
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225 | LDF f17, FP_17(r3) |
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226 | LDF f18, FP_18(r3) |
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227 | LDF f19, FP_19(r3) |
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228 | LDF f20, FP_20(r3) |
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229 | LDF f21, FP_21(r3) |
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230 | LDF f22, FP_22(r3) |
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231 | LDF f23, FP_23(r3) |
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232 | LDF f24, FP_24(r3) |
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233 | LDF f25, FP_25(r3) |
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234 | LDF f26, FP_26(r3) |
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235 | LDF f27, FP_27(r3) |
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236 | LDF f28, FP_28(r3) |
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237 | LDF f29, FP_29(r3) |
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238 | LDF f30, FP_30(r3) |
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239 | LDF f31, FP_31(r3) |
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240 | bne 1f |
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241 | mtmsr r4 |
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242 | isync |
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243 | 1: |
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244 | blr |
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245 | #endif /* PPC_HAS_FPU == 1 */ |
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246 | |
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247 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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248 | PUBLIC_PROC (_CPU_Context_switch) |
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249 | PROC (_CPU_Context_switch): |
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250 | |
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251 | #ifdef BSP_USE_SYNC_IN_CONTEXT_SWITCH |
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252 | sync |
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253 | isync |
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254 | #endif |
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255 | |
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256 | /* Align to a cache line */ |
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257 | clrrwi r3, r3, PPC_DEFAULT_CACHE_LINE_POWER |
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258 | clrrwi r5, r4, PPC_DEFAULT_CACHE_LINE_POWER |
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259 | |
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260 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_0) |
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261 | |
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262 | #if PPC_CONTEXT_CACHE_LINE_2 <= PPC_CONTEXT_VOLATILE_SIZE |
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263 | DATA_CACHE_ZERO_AND_TOUCH(r11, PPC_CONTEXT_CACHE_LINE_1) |
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264 | #endif |
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265 | |
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266 | /* Save context to r3 */ |
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267 | |
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268 | GET_SELF_CPU_CONTROL r12 |
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269 | mfmsr r6 |
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270 | mflr r7 |
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271 | mfcr r8 |
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272 | lwz r11, PER_CPU_ISR_DISPATCH_DISABLE(r12) |
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273 | |
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274 | /* |
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275 | * We have to clear the reservation of the executing thread. See also |
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276 | * Book E section 6.1.6.2 "Atomic Update Primitives". Recent GCC |
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277 | * versions use atomic operations in the C++ library for example. On |
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278 | * SMP configurations the reservation is cleared later during the |
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279 | * context switch. |
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280 | */ |
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281 | #if PPC_CONTEXT_OFFSET_GPR1 != PPC_CONTEXT_CACHE_LINE_0 \ |
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282 | || !BSP_DATA_CACHE_ENABLED \ |
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283 | || PPC_DEFAULT_CACHE_LINE_SIZE != 32 |
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284 | li r10, PPC_CONTEXT_OFFSET_GPR1 |
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285 | #endif |
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286 | #ifndef RTEMS_SMP |
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287 | stwcx. r1, r3, r10 |
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288 | #endif |
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289 | |
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290 | stw r1, PPC_CONTEXT_OFFSET_GPR1(r3) |
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291 | stw r6, PPC_CONTEXT_OFFSET_MSR(r3) |
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292 | stw r7, PPC_CONTEXT_OFFSET_LR(r3) |
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293 | stw r8, PPC_CONTEXT_OFFSET_CR(r3) |
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294 | PPC_GPR_STORE r14, PPC_CONTEXT_OFFSET_GPR14(r3) |
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295 | PPC_GPR_STORE r15, PPC_CONTEXT_OFFSET_GPR15(r3) |
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296 | |
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297 | #if PPC_CONTEXT_OFFSET_GPR20 == PPC_CONTEXT_CACHE_LINE_2 |
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298 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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299 | #endif |
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300 | |
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301 | PPC_GPR_STORE r16, PPC_CONTEXT_OFFSET_GPR16(r3) |
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302 | PPC_GPR_STORE r17, PPC_CONTEXT_OFFSET_GPR17(r3) |
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303 | |
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304 | #if PPC_CONTEXT_OFFSET_GPR26 == PPC_CONTEXT_CACHE_LINE_2 |
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305 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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306 | #endif |
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307 | |
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308 | PPC_GPR_STORE r18, PPC_CONTEXT_OFFSET_GPR18(r3) |
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309 | PPC_GPR_STORE r19, PPC_CONTEXT_OFFSET_GPR19(r3) |
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310 | |
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311 | #if PPC_CONTEXT_OFFSET_GPR24 == PPC_CONTEXT_CACHE_LINE_3 |
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312 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_3) |
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313 | #endif |
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314 | |
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315 | PPC_GPR_STORE r20, PPC_CONTEXT_OFFSET_GPR20(r3) |
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316 | PPC_GPR_STORE r21, PPC_CONTEXT_OFFSET_GPR21(r3) |
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317 | PPC_GPR_STORE r22, PPC_CONTEXT_OFFSET_GPR22(r3) |
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318 | PPC_GPR_STORE r23, PPC_CONTEXT_OFFSET_GPR23(r3) |
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319 | |
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320 | #if PPC_CONTEXT_OFFSET_GPR28 == PPC_CONTEXT_CACHE_LINE_4 |
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321 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_4) |
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322 | #endif |
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323 | |
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324 | PPC_GPR_STORE r24, PPC_CONTEXT_OFFSET_GPR24(r3) |
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325 | PPC_GPR_STORE r25, PPC_CONTEXT_OFFSET_GPR25(r3) |
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326 | |
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327 | #if PPC_CONTEXT_OFFSET_V22 == PPC_CONTEXT_CACHE_LINE_2 |
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328 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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329 | #endif |
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330 | |
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331 | PPC_GPR_STORE r26, PPC_CONTEXT_OFFSET_GPR26(r3) |
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332 | PPC_GPR_STORE r27, PPC_CONTEXT_OFFSET_GPR27(r3) |
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333 | |
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334 | PPC_GPR_STORE r28, PPC_CONTEXT_OFFSET_GPR28(r3) |
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335 | PPC_GPR_STORE r29, PPC_CONTEXT_OFFSET_GPR29(r3) |
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336 | PPC_GPR_STORE r30, PPC_CONTEXT_OFFSET_GPR30(r3) |
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337 | PPC_GPR_STORE r31, PPC_CONTEXT_OFFSET_GPR31(r3) |
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338 | |
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339 | stw r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r3) |
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340 | |
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341 | #ifdef PPC_MULTILIB_ALTIVEC |
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342 | li r9, PPC_CONTEXT_OFFSET_V20 |
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343 | stvx v20, r3, r9 |
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344 | li r9, PPC_CONTEXT_OFFSET_V21 |
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345 | stvx v21, r3, r9 |
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346 | |
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347 | #if PPC_CONTEXT_OFFSET_V26 == PPC_CONTEXT_CACHE_LINE_3 |
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348 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_3) |
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349 | #endif |
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350 | |
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351 | li r9, PPC_CONTEXT_OFFSET_V22 |
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352 | stvx v22, r3, r9 |
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353 | li r9, PPC_CONTEXT_OFFSET_V23 |
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354 | stvx v23, r3, r9 |
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355 | li r9, PPC_CONTEXT_OFFSET_V24 |
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356 | stvx v24, r3, r9 |
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357 | li r9, PPC_CONTEXT_OFFSET_V25 |
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358 | stvx v25, r3, r9 |
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359 | |
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360 | #if PPC_CONTEXT_OFFSET_V30 == PPC_CONTEXT_CACHE_LINE_4 |
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361 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_4) |
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362 | #endif |
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363 | |
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364 | li r9, PPC_CONTEXT_OFFSET_V26 |
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365 | stvx v26, r3, r9 |
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366 | li r9, PPC_CONTEXT_OFFSET_V27 |
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367 | stvx v27, r3, r9 |
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368 | li r9, PPC_CONTEXT_OFFSET_V28 |
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369 | stvx v28, r3, r9 |
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370 | li r9, PPC_CONTEXT_OFFSET_V29 |
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371 | stvx v29, r3, r9 |
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372 | |
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373 | #if PPC_CONTEXT_OFFSET_F17 == PPC_CONTEXT_CACHE_LINE_5 |
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374 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_5) |
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375 | #endif |
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376 | |
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377 | li r9, PPC_CONTEXT_OFFSET_V30 |
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378 | stvx v30, r3, r9 |
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379 | li r9, PPC_CONTEXT_OFFSET_V31 |
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380 | stvx v31, r3, r9 |
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381 | mfvrsave r9 |
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382 | stw r9, PPC_CONTEXT_OFFSET_VRSAVE(r3) |
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383 | #endif |
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384 | |
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385 | #ifdef PPC_MULTILIB_FPU |
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386 | stfd f14, PPC_CONTEXT_OFFSET_F14(r3) |
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387 | stfd f15, PPC_CONTEXT_OFFSET_F15(r3) |
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388 | stfd f16, PPC_CONTEXT_OFFSET_F16(r3) |
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389 | stfd f17, PPC_CONTEXT_OFFSET_F17(r3) |
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390 | stfd f18, PPC_CONTEXT_OFFSET_F18(r3) |
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391 | stfd f19, PPC_CONTEXT_OFFSET_F19(r3) |
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392 | stfd f20, PPC_CONTEXT_OFFSET_F20(r3) |
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393 | stfd f21, PPC_CONTEXT_OFFSET_F21(r3) |
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394 | stfd f22, PPC_CONTEXT_OFFSET_F22(r3) |
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395 | stfd f23, PPC_CONTEXT_OFFSET_F23(r3) |
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396 | stfd f24, PPC_CONTEXT_OFFSET_F24(r3) |
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397 | stfd f25, PPC_CONTEXT_OFFSET_F25(r3) |
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398 | stfd f26, PPC_CONTEXT_OFFSET_F26(r3) |
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399 | stfd f27, PPC_CONTEXT_OFFSET_F27(r3) |
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400 | stfd f28, PPC_CONTEXT_OFFSET_F28(r3) |
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401 | stfd f29, PPC_CONTEXT_OFFSET_F29(r3) |
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402 | stfd f30, PPC_CONTEXT_OFFSET_F30(r3) |
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403 | stfd f31, PPC_CONTEXT_OFFSET_F31(r3) |
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404 | #endif |
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405 | |
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406 | #ifdef RTEMS_SMP |
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407 | /* |
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408 | * The executing thread no longer executes on this processor. Switch |
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409 | * the stack to the temporary interrupt stack of this processor. Mark |
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410 | * the context of the executing thread as not executing. |
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411 | */ |
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412 | msync |
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413 | |
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414 | addi r1, r12, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE |
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415 | li r6, 0 |
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416 | stw r6, PPC_CONTEXT_OFFSET_IS_EXECUTING(r3) |
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417 | |
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418 | .Lcheck_is_executing: |
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419 | |
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420 | /* Check the is executing indicator of the heir context */ |
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421 | addi r6, r5, PPC_CONTEXT_OFFSET_IS_EXECUTING |
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422 | lwarx r7, r0, r6 |
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423 | cmpwi r7, 0 |
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424 | bne .Lget_potential_new_heir |
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425 | |
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426 | /* Try to update the is executing indicator of the heir context */ |
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427 | li r7, 1 |
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428 | stwcx. r7, r0, r6 |
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429 | bne .Lget_potential_new_heir |
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430 | isync |
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431 | #endif |
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432 | |
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433 | /* Restore context from r5 */ |
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434 | restore_context: |
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435 | |
---|
436 | #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) |
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437 | mr r4, r5 |
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438 | .extern _CPU_Context_switch_altivec |
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439 | bl _CPU_Context_switch_altivec |
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440 | #endif |
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441 | |
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442 | lwz r1, PPC_CONTEXT_OFFSET_GPR1(r5) |
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443 | lwz r6, PPC_CONTEXT_OFFSET_MSR(r5) |
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444 | lwz r7, PPC_CONTEXT_OFFSET_LR(r5) |
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445 | lwz r8, PPC_CONTEXT_OFFSET_CR(r5) |
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446 | |
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447 | PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r5) |
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448 | PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r5) |
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449 | |
---|
450 | DATA_CACHE_TOUCH(r0, r1) |
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451 | |
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452 | PPC_GPR_LOAD r16, PPC_CONTEXT_OFFSET_GPR16(r5) |
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453 | PPC_GPR_LOAD r17, PPC_CONTEXT_OFFSET_GPR17(r5) |
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454 | PPC_GPR_LOAD r18, PPC_CONTEXT_OFFSET_GPR18(r5) |
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455 | PPC_GPR_LOAD r19, PPC_CONTEXT_OFFSET_GPR19(r5) |
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456 | |
---|
457 | PPC_GPR_LOAD r20, PPC_CONTEXT_OFFSET_GPR20(r5) |
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458 | PPC_GPR_LOAD r21, PPC_CONTEXT_OFFSET_GPR21(r5) |
---|
459 | PPC_GPR_LOAD r22, PPC_CONTEXT_OFFSET_GPR22(r5) |
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460 | PPC_GPR_LOAD r23, PPC_CONTEXT_OFFSET_GPR23(r5) |
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461 | |
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462 | PPC_GPR_LOAD r24, PPC_CONTEXT_OFFSET_GPR24(r5) |
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463 | PPC_GPR_LOAD r25, PPC_CONTEXT_OFFSET_GPR25(r5) |
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464 | PPC_GPR_LOAD r26, PPC_CONTEXT_OFFSET_GPR26(r5) |
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465 | PPC_GPR_LOAD r27, PPC_CONTEXT_OFFSET_GPR27(r5) |
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466 | |
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467 | PPC_GPR_LOAD r28, PPC_CONTEXT_OFFSET_GPR28(r5) |
---|
468 | PPC_GPR_LOAD r29, PPC_CONTEXT_OFFSET_GPR29(r5) |
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469 | PPC_GPR_LOAD r30, PPC_CONTEXT_OFFSET_GPR30(r5) |
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470 | PPC_GPR_LOAD r31, PPC_CONTEXT_OFFSET_GPR31(r5) |
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471 | |
---|
472 | lwz r2, PPC_CONTEXT_OFFSET_GPR2(r5) |
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473 | lwz r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r5) |
---|
474 | |
---|
475 | #ifdef PPC_MULTILIB_ALTIVEC |
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476 | li r9, PPC_CONTEXT_OFFSET_V20 |
---|
477 | lvx v20, r5, r9 |
---|
478 | li r9, PPC_CONTEXT_OFFSET_V21 |
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479 | lvx v21, r5, r9 |
---|
480 | li r9, PPC_CONTEXT_OFFSET_V22 |
---|
481 | lvx v22, r5, r9 |
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482 | li r9, PPC_CONTEXT_OFFSET_V23 |
---|
483 | lvx v23, r5, r9 |
---|
484 | li r9, PPC_CONTEXT_OFFSET_V24 |
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485 | lvx v24, r5, r9 |
---|
486 | li r9, PPC_CONTEXT_OFFSET_V25 |
---|
487 | lvx v25, r5, r9 |
---|
488 | li r9, PPC_CONTEXT_OFFSET_V26 |
---|
489 | lvx v26, r5, r9 |
---|
490 | li r9, PPC_CONTEXT_OFFSET_V27 |
---|
491 | lvx v27, r5, r9 |
---|
492 | li r9, PPC_CONTEXT_OFFSET_V28 |
---|
493 | lvx v28, r5, r9 |
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494 | li r9, PPC_CONTEXT_OFFSET_V29 |
---|
495 | lvx v29, r5, r9 |
---|
496 | li r9, PPC_CONTEXT_OFFSET_V30 |
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497 | lvx v30, r5, r9 |
---|
498 | li r9, PPC_CONTEXT_OFFSET_V31 |
---|
499 | lvx v31, r5, r9 |
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500 | lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r5) |
---|
501 | mtvrsave r9 |
---|
502 | #endif |
---|
503 | |
---|
504 | #ifdef PPC_MULTILIB_FPU |
---|
505 | lfd f14, PPC_CONTEXT_OFFSET_F14(r5) |
---|
506 | lfd f15, PPC_CONTEXT_OFFSET_F15(r5) |
---|
507 | lfd f16, PPC_CONTEXT_OFFSET_F16(r5) |
---|
508 | lfd f17, PPC_CONTEXT_OFFSET_F17(r5) |
---|
509 | lfd f18, PPC_CONTEXT_OFFSET_F18(r5) |
---|
510 | lfd f19, PPC_CONTEXT_OFFSET_F19(r5) |
---|
511 | lfd f20, PPC_CONTEXT_OFFSET_F20(r5) |
---|
512 | lfd f21, PPC_CONTEXT_OFFSET_F21(r5) |
---|
513 | lfd f22, PPC_CONTEXT_OFFSET_F22(r5) |
---|
514 | lfd f23, PPC_CONTEXT_OFFSET_F23(r5) |
---|
515 | lfd f24, PPC_CONTEXT_OFFSET_F24(r5) |
---|
516 | lfd f25, PPC_CONTEXT_OFFSET_F25(r5) |
---|
517 | lfd f26, PPC_CONTEXT_OFFSET_F26(r5) |
---|
518 | lfd f27, PPC_CONTEXT_OFFSET_F27(r5) |
---|
519 | lfd f28, PPC_CONTEXT_OFFSET_F28(r5) |
---|
520 | lfd f29, PPC_CONTEXT_OFFSET_F29(r5) |
---|
521 | lfd f30, PPC_CONTEXT_OFFSET_F30(r5) |
---|
522 | lfd f31, PPC_CONTEXT_OFFSET_F31(r5) |
---|
523 | #endif |
---|
524 | |
---|
525 | mtcr r8 |
---|
526 | mtlr r7 |
---|
527 | mtmsr r6 |
---|
528 | stw r11, PER_CPU_ISR_DISPATCH_DISABLE(r12) |
---|
529 | |
---|
530 | #ifdef BSP_USE_SYNC_IN_CONTEXT_SWITCH |
---|
531 | isync |
---|
532 | #endif |
---|
533 | |
---|
534 | blr |
---|
535 | |
---|
536 | PUBLIC_PROC (_CPU_Context_restore) |
---|
537 | PROC (_CPU_Context_restore): |
---|
538 | /* Align to a cache line */ |
---|
539 | clrrwi r5, r3, PPC_DEFAULT_CACHE_LINE_POWER |
---|
540 | |
---|
541 | GET_SELF_CPU_CONTROL r12 |
---|
542 | |
---|
543 | #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) |
---|
544 | li r3, 0 |
---|
545 | #endif |
---|
546 | |
---|
547 | b restore_context |
---|
548 | |
---|
549 | #ifdef RTEMS_SMP |
---|
550 | .Lget_potential_new_heir: |
---|
551 | |
---|
552 | /* We may have a new heir */ |
---|
553 | |
---|
554 | /* Read the executing and heir */ |
---|
555 | lwz r7, PER_CPU_OFFSET_EXECUTING(r12) |
---|
556 | lwz r8, PER_CPU_OFFSET_HEIR(r12) |
---|
557 | |
---|
558 | /* |
---|
559 | * Update the executing only if necessary to avoid cache line |
---|
560 | * monopolization. |
---|
561 | */ |
---|
562 | cmpw r7, r8 |
---|
563 | beq .Lcheck_is_executing |
---|
564 | |
---|
565 | /* Calculate the heir context pointer */ |
---|
566 | sub r7, r4, r7 |
---|
567 | add r4, r8, r7 |
---|
568 | clrrwi r5, r4, PPC_DEFAULT_CACHE_LINE_POWER |
---|
569 | |
---|
570 | /* Update the executing */ |
---|
571 | stw r8, PER_CPU_OFFSET_EXECUTING(r12) |
---|
572 | |
---|
573 | b .Lcheck_is_executing |
---|
574 | #endif |
---|