1 | /* cpu_asm.s 1.1 - 95/12/04 |
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2 | * |
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3 | * This file contains the assembly code for the PowerPC implementation |
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4 | * of RTEMS. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * |
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26 | * Copyright (c) 2011-2014 embedded brains GmbH |
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27 | * |
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28 | * The license and distribution terms for this file may in |
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29 | * the file LICENSE in this distribution or at |
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30 | * http://www.rtems.org/license/LICENSE. |
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31 | */ |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | #include <rtems/powerpc/powerpc.h> |
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35 | #include <rtems/score/percpu.h> |
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36 | #include <libcpu/powerpc-utility.h> |
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37 | #include <bspopts.h> |
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38 | |
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39 | #ifdef BSP_USE_DATA_CACHE_BLOCK_TOUCH |
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40 | #define DATA_CACHE_TOUCH(rega, regb) \ |
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41 | dcbt rega, regb |
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42 | #else |
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43 | #define DATA_CACHE_TOUCH(rega, regb) |
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44 | #endif |
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45 | |
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46 | #if BSP_DATA_CACHE_ENABLED && PPC_DEFAULT_CACHE_LINE_SIZE == 32 |
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47 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) \ |
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48 | li reg, offset; dcbz reg, r3; DATA_CACHE_TOUCH(reg, r4) |
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49 | #else |
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50 | #define DATA_CACHE_ZERO_AND_TOUCH(reg, offset) |
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51 | #endif |
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52 | |
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53 | #define PPC_CONTEXT_CACHE_LINE_0 (1 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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54 | #define PPC_CONTEXT_CACHE_LINE_1 (2 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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55 | #define PPC_CONTEXT_CACHE_LINE_2 (3 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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56 | #define PPC_CONTEXT_CACHE_LINE_3 (4 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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57 | #define PPC_CONTEXT_CACHE_LINE_4 (5 * PPC_DEFAULT_CACHE_LINE_SIZE) |
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58 | |
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59 | BEGIN_CODE |
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60 | |
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61 | #if PPC_HAS_FPU == 1 |
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62 | |
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63 | /* |
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64 | * Offsets for Context_Control_fp |
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65 | */ |
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66 | |
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67 | #if (PPC_HAS_DOUBLE==1) |
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68 | .set FP_SIZE, 8 |
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69 | #define LDF lfd |
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70 | #define STF stfd |
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71 | #else |
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72 | .set FP_SIZE, 4 |
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73 | #define LDF lfs |
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74 | #define STF stfs |
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75 | #endif |
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76 | |
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77 | .set FP_0, 0 |
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78 | .set FP_1, (FP_0 + FP_SIZE) |
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79 | .set FP_2, (FP_1 + FP_SIZE) |
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80 | .set FP_3, (FP_2 + FP_SIZE) |
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81 | .set FP_4, (FP_3 + FP_SIZE) |
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82 | .set FP_5, (FP_4 + FP_SIZE) |
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83 | .set FP_6, (FP_5 + FP_SIZE) |
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84 | .set FP_7, (FP_6 + FP_SIZE) |
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85 | .set FP_8, (FP_7 + FP_SIZE) |
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86 | .set FP_9, (FP_8 + FP_SIZE) |
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87 | .set FP_10, (FP_9 + FP_SIZE) |
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88 | .set FP_11, (FP_10 + FP_SIZE) |
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89 | .set FP_12, (FP_11 + FP_SIZE) |
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90 | .set FP_13, (FP_12 + FP_SIZE) |
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91 | .set FP_14, (FP_13 + FP_SIZE) |
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92 | .set FP_15, (FP_14 + FP_SIZE) |
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93 | .set FP_16, (FP_15 + FP_SIZE) |
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94 | .set FP_17, (FP_16 + FP_SIZE) |
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95 | .set FP_18, (FP_17 + FP_SIZE) |
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96 | .set FP_19, (FP_18 + FP_SIZE) |
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97 | .set FP_20, (FP_19 + FP_SIZE) |
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98 | .set FP_21, (FP_20 + FP_SIZE) |
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99 | .set FP_22, (FP_21 + FP_SIZE) |
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100 | .set FP_23, (FP_22 + FP_SIZE) |
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101 | .set FP_24, (FP_23 + FP_SIZE) |
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102 | .set FP_25, (FP_24 + FP_SIZE) |
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103 | .set FP_26, (FP_25 + FP_SIZE) |
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104 | .set FP_27, (FP_26 + FP_SIZE) |
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105 | .set FP_28, (FP_27 + FP_SIZE) |
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106 | .set FP_29, (FP_28 + FP_SIZE) |
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107 | .set FP_30, (FP_29 + FP_SIZE) |
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108 | .set FP_31, (FP_30 + FP_SIZE) |
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109 | .set FP_FPSCR, (FP_31 + FP_SIZE) |
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110 | |
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111 | /* |
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112 | * _CPU_Context_save_fp_context |
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113 | * |
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114 | * This routine is responsible for saving the FP context |
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115 | * at *fp_context_ptr. If the point to load the FP context |
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116 | * from is changed then the pointer is modified by this routine. |
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117 | * |
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118 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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119 | * the ** and a similarly named routine in this file is passed something |
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120 | * like a (Context_Control_fp *). The general rule on making this decision |
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121 | * is to avoid writing assembly language. |
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122 | */ |
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123 | |
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124 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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125 | PUBLIC_PROC (_CPU_Context_save_fp) |
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126 | PROC (_CPU_Context_save_fp): |
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127 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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128 | * available. Therefore, we must explicitely enable it here! |
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129 | */ |
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130 | mfmsr r4 |
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131 | andi. r5,r4,MSR_FP |
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132 | bne 1f |
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133 | ori r5,r4,MSR_FP |
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134 | mtmsr r5 |
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135 | isync |
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136 | 1: |
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137 | lwz r3, 0(r3) |
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138 | STF f0, FP_0(r3) |
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139 | STF f1, FP_1(r3) |
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140 | STF f2, FP_2(r3) |
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141 | STF f3, FP_3(r3) |
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142 | STF f4, FP_4(r3) |
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143 | STF f5, FP_5(r3) |
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144 | STF f6, FP_6(r3) |
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145 | STF f7, FP_7(r3) |
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146 | STF f8, FP_8(r3) |
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147 | STF f9, FP_9(r3) |
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148 | STF f10, FP_10(r3) |
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149 | STF f11, FP_11(r3) |
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150 | STF f12, FP_12(r3) |
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151 | STF f13, FP_13(r3) |
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152 | STF f14, FP_14(r3) |
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153 | STF f15, FP_15(r3) |
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154 | STF f16, FP_16(r3) |
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155 | STF f17, FP_17(r3) |
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156 | STF f18, FP_18(r3) |
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157 | STF f19, FP_19(r3) |
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158 | STF f20, FP_20(r3) |
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159 | STF f21, FP_21(r3) |
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160 | STF f22, FP_22(r3) |
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161 | STF f23, FP_23(r3) |
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162 | STF f24, FP_24(r3) |
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163 | STF f25, FP_25(r3) |
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164 | STF f26, FP_26(r3) |
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165 | STF f27, FP_27(r3) |
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166 | STF f28, FP_28(r3) |
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167 | STF f29, FP_29(r3) |
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168 | STF f30, FP_30(r3) |
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169 | STF f31, FP_31(r3) |
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170 | mffs f2 |
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171 | STF f2, FP_FPSCR(r3) |
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172 | bne 1f |
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173 | mtmsr r4 |
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174 | isync |
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175 | 1: |
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176 | blr |
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177 | |
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178 | /* |
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179 | * _CPU_Context_restore_fp_context |
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180 | * |
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181 | * This routine is responsible for restoring the FP context |
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182 | * at *fp_context_ptr. If the point to load the FP context |
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183 | * from is changed then the pointer is modified by this routine. |
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184 | * |
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185 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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186 | * the ** and a similarly named routine in this file is passed something |
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187 | * like a (Context_Control_fp *). The general rule on making this decision |
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188 | * is to avoid writing assembly language. |
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189 | */ |
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190 | |
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191 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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192 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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193 | PROC (_CPU_Context_restore_fp): |
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194 | lwz r3, 0(r3) |
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195 | /* A FP context switch may occur in an ISR or exception handler when the FPU is not |
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196 | * available. Therefore, we must explicitely enable it here! |
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197 | */ |
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198 | mfmsr r4 |
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199 | andi. r5,r4,MSR_FP |
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200 | bne 1f |
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201 | ori r5,r4,MSR_FP |
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202 | mtmsr r5 |
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203 | isync |
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204 | 1: |
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205 | LDF f2, FP_FPSCR(r3) |
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206 | mtfsf 255, f2 |
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207 | LDF f0, FP_0(r3) |
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208 | LDF f1, FP_1(r3) |
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209 | LDF f2, FP_2(r3) |
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210 | LDF f3, FP_3(r3) |
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211 | LDF f4, FP_4(r3) |
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212 | LDF f5, FP_5(r3) |
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213 | LDF f6, FP_6(r3) |
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214 | LDF f7, FP_7(r3) |
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215 | LDF f8, FP_8(r3) |
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216 | LDF f9, FP_9(r3) |
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217 | LDF f10, FP_10(r3) |
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218 | LDF f11, FP_11(r3) |
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219 | LDF f12, FP_12(r3) |
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220 | LDF f13, FP_13(r3) |
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221 | LDF f14, FP_14(r3) |
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222 | LDF f15, FP_15(r3) |
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223 | LDF f16, FP_16(r3) |
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224 | LDF f17, FP_17(r3) |
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225 | LDF f18, FP_18(r3) |
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226 | LDF f19, FP_19(r3) |
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227 | LDF f20, FP_20(r3) |
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228 | LDF f21, FP_21(r3) |
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229 | LDF f22, FP_22(r3) |
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230 | LDF f23, FP_23(r3) |
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231 | LDF f24, FP_24(r3) |
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232 | LDF f25, FP_25(r3) |
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233 | LDF f26, FP_26(r3) |
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234 | LDF f27, FP_27(r3) |
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235 | LDF f28, FP_28(r3) |
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236 | LDF f29, FP_29(r3) |
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237 | LDF f30, FP_30(r3) |
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238 | LDF f31, FP_31(r3) |
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239 | bne 1f |
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240 | mtmsr r4 |
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241 | isync |
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242 | 1: |
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243 | blr |
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244 | #endif /* PPC_HAS_FPU == 1 */ |
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245 | |
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246 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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247 | PUBLIC_PROC (_CPU_Context_switch) |
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248 | PROC (_CPU_Context_switch): |
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249 | |
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250 | #ifdef BSP_USE_SYNC_IN_CONTEXT_SWITCH |
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251 | sync |
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252 | isync |
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253 | #endif |
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254 | |
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255 | /* Align to a cache line */ |
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256 | clrrwi r3, r3, PPC_DEFAULT_CACHE_LINE_POWER |
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257 | clrrwi r5, r4, PPC_DEFAULT_CACHE_LINE_POWER |
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258 | |
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259 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_0) |
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260 | DATA_CACHE_ZERO_AND_TOUCH(r11, PPC_CONTEXT_CACHE_LINE_1) |
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261 | |
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262 | /* Save context to r3 */ |
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263 | |
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264 | mfmsr r6 |
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265 | mflr r7 |
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266 | mfcr r8 |
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267 | |
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268 | /* |
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269 | * We have to clear the reservation of the executing thread. See also |
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270 | * Book E section 6.1.6.2 "Atomic Update Primitives". Recent GCC |
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271 | * versions use atomic operations in the C++ library for example. On |
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272 | * SMP configurations the reservation is cleared later during the |
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273 | * context switch. |
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274 | */ |
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275 | #if PPC_CONTEXT_OFFSET_GPR1 != PPC_CONTEXT_CACHE_LINE_0 \ |
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276 | || !BSP_DATA_CACHE_ENABLED \ |
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277 | || PPC_DEFAULT_CACHE_LINE_SIZE != 32 |
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278 | li r10, PPC_CONTEXT_OFFSET_GPR1 |
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279 | #endif |
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280 | #ifndef RTEMS_SMP |
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281 | stwcx. r1, r3, r10 |
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282 | #endif |
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283 | |
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284 | stw r1, PPC_CONTEXT_OFFSET_GPR1(r3) |
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285 | stw r6, PPC_CONTEXT_OFFSET_MSR(r3) |
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286 | stw r7, PPC_CONTEXT_OFFSET_LR(r3) |
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287 | stw r8, PPC_CONTEXT_OFFSET_CR(r3) |
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288 | PPC_GPR_STORE r14, PPC_CONTEXT_OFFSET_GPR14(r3) |
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289 | PPC_GPR_STORE r15, PPC_CONTEXT_OFFSET_GPR15(r3) |
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290 | |
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291 | #if PPC_CONTEXT_OFFSET_GPR20 == PPC_CONTEXT_CACHE_LINE_2 |
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292 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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293 | #endif |
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294 | |
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295 | PPC_GPR_STORE r16, PPC_CONTEXT_OFFSET_GPR16(r3) |
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296 | PPC_GPR_STORE r17, PPC_CONTEXT_OFFSET_GPR17(r3) |
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297 | |
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298 | #if PPC_CONTEXT_OFFSET_GPR26 == PPC_CONTEXT_CACHE_LINE_2 |
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299 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_2) |
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300 | #endif |
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301 | |
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302 | PPC_GPR_STORE r18, PPC_CONTEXT_OFFSET_GPR18(r3) |
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303 | PPC_GPR_STORE r19, PPC_CONTEXT_OFFSET_GPR19(r3) |
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304 | |
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305 | #if PPC_CONTEXT_OFFSET_GPR24 == PPC_CONTEXT_CACHE_LINE_3 |
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306 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_3) |
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307 | #endif |
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308 | |
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309 | PPC_GPR_STORE r20, PPC_CONTEXT_OFFSET_GPR20(r3) |
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310 | PPC_GPR_STORE r21, PPC_CONTEXT_OFFSET_GPR21(r3) |
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311 | PPC_GPR_STORE r22, PPC_CONTEXT_OFFSET_GPR22(r3) |
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312 | PPC_GPR_STORE r23, PPC_CONTEXT_OFFSET_GPR23(r3) |
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313 | |
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314 | #if PPC_CONTEXT_OFFSET_GPR28 == PPC_CONTEXT_CACHE_LINE_4 |
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315 | DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_4) |
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316 | #endif |
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317 | |
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318 | PPC_GPR_STORE r24, PPC_CONTEXT_OFFSET_GPR24(r3) |
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319 | PPC_GPR_STORE r25, PPC_CONTEXT_OFFSET_GPR25(r3) |
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320 | PPC_GPR_STORE r26, PPC_CONTEXT_OFFSET_GPR26(r3) |
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321 | PPC_GPR_STORE r27, PPC_CONTEXT_OFFSET_GPR27(r3) |
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322 | |
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323 | PPC_GPR_STORE r28, PPC_CONTEXT_OFFSET_GPR28(r3) |
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324 | PPC_GPR_STORE r29, PPC_CONTEXT_OFFSET_GPR29(r3) |
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325 | PPC_GPR_STORE r30, PPC_CONTEXT_OFFSET_GPR30(r3) |
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326 | PPC_GPR_STORE r31, PPC_CONTEXT_OFFSET_GPR31(r3) |
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327 | |
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328 | stw r2, PPC_CONTEXT_OFFSET_GPR2(r3) |
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329 | |
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330 | #ifdef RTEMS_SMP |
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331 | /* The executing context no longer executes on this processor */ |
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332 | msync |
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333 | li r6, 0 |
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334 | stw r6, PPC_CONTEXT_OFFSET_IS_EXECUTING(r3) |
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335 | |
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336 | check_is_executing: |
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337 | |
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338 | /* Check the is executing indicator of the heir context */ |
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339 | addi r6, r5, PPC_CONTEXT_OFFSET_IS_EXECUTING |
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340 | lwarx r7, r0, r6 |
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341 | cmpwi r7, 0 |
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342 | bne check_thread_dispatch_necessary |
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343 | |
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344 | /* Try to update the is executing indicator of the heir context */ |
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345 | li r7, 1 |
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346 | stwcx. r7, r0, r6 |
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347 | bne check_thread_dispatch_necessary |
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348 | isync |
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349 | #endif |
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350 | |
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351 | /* Restore context from r5 */ |
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352 | restore_context: |
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353 | |
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354 | #ifdef __ALTIVEC__ |
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355 | mr r14, r5 |
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356 | .extern _CPU_Context_switch_altivec |
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357 | bl _CPU_Context_switch_altivec |
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358 | mr r5, r14 |
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359 | #endif |
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360 | |
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361 | lwz r1, PPC_CONTEXT_OFFSET_GPR1(r5) |
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362 | lwz r6, PPC_CONTEXT_OFFSET_MSR(r5) |
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363 | lwz r7, PPC_CONTEXT_OFFSET_LR(r5) |
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364 | lwz r8, PPC_CONTEXT_OFFSET_CR(r5) |
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365 | |
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366 | PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r5) |
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367 | PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r5) |
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368 | |
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369 | DATA_CACHE_TOUCH(r0, r1) |
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370 | |
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371 | PPC_GPR_LOAD r16, PPC_CONTEXT_OFFSET_GPR16(r5) |
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372 | PPC_GPR_LOAD r17, PPC_CONTEXT_OFFSET_GPR17(r5) |
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373 | PPC_GPR_LOAD r18, PPC_CONTEXT_OFFSET_GPR18(r5) |
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374 | PPC_GPR_LOAD r19, PPC_CONTEXT_OFFSET_GPR19(r5) |
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375 | |
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376 | PPC_GPR_LOAD r20, PPC_CONTEXT_OFFSET_GPR20(r5) |
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377 | PPC_GPR_LOAD r21, PPC_CONTEXT_OFFSET_GPR21(r5) |
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378 | PPC_GPR_LOAD r22, PPC_CONTEXT_OFFSET_GPR22(r5) |
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379 | PPC_GPR_LOAD r23, PPC_CONTEXT_OFFSET_GPR23(r5) |
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380 | |
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381 | PPC_GPR_LOAD r24, PPC_CONTEXT_OFFSET_GPR24(r5) |
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382 | PPC_GPR_LOAD r25, PPC_CONTEXT_OFFSET_GPR25(r5) |
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383 | PPC_GPR_LOAD r26, PPC_CONTEXT_OFFSET_GPR26(r5) |
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384 | PPC_GPR_LOAD r27, PPC_CONTEXT_OFFSET_GPR27(r5) |
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385 | |
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386 | PPC_GPR_LOAD r28, PPC_CONTEXT_OFFSET_GPR28(r5) |
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387 | PPC_GPR_LOAD r29, PPC_CONTEXT_OFFSET_GPR29(r5) |
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388 | PPC_GPR_LOAD r30, PPC_CONTEXT_OFFSET_GPR30(r5) |
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389 | PPC_GPR_LOAD r31, PPC_CONTEXT_OFFSET_GPR31(r5) |
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390 | |
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391 | lwz r2, PPC_CONTEXT_OFFSET_GPR2(r5) |
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392 | |
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393 | mtcr r8 |
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394 | mtlr r7 |
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395 | mtmsr r6 |
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396 | |
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397 | #ifdef BSP_USE_SYNC_IN_CONTEXT_SWITCH |
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398 | isync |
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399 | #endif |
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400 | |
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401 | blr |
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402 | |
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403 | PUBLIC_PROC (_CPU_Context_restore) |
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404 | PROC (_CPU_Context_restore): |
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405 | /* Align to a cache line */ |
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406 | clrrwi r5, r3, PPC_DEFAULT_CACHE_LINE_POWER |
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407 | |
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408 | #ifdef __ALTIVEC__ |
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409 | li r3, 0 |
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410 | #endif |
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411 | |
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412 | b restore_context |
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413 | |
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414 | #ifdef RTEMS_SMP |
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415 | check_thread_dispatch_necessary: |
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416 | |
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417 | GET_SELF_CPU_CONTROL r6 |
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418 | |
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419 | /* Check if a thread dispatch is necessary */ |
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420 | lbz r7, PER_CPU_DISPATCH_NEEDED(r6) |
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421 | cmpwi r7, 0 |
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422 | beq check_is_executing |
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423 | |
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424 | /* We have a new heir */ |
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425 | |
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426 | /* Clear the thread dispatch necessary flag */ |
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427 | li r7, 0 |
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428 | stb r7, PER_CPU_DISPATCH_NEEDED(r6) |
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429 | msync |
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430 | |
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431 | /* Read the executing and heir */ |
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432 | lwz r7, PER_CPU_OFFSET_EXECUTING(r6) |
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433 | lwz r8, PER_CPU_OFFSET_HEIR(r6) |
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434 | |
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435 | /* Calculate the heir context pointer */ |
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436 | sub r7, r4, r7 |
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437 | add r4, r8, r7 |
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438 | clrrwi r5, r4, PPC_DEFAULT_CACHE_LINE_POWER |
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439 | |
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440 | /* Update the executing */ |
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441 | stw r8, PER_CPU_OFFSET_EXECUTING(r6) |
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442 | |
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443 | b check_is_executing |
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444 | #endif |
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