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cpu_asm.S @ ae2b1e0

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Last change on this file since ae2b1e0 was ae2b1e0, checked in by Sebastian Huber <sebastian.huber@…>, on 06/07/11 at 12:59:39

2011-06-07 Sebastian Huber <sebastian.huber@…>

new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of PPC_USE_DATA_CACHE.

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1
2	/* cpu_asm.s 1.1 - 95/12/04
3	*
4	* This file contains the assembly code for the PowerPC implementation
5	* of RTEMS.
6	*
7	* Author: Andrew Bray <andy@i-cubed.co.uk>
8	*
9	* COPYRIGHT (c) 1995 by i-cubed ltd.
10	*
11	* To anyone who acknowledges that this file is provided "AS IS"
12	* without any express or implied warranty:
13	* permission to use, copy, modify, and distribute this file
14	* for any purpose is hereby granted without fee, provided that
15	* the above copyright notice and this notice appears in all
16	* copies, and that the name of i-cubed limited not be used in
17	* advertising or publicity pertaining to distribution of the
18	* software without specific, written prior permission.
19	* i-cubed limited makes no representations about the suitability
20	* of this software for any purpose.
21	*
22	* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
23	*
24	* COPYRIGHT (c) 1989-1997.
25	* On-Line Applications Research Corporation (OAR).
26	*
27	* The license and distribution terms for this file may in
28	* the file LICENSE in this distribution or at
29	* http://www.rtems.com/license/LICENSE.
30	*
31	* $Id$
32	*/
33
34	#include <rtems/asm.h>
35	#include <rtems/powerpc/powerpc.h>
36	#include <rtems/powerpc/registers.h>
37
38	/*
39	* Offsets for various Contexts
40	*/
41	.set GP_1, 0
42	.set GP_2, (GP_1 + 4)
43	.set GP_13, (GP_2 + 4)
44	.set GP_14, (GP_13 + 4)
45
46	.set GP_15, (GP_14 + 4)
47	.set GP_16, (GP_15 + 4)
48	.set GP_17, (GP_16 + 4)
49	.set GP_18, (GP_17 + 4)
50
51	.set GP_19, (GP_18 + 4)
52	.set GP_20, (GP_19 + 4)
53	.set GP_21, (GP_20 + 4)
54	.set GP_22, (GP_21 + 4)
55
56	.set GP_23, (GP_22 + 4)
57	.set GP_24, (GP_23 + 4)
58	.set GP_25, (GP_24 + 4)
59	.set GP_26, (GP_25 + 4)
60
61	.set GP_27, (GP_26 + 4)
62	.set GP_28, (GP_27 + 4)
63	.set GP_29, (GP_28 + 4)
64	.set GP_30, (GP_29 + 4)
65
66	.set GP_31, (GP_30 + 4)
67	.set GP_CR, (GP_31 + 4)
68	.set GP_PC, (GP_CR + 4)
69	.set GP_MSR, (GP_PC + 4)
70
71	#if (PPC_HAS_DOUBLE==1)
72	.set FP_SIZE, 8
73	#define LDF lfd
74	#define STF stfd
75	#else
76	.set FP_SIZE, 4
77	#define LDF lfs
78	#define STF stfs
79	#endif
80
81	.set FP_0, 0
82	.set FP_1, (FP_0 + FP_SIZE)
83	.set FP_2, (FP_1 + FP_SIZE)
84	.set FP_3, (FP_2 + FP_SIZE)
85	.set FP_4, (FP_3 + FP_SIZE)
86	.set FP_5, (FP_4 + FP_SIZE)
87	.set FP_6, (FP_5 + FP_SIZE)
88	.set FP_7, (FP_6 + FP_SIZE)
89	.set FP_8, (FP_7 + FP_SIZE)
90	.set FP_9, (FP_8 + FP_SIZE)
91	.set FP_10, (FP_9 + FP_SIZE)
92	.set FP_11, (FP_10 + FP_SIZE)
93	.set FP_12, (FP_11 + FP_SIZE)
94	.set FP_13, (FP_12 + FP_SIZE)
95	.set FP_14, (FP_13 + FP_SIZE)
96	.set FP_15, (FP_14 + FP_SIZE)
97	.set FP_16, (FP_15 + FP_SIZE)
98	.set FP_17, (FP_16 + FP_SIZE)
99	.set FP_18, (FP_17 + FP_SIZE)
100	.set FP_19, (FP_18 + FP_SIZE)
101	.set FP_20, (FP_19 + FP_SIZE)
102	.set FP_21, (FP_20 + FP_SIZE)
103	.set FP_22, (FP_21 + FP_SIZE)
104	.set FP_23, (FP_22 + FP_SIZE)
105	.set FP_24, (FP_23 + FP_SIZE)
106	.set FP_25, (FP_24 + FP_SIZE)
107	.set FP_26, (FP_25 + FP_SIZE)
108	.set FP_27, (FP_26 + FP_SIZE)
109	.set FP_28, (FP_27 + FP_SIZE)
110	.set FP_29, (FP_28 + FP_SIZE)
111	.set FP_30, (FP_29 + FP_SIZE)
112	.set FP_31, (FP_30 + FP_SIZE)
113	.set FP_FPSCR, (FP_31 + FP_SIZE)
114
115	.set IP_LINK, 0
116	.set IP_0, (IP_LINK + 8)
117	.set IP_2, (IP_0 + 4)
118
119	.set IP_3, (IP_2 + 4)
120	.set IP_4, (IP_3 + 4)
121	.set IP_5, (IP_4 + 4)
122	.set IP_6, (IP_5 + 4)
123
124	.set IP_7, (IP_6 + 4)
125	.set IP_8, (IP_7 + 4)
126	.set IP_9, (IP_8 + 4)
127	.set IP_10, (IP_9 + 4)
128
129	.set IP_11, (IP_10 + 4)
130	.set IP_12, (IP_11 + 4)
131	.set IP_13, (IP_12 + 4)
132	.set IP_28, (IP_13 + 4)
133
134	.set IP_29, (IP_28 + 4)
135	.set IP_30, (IP_29 + 4)
136	.set IP_31, (IP_30 + 4)
137	.set IP_CR, (IP_31 + 4)
138
139	.set IP_CTR, (IP_CR + 4)
140	.set IP_XER, (IP_CTR + 4)
141	.set IP_LR, (IP_XER + 4)
142	.set IP_PC, (IP_LR + 4)
143
144	.set IP_MSR, (IP_PC + 4)
145	.set IP_END, (IP_MSR + 16)
146
147	BEGIN_CODE
148	/*
149	* _CPU_Context_save_fp_context
150	*
151	* This routine is responsible for saving the FP context
152	* at *fp_context_ptr. If the point to load the FP context
153	* from is changed then the pointer is modified by this routine.
154	*
155	* Sometimes a macro implementation of this is in cpu.h which dereferences
156	* the ** and a similarly named routine in this file is passed something
157	* like a (Context_Control_fp *). The general rule on making this decision
158	* is to avoid writing assembly language.
159	*/
160
161	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
162	PUBLIC_PROC (_CPU_Context_save_fp)
163	PROC (_CPU_Context_save_fp):
164	#if (PPC_HAS_FPU == 1)
165	/* A FP context switch may occur in an ISR or exception handler when the FPU is not
166	* available. Therefore, we must explicitely enable it here!
167	*/
168	mfmsr r4
169	andi. r5,r4,MSR_FP
170	bne 1f
171	ori r5,r4,MSR_FP
172	mtmsr r5
173	isync
174	1:
175	lwz r3, 0(r3)
176	STF f0, FP_0(r3)
177	STF f1, FP_1(r3)
178	STF f2, FP_2(r3)
179	STF f3, FP_3(r3)
180	STF f4, FP_4(r3)
181	STF f5, FP_5(r3)
182	STF f6, FP_6(r3)
183	STF f7, FP_7(r3)
184	STF f8, FP_8(r3)
185	STF f9, FP_9(r3)
186	STF f10, FP_10(r3)
187	STF f11, FP_11(r3)
188	STF f12, FP_12(r3)
189	STF f13, FP_13(r3)
190	STF f14, FP_14(r3)
191	STF f15, FP_15(r3)
192	STF f16, FP_16(r3)
193	STF f17, FP_17(r3)
194	STF f18, FP_18(r3)
195	STF f19, FP_19(r3)
196	STF f20, FP_20(r3)
197	STF f21, FP_21(r3)
198	STF f22, FP_22(r3)
199	STF f23, FP_23(r3)
200	STF f24, FP_24(r3)
201	STF f25, FP_25(r3)
202	STF f26, FP_26(r3)
203	STF f27, FP_27(r3)
204	STF f28, FP_28(r3)
205	STF f29, FP_29(r3)
206	STF f30, FP_30(r3)
207	STF f31, FP_31(r3)
208	mffs f2
209	STF f2, FP_FPSCR(r3)
210	bne 1f
211	mtmsr r4
212	isync
213	1:
214	#endif
215	blr
216
217	/*
218	* _CPU_Context_restore_fp_context
219	*
220	* This routine is responsible for restoring the FP context
221	* at *fp_context_ptr. If the point to load the FP context
222	* from is changed then the pointer is modified by this routine.
223	*
224	* Sometimes a macro implementation of this is in cpu.h which dereferences
225	* the ** and a similarly named routine in this file is passed something
226	* like a (Context_Control_fp *). The general rule on making this decision
227	* is to avoid writing assembly language.
228	*/
229
230	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
231	PUBLIC_PROC (_CPU_Context_restore_fp)
232	PROC (_CPU_Context_restore_fp):
233	#if (PPC_HAS_FPU == 1)
234	lwz r3, 0(r3)
235	/* A FP context switch may occur in an ISR or exception handler when the FPU is not
236	* available. Therefore, we must explicitely enable it here!
237	*/
238	mfmsr r4
239	andi. r5,r4,MSR_FP
240	bne 1f
241	ori r5,r4,MSR_FP
242	mtmsr r5
243	isync
244	1:
245	LDF f2, FP_FPSCR(r3)
246	mtfsf 255, f2
247	LDF f0, FP_0(r3)
248	LDF f1, FP_1(r3)
249	LDF f2, FP_2(r3)
250	LDF f3, FP_3(r3)
251	LDF f4, FP_4(r3)
252	LDF f5, FP_5(r3)
253	LDF f6, FP_6(r3)
254	LDF f7, FP_7(r3)
255	LDF f8, FP_8(r3)
256	LDF f9, FP_9(r3)
257	LDF f10, FP_10(r3)
258	LDF f11, FP_11(r3)
259	LDF f12, FP_12(r3)
260	LDF f13, FP_13(r3)
261	LDF f14, FP_14(r3)
262	LDF f15, FP_15(r3)
263	LDF f16, FP_16(r3)
264	LDF f17, FP_17(r3)
265	LDF f18, FP_18(r3)
266	LDF f19, FP_19(r3)
267	LDF f20, FP_20(r3)
268	LDF f21, FP_21(r3)
269	LDF f22, FP_22(r3)
270	LDF f23, FP_23(r3)
271	LDF f24, FP_24(r3)
272	LDF f25, FP_25(r3)
273	LDF f26, FP_26(r3)
274	LDF f27, FP_27(r3)
275	LDF f28, FP_28(r3)
276	LDF f29, FP_29(r3)
277	LDF f30, FP_30(r3)
278	LDF f31, FP_31(r3)
279	bne 1f
280	mtmsr r4
281	isync
282	1:
283	#endif
284	blr
285
286	/* _CPU_Context_switch
287	*
288	* This routine performs a normal non-FP context switch.
289	*/
290	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
291	PUBLIC_PROC (_CPU_Context_switch)
292	PROC (_CPU_Context_switch):
293	sync
294	isync
295	/* This assumes that all the registers are in the given order */
296	#if ( BSP_DATA_CACHE_ENABLED )
297	#if PPC_CACHE_ALIGNMENT != 32
298	#error "code assumes PPC_CACHE_ALIGNMENT == 32!"
299	#endif
300	li r5, PPC_CACHE_ALIGNMENT
301	#endif
302	addi r9,r3,-4
303	#if ( BSP_DATA_CACHE_ENABLED )
304	dcbz r5, r9
305	#endif
306	stw r1, GP_1+4(r9)
307	stw r2, GP_2+4(r9)
308	#if (PPC_USE_MULTIPLE == 1)
309	addi r9, r9, GP_18+4
310	#if ( BSP_DATA_CACHE_ENABLED )
311	dcbz r5, r9
312	#endif
313	stmw r13, GP_13-GP_18(r9)
314	#else
315	stw r13, GP_13+4(r9)
316	stw r14, GP_14+4(r9)
317	stw r15, GP_15+4(r9)
318	stw r16, GP_16+4(r9)
319	stw r17, GP_17+4(r9)
320	stwu r18, GP_18+4(r9)
321	#if ( BSP_DATA_CACHE_ENABLED )
322	dcbz r5, r9
323	#endif
324	stw r19, GP_19-GP_18(r9)
325	stw r20, GP_20-GP_18(r9)
326	stw r21, GP_21-GP_18(r9)
327	stw r22, GP_22-GP_18(r9)
328	stw r23, GP_23-GP_18(r9)
329	stw r24, GP_24-GP_18(r9)
330	stw r25, GP_25-GP_18(r9)
331	stw r26, GP_26-GP_18(r9)
332	stw r27, GP_27-GP_18(r9)
333	stw r28, GP_28-GP_18(r9)
334	stw r29, GP_29-GP_18(r9)
335	stw r30, GP_30-GP_18(r9)
336	stw r31, GP_31-GP_18(r9)
337	#endif
338	#if ( BSP_DATA_CACHE_ENABLED )
339	dcbt r0, r4
340	#endif
341	mfcr r6
342	stw r6, GP_CR-GP_18(r9)
343	mflr r7
344	stw r7, GP_PC-GP_18(r9)
345	mfmsr r8
346	stw r8, GP_MSR-GP_18(r9)
347
348	#ifdef __ALTIVEC__
349	mr r14, r4
350	EXTERN_PROC(_CPU_Context_switch_altivec)
351	bl _CPU_Context_switch_altivec
352	mr r4, r14
353	#if ( BSP_DATA_CACHE_ENABLED )
354	li r5, PPC_CACHE_ALIGNMENT
355	#endif
356	#endif
357
358	#if ( BSP_DATA_CACHE_ENABLED )
359	dcbt r5, r4
360	#endif
361	lwz r1, GP_1(r4)
362	lwz r2, GP_2(r4)
363	#if (PPC_USE_MULTIPLE == 1)
364	addi r4, r4, GP_19
365	#if ( BSP_DATA_CACHE_ENABLED )
366	dcbt r5, r4
367	#endif
368	lmw r13, GP_13-GP_19(r4)
369	#else
370	lwz r13, GP_13(r4)
371	lwz r14, GP_14(r4)
372	lwz r15, GP_15(r4)
373	lwz r16, GP_16(r4)
374	lwz r17, GP_17(r4)
375	lwz r18, GP_18(r4)
376	lwzu r19, GP_19(r4)
377	#if ( BSP_DATA_CACHE_ENABLED )
378	dcbt r5, r4
379	#endif
380	lwz r20, GP_20-GP_19(r4)
381	lwz r21, GP_21-GP_19(r4)
382	lwz r22, GP_22-GP_19(r4)
383	lwz r23, GP_23-GP_19(r4)
384	lwz r24, GP_24-GP_19(r4)
385	lwz r25, GP_25-GP_19(r4)
386	lwz r26, GP_26-GP_19(r4)
387	lwz r27, GP_27-GP_19(r4)
388	lwz r28, GP_28-GP_19(r4)
389	lwz r29, GP_29-GP_19(r4)
390	lwz r30, GP_30-GP_19(r4)
391	lwz r31, GP_31-GP_19(r4)
392	#endif
393	lwz r6, GP_CR-GP_19(r4)
394	lwz r7, GP_PC-GP_19(r4)
395	lwz r8, GP_MSR-GP_19(r4)
396	mtcrf 255, r6
397	mtlr r7
398	mtmsr r8
399	isync
400
401	blr
402
403	/*
404	* _CPU_Context_restore
405	*
406	* This routine is generallu used only to restart self in an
407	* efficient manner. It may simply be a label in _CPU_Context_switch.
408	*
409	* NOTE: May be unnecessary to reload some registers.
410	*/
411	/*
412	* ACB: Don't worry about cache optimisation here - this is not THAT critical.
413	*/
414	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
415	PUBLIC_PROC (_CPU_Context_restore)
416	PROC (_CPU_Context_restore):
417	lwz r5, GP_CR(r3)
418	lwz r6, GP_PC(r3)
419	lwz r7, GP_MSR(r3)
420	mtcrf 255, r5
421	mtlr r6
422	mtmsr r7
423	isync
424	lwz r1, GP_1(r3)
425	lwz r2, GP_2(r3)
426	#if (PPC_USE_MULTIPLE == 1)
427	lmw r13, GP_13(r3)
428	#else
429	lwz r13, GP_13(r3)
430	lwz r14, GP_14(r3)
431	lwz r15, GP_15(r3)
432	lwz r16, GP_16(r3)
433	lwz r17, GP_17(r3)
434	lwz r18, GP_18(r3)
435	lwz r19, GP_19(r3)
436	lwz r20, GP_20(r3)
437	lwz r21, GP_21(r3)
438	lwz r22, GP_22(r3)
439	lwz r23, GP_23(r3)
440	lwz r24, GP_24(r3)
441	lwz r25, GP_25(r3)
442	lwz r26, GP_26(r3)
443	lwz r27, GP_27(r3)
444	lwz r28, GP_28(r3)
445	lwz r29, GP_29(r3)
446	lwz r30, GP_30(r3)
447	lwz r31, GP_31(r3)
448	#endif
449	#ifdef __ALTIVEC__
450	EXTERN_PROC(_CPU_Context_restore_altivec)
451	b _CPU_Context_restore_altivec
452	#endif
453	blr

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