[acc25ee] | 1 | |
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| 2 | /* cpu_asm.s 1.1 - 95/12/04 |
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| 3 | * |
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| 4 | * This file contains the assembly code for the PowerPC implementation |
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| 5 | * of RTEMS. |
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| 6 | * |
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| 7 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 10 | * |
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| 11 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 12 | * without any express or implied warranty: |
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| 13 | * permission to use, copy, modify, and distribute this file |
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| 14 | * for any purpose is hereby granted without fee, provided that |
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| 15 | * the above copyright notice and this notice appears in all |
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| 16 | * copies, and that the name of i-cubed limited not be used in |
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| 17 | * advertising or publicity pertaining to distribution of the |
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| 18 | * software without specific, written prior permission. |
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| 19 | * i-cubed limited makes no representations about the suitability |
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| 20 | * of this software for any purpose. |
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| 21 | * |
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| 22 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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| 23 | * |
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| 24 | * COPYRIGHT (c) 1989-1997. |
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| 25 | * On-Line Applications Research Corporation (OAR). |
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| 26 | * Copyright assigned to U.S. Government, 1994. |
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| 27 | * |
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| 28 | * The license and distribution terms for this file may in |
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| 29 | * the file LICENSE in this distribution or at |
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| 30 | * http://www.OARcorp.com/rtems/license.html. |
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| 31 | * |
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| 32 | * $Id$ |
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| 33 | */ |
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| 34 | |
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| 35 | #include <asm.h> |
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| 36 | |
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| 37 | /* |
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| 38 | * Offsets for various Contexts |
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| 39 | */ |
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| 40 | .set GP_1, 0 |
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| 41 | .set GP_2, (GP_1 + 4) |
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| 42 | .set GP_13, (GP_2 + 4) |
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| 43 | .set GP_14, (GP_13 + 4) |
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| 44 | |
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| 45 | .set GP_15, (GP_14 + 4) |
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| 46 | .set GP_16, (GP_15 + 4) |
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| 47 | .set GP_17, (GP_16 + 4) |
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| 48 | .set GP_18, (GP_17 + 4) |
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| 49 | |
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| 50 | .set GP_19, (GP_18 + 4) |
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| 51 | .set GP_20, (GP_19 + 4) |
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| 52 | .set GP_21, (GP_20 + 4) |
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| 53 | .set GP_22, (GP_21 + 4) |
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| 54 | |
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| 55 | .set GP_23, (GP_22 + 4) |
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| 56 | .set GP_24, (GP_23 + 4) |
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| 57 | .set GP_25, (GP_24 + 4) |
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| 58 | .set GP_26, (GP_25 + 4) |
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| 59 | |
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| 60 | .set GP_27, (GP_26 + 4) |
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| 61 | .set GP_28, (GP_27 + 4) |
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| 62 | .set GP_29, (GP_28 + 4) |
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| 63 | .set GP_30, (GP_29 + 4) |
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| 64 | |
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| 65 | .set GP_31, (GP_30 + 4) |
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| 66 | .set GP_CR, (GP_31 + 4) |
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| 67 | .set GP_PC, (GP_CR + 4) |
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| 68 | .set GP_MSR, (GP_PC + 4) |
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| 69 | |
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| 70 | .set FP_0, 0 |
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| 71 | .set FP_1, (FP_0 + 4) |
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| 72 | .set FP_2, (FP_1 + 4) |
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| 73 | .set FP_3, (FP_2 + 4) |
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| 74 | .set FP_4, (FP_3 + 4) |
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| 75 | .set FP_5, (FP_4 + 4) |
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| 76 | .set FP_6, (FP_5 + 4) |
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| 77 | .set FP_7, (FP_6 + 4) |
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| 78 | .set FP_8, (FP_7 + 4) |
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| 79 | .set FP_9, (FP_8 + 4) |
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| 80 | .set FP_10, (FP_9 + 4) |
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| 81 | .set FP_11, (FP_10 + 4) |
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| 82 | .set FP_12, (FP_11 + 4) |
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| 83 | .set FP_13, (FP_12 + 4) |
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| 84 | .set FP_14, (FP_13 + 4) |
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| 85 | .set FP_15, (FP_14 + 4) |
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| 86 | .set FP_16, (FP_15 + 4) |
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| 87 | .set FP_17, (FP_16 + 4) |
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| 88 | .set FP_18, (FP_17 + 4) |
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| 89 | .set FP_19, (FP_18 + 4) |
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| 90 | .set FP_20, (FP_19 + 4) |
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| 91 | .set FP_21, (FP_20 + 4) |
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| 92 | .set FP_22, (FP_21 + 4) |
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| 93 | .set FP_23, (FP_22 + 4) |
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| 94 | .set FP_24, (FP_23 + 4) |
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| 95 | .set FP_25, (FP_24 + 4) |
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| 96 | .set FP_26, (FP_25 + 4) |
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| 97 | .set FP_27, (FP_26 + 4) |
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| 98 | .set FP_28, (FP_27 + 4) |
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| 99 | .set FP_29, (FP_28 + 4) |
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| 100 | .set FP_30, (FP_29 + 4) |
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| 101 | .set FP_31, (FP_30 + 4) |
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| 102 | .set FP_FPSCR, (FP_31 + 4) |
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| 103 | |
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| 104 | .set IP_LINK, 0 |
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| 105 | .set IP_0, (IP_LINK + 8) |
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| 106 | .set IP_2, (IP_0 + 4) |
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| 107 | |
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| 108 | .set IP_3, (IP_2 + 4) |
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| 109 | .set IP_4, (IP_3 + 4) |
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| 110 | .set IP_5, (IP_4 + 4) |
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| 111 | .set IP_6, (IP_5 + 4) |
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| 112 | |
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| 113 | .set IP_7, (IP_6 + 4) |
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| 114 | .set IP_8, (IP_7 + 4) |
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| 115 | .set IP_9, (IP_8 + 4) |
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| 116 | .set IP_10, (IP_9 + 4) |
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| 117 | |
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| 118 | .set IP_11, (IP_10 + 4) |
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| 119 | .set IP_12, (IP_11 + 4) |
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| 120 | .set IP_13, (IP_12 + 4) |
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| 121 | .set IP_28, (IP_13 + 4) |
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| 122 | |
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| 123 | .set IP_29, (IP_28 + 4) |
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| 124 | .set IP_30, (IP_29 + 4) |
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| 125 | .set IP_31, (IP_30 + 4) |
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| 126 | .set IP_CR, (IP_31 + 4) |
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| 127 | |
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| 128 | .set IP_CTR, (IP_CR + 4) |
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| 129 | .set IP_XER, (IP_CTR + 4) |
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| 130 | .set IP_LR, (IP_XER + 4) |
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| 131 | .set IP_PC, (IP_LR + 4) |
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| 132 | |
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| 133 | .set IP_MSR, (IP_PC + 4) |
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| 134 | .set IP_END, (IP_MSR + 16) |
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| 135 | |
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| 136 | BEGIN_CODE |
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| 137 | /* |
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| 138 | * _CPU_Context_save_fp_context |
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| 139 | * |
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| 140 | * This routine is responsible for saving the FP context |
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| 141 | * at *fp_context_ptr. If the point to load the FP context |
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| 142 | * from is changed then the pointer is modified by this routine. |
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| 143 | * |
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| 144 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 145 | * the ** and a similarly named routine in this file is passed something |
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| 146 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 147 | * is to avoid writing assembly language. |
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| 148 | */ |
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| 149 | |
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| 150 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 151 | PUBLIC_PROC (_CPU_Context_save_fp) |
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| 152 | PROC (_CPU_Context_save_fp): |
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| 153 | #if (PPC_HAS_FPU == 1) |
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| 154 | lwz r3, 0(r3) |
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| 155 | stfs f0, FP_0(r3) |
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| 156 | stfs f1, FP_1(r3) |
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| 157 | stfs f2, FP_2(r3) |
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| 158 | stfs f3, FP_3(r3) |
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| 159 | stfs f4, FP_4(r3) |
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| 160 | stfs f5, FP_5(r3) |
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| 161 | stfs f6, FP_6(r3) |
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| 162 | stfs f7, FP_7(r3) |
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| 163 | stfs f8, FP_8(r3) |
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| 164 | stfs f9, FP_9(r3) |
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| 165 | stfs f10, FP_10(r3) |
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| 166 | stfs f11, FP_11(r3) |
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| 167 | stfs f12, FP_12(r3) |
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| 168 | stfs f13, FP_13(r3) |
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| 169 | stfs f14, FP_14(r3) |
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| 170 | stfs f15, FP_15(r3) |
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| 171 | stfs f16, FP_16(r3) |
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| 172 | stfs f17, FP_17(r3) |
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| 173 | stfs f18, FP_18(r3) |
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| 174 | stfs f19, FP_19(r3) |
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| 175 | stfs f20, FP_20(r3) |
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| 176 | stfs f21, FP_21(r3) |
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| 177 | stfs f22, FP_22(r3) |
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| 178 | stfs f23, FP_23(r3) |
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| 179 | stfs f24, FP_24(r3) |
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| 180 | stfs f25, FP_25(r3) |
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| 181 | stfs f26, FP_26(r3) |
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| 182 | stfs f27, FP_27(r3) |
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| 183 | stfs f28, FP_28(r3) |
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| 184 | stfs f29, FP_29(r3) |
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| 185 | stfs f30, FP_30(r3) |
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| 186 | stfs f31, FP_31(r3) |
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| 187 | mffs f2 |
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| 188 | stfs f2, FP_FPSCR(r3) |
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| 189 | #endif |
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| 190 | blr |
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| 191 | |
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| 192 | /* |
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| 193 | * _CPU_Context_restore_fp_context |
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| 194 | * |
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| 195 | * This routine is responsible for restoring the FP context |
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| 196 | * at *fp_context_ptr. If the point to load the FP context |
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| 197 | * from is changed then the pointer is modified by this routine. |
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| 198 | * |
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| 199 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 200 | * the ** and a similarly named routine in this file is passed something |
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| 201 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 202 | * is to avoid writing assembly language. |
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| 203 | */ |
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| 204 | |
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| 205 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 206 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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| 207 | PROC (_CPU_Context_restore_fp): |
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| 208 | #if (PPC_HAS_FPU == 1) |
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| 209 | lwz r3, 0(r3) |
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| 210 | lfs f2, FP_FPSCR(r3) |
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| 211 | mtfsf 255, f2 |
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| 212 | lfs f0, FP_0(r3) |
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| 213 | lfs f1, FP_1(r3) |
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| 214 | lfs f2, FP_2(r3) |
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| 215 | lfs f3, FP_3(r3) |
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| 216 | lfs f4, FP_4(r3) |
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| 217 | lfs f5, FP_5(r3) |
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| 218 | lfs f6, FP_6(r3) |
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| 219 | lfs f7, FP_7(r3) |
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| 220 | lfs f8, FP_8(r3) |
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| 221 | lfs f9, FP_9(r3) |
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| 222 | lfs f10, FP_10(r3) |
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| 223 | lfs f11, FP_11(r3) |
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| 224 | lfs f12, FP_12(r3) |
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| 225 | lfs f13, FP_13(r3) |
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| 226 | lfs f14, FP_14(r3) |
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| 227 | lfs f15, FP_15(r3) |
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| 228 | lfs f16, FP_16(r3) |
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| 229 | lfs f17, FP_17(r3) |
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| 230 | lfs f18, FP_18(r3) |
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| 231 | lfs f19, FP_19(r3) |
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| 232 | lfs f20, FP_20(r3) |
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| 233 | lfs f21, FP_21(r3) |
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| 234 | lfs f22, FP_22(r3) |
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| 235 | lfs f23, FP_23(r3) |
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| 236 | lfs f24, FP_24(r3) |
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| 237 | lfs f25, FP_25(r3) |
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| 238 | lfs f26, FP_26(r3) |
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| 239 | lfs f27, FP_27(r3) |
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| 240 | lfs f28, FP_28(r3) |
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| 241 | lfs f29, FP_29(r3) |
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| 242 | lfs f30, FP_30(r3) |
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| 243 | lfs f31, FP_31(r3) |
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| 244 | #endif |
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| 245 | blr |
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| 246 | |
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| 247 | |
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| 248 | /* _CPU_Context_switch |
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| 249 | * |
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| 250 | * This routine performs a normal non-FP context switch. |
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| 251 | */ |
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| 252 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 253 | PUBLIC_PROC (_CPU_Context_switch) |
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| 254 | PROC (_CPU_Context_switch): |
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| 255 | sync |
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| 256 | isync |
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| 257 | /* This assumes that all the registers are in the given order */ |
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| 258 | li r5, 32 |
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| 259 | addi r3,r3,-4 |
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| 260 | #if ( PPC_USE_DATA_CACHE ) |
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| 261 | dcbz r5, r3 |
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| 262 | #endif |
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| 263 | stw r1, GP_1+4(r3) |
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| 264 | stw r2, GP_2+4(r3) |
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| 265 | #if (PPC_USE_MULTIPLE == 1) |
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| 266 | addi r3, r3, GP_18+4 |
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| 267 | #if ( PPC_USE_DATA_CACHE ) |
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| 268 | dcbz r5, r3 |
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| 269 | #endif |
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| 270 | stmw r13, GP_13-GP_18(r3) |
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| 271 | #else |
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| 272 | stw r13, GP_13+4(r3) |
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| 273 | stw r14, GP_14+4(r3) |
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| 274 | stw r15, GP_15+4(r3) |
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| 275 | stw r16, GP_16+4(r3) |
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| 276 | stw r17, GP_17+4(r3) |
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| 277 | stwu r18, GP_18+4(r3) |
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| 278 | #if ( PPC_USE_DATA_CACHE ) |
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| 279 | dcbz r5, r3 |
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| 280 | #endif |
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| 281 | stw r19, GP_19-GP_18(r3) |
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| 282 | stw r20, GP_20-GP_18(r3) |
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| 283 | stw r21, GP_21-GP_18(r3) |
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| 284 | stw r22, GP_22-GP_18(r3) |
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| 285 | stw r23, GP_23-GP_18(r3) |
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| 286 | stw r24, GP_24-GP_18(r3) |
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| 287 | stw r25, GP_25-GP_18(r3) |
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| 288 | stw r26, GP_26-GP_18(r3) |
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| 289 | stw r27, GP_27-GP_18(r3) |
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| 290 | stw r28, GP_28-GP_18(r3) |
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| 291 | stw r29, GP_29-GP_18(r3) |
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| 292 | stw r30, GP_30-GP_18(r3) |
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| 293 | stw r31, GP_31-GP_18(r3) |
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| 294 | #endif |
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| 295 | #if ( PPC_USE_DATA_CACHE ) |
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| 296 | dcbt r0, r4 |
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| 297 | #endif |
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| 298 | mfcr r6 |
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| 299 | stw r6, GP_CR-GP_18(r3) |
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| 300 | mflr r7 |
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| 301 | stw r7, GP_PC-GP_18(r3) |
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| 302 | mfmsr r8 |
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| 303 | stw r8, GP_MSR-GP_18(r3) |
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| 304 | |
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| 305 | #if ( PPC_USE_DATA_CACHE ) |
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| 306 | dcbt r5, r4 |
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| 307 | #endif |
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| 308 | lwz r1, GP_1(r4) |
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| 309 | lwz r2, GP_2(r4) |
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| 310 | #if (PPC_USE_MULTIPLE == 1) |
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| 311 | addi r4, r4, GP_19 |
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| 312 | #if ( PPC_USE_DATA_CACHE ) |
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| 313 | dcbt r5, r4 |
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| 314 | #endif |
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| 315 | lmw r13, GP_13-GP_19(r4) |
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| 316 | #else |
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| 317 | lwz r13, GP_13(r4) |
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| 318 | lwz r14, GP_14(r4) |
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| 319 | lwz r15, GP_15(r4) |
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| 320 | lwz r16, GP_16(r4) |
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| 321 | lwz r17, GP_17(r4) |
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| 322 | lwz r18, GP_18(r4) |
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| 323 | lwzu r19, GP_19(r4) |
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| 324 | #if ( PPC_USE_DATA_CACHE ) |
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| 325 | dcbt r5, r4 |
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| 326 | #endif |
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| 327 | lwz r20, GP_20-GP_19(r4) |
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| 328 | lwz r21, GP_21-GP_19(r4) |
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| 329 | lwz r22, GP_22-GP_19(r4) |
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| 330 | lwz r23, GP_23-GP_19(r4) |
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| 331 | lwz r24, GP_24-GP_19(r4) |
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| 332 | lwz r25, GP_25-GP_19(r4) |
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| 333 | lwz r26, GP_26-GP_19(r4) |
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| 334 | lwz r27, GP_27-GP_19(r4) |
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| 335 | lwz r28, GP_28-GP_19(r4) |
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| 336 | lwz r29, GP_29-GP_19(r4) |
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| 337 | lwz r30, GP_30-GP_19(r4) |
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| 338 | lwz r31, GP_31-GP_19(r4) |
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| 339 | #endif |
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| 340 | lwz r6, GP_CR-GP_19(r4) |
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| 341 | lwz r7, GP_PC-GP_19(r4) |
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| 342 | lwz r8, GP_MSR-GP_19(r4) |
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| 343 | mtcrf 255, r6 |
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| 344 | mtlr r7 |
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| 345 | mtmsr r8 |
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| 346 | |
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| 347 | blr |
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| 348 | |
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| 349 | /* |
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| 350 | * _CPU_Context_restore |
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| 351 | * |
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| 352 | * This routine is generallu used only to restart self in an |
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| 353 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 354 | * |
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| 355 | * NOTE: May be unnecessary to reload some registers. |
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| 356 | */ |
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| 357 | /* |
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| 358 | * ACB: Don't worry about cache optimisation here - this is not THAT critical. |
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| 359 | */ |
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| 360 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 361 | PUBLIC_PROC (_CPU_Context_restore) |
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| 362 | PROC (_CPU_Context_restore): |
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| 363 | lwz r5, GP_CR(r3) |
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| 364 | lwz r6, GP_PC(r3) |
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| 365 | lwz r7, GP_MSR(r3) |
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| 366 | mtcrf 255, r5 |
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| 367 | mtlr r6 |
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| 368 | mtmsr r7 |
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| 369 | lwz r1, GP_1(r3) |
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| 370 | lwz r2, GP_2(r3) |
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| 371 | #if (PPC_USE_MULTIPLE == 1) |
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| 372 | lmw r13, GP_13(r3) |
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| 373 | #else |
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| 374 | lwz r13, GP_13(r3) |
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| 375 | lwz r14, GP_14(r3) |
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| 376 | lwz r15, GP_15(r3) |
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| 377 | lwz r16, GP_16(r3) |
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| 378 | lwz r17, GP_17(r3) |
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| 379 | lwz r18, GP_18(r3) |
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| 380 | lwz r19, GP_19(r3) |
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| 381 | lwz r20, GP_20(r3) |
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| 382 | lwz r21, GP_21(r3) |
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| 383 | lwz r22, GP_22(r3) |
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| 384 | lwz r23, GP_23(r3) |
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| 385 | lwz r24, GP_24(r3) |
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| 386 | lwz r25, GP_25(r3) |
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| 387 | lwz r26, GP_26(r3) |
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| 388 | lwz r27, GP_27(r3) |
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| 389 | lwz r28, GP_28(r3) |
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| 390 | lwz r29, GP_29(r3) |
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| 391 | lwz r30, GP_30(r3) |
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| 392 | lwz r31, GP_31(r3) |
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| 393 | #endif |
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| 394 | |
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| 395 | blr |
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| 396 | |
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