source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c @ ab504d3

4.104.114.84.95
Last change on this file since ab504d3 was ab504d3, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 18, 2003 at 7:22:33 PM

2003-03-18 Till Straumann <strauman@…>

PR 356/bsps

  • cpu.c: This patch makes RTEMS/PowerPC eabi compliant.
  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *  $Id$
29 */
30
31#include <rtems/system.h>
32#include <rtems/score/isr.h>
33#include <rtems/score/context.h>
34#include <rtems/score/thread.h>
35#include <rtems/score/interr.h>
36
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS:
43 *    cpu_table       - CPU table to initialize
44 *    thread_dispatch - address of disptaching routine
45 */
46
47void _CPU_Initialize(
48  rtems_cpu_table  *cpu_table,
49  void      (*thread_dispatch)      /* ignored on this CPU */
50)
51{
52  _CPU_Table = *cpu_table;
53}
54
55/*PAGE
56 *
57 *  _CPU_Context_Initialize
58 */
59
60void _CPU_Context_Initialize(
61  Context_Control  *the_context,
62  unsigned32       *stack_base,
63  unsigned32        size,
64  unsigned32        new_level,
65  void             *entry_point,
66  boolean           is_fp
67)
68{
69  unsigned32 msr_value;
70  unsigned32 sp;
71
72  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
73
74  sp &= ~(CPU_STACK_ALIGNMENT-1);
75
76  *((unsigned32 *)sp) = 0;
77  the_context->gpr1 = sp;
78   
79  _CPU_MSR_GET( msr_value );
80
81  if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
82    msr_value |= MSR_EE;
83  }
84  else {
85    msr_value &= ~MSR_EE;
86  }
87
88  the_context->msr = msr_value;
89
90  /*
91   *  The FP bit of the MSR should only be enabled if this is a floating
92   *  point task.  Unfortunately, the vfprintf_r routine in newlib
93   *  ends up pushing a floating point register regardless of whether or
94   *  not a floating point number is being printed.  Serious restructuring
95   *  of vfprintf.c will be required to avoid this behavior.  At this
96   *  time (7 July 1997), this restructuring is not being done.
97   */
98
99  /* Till Straumann: For deferred FPContext save/restore, make sure integer
100   *                 tasks have no FPU access in order to catch violations.
101   *                 Otherwise, the FP registers may be corrupted.
102   *                             Since we set the_contex->msr using our current MSR,
103   *                             we must make sure MSR_FP is off if (!is_fp)...
104   */
105#if defined(CPU_USE_DEFERRED_FP_SWITCH) && (CPU_USE_DEFERRED_FP_SWITCH==TRUE)
106  if ( is_fp )
107#endif
108    the_context->msr |= PPC_MSR_FP;
109#if defined(CPU_USE_DEFERRED_FP_SWITCH) && (CPU_USE_DEFERRED_FP_SWITCH==TRUE)
110  else
111        the_context->msr &= ~PPC_MSR_FP;
112#endif
113
114  the_context->pc = (unsigned32)entry_point;
115
116#if (PPC_ABI == PPC_ABI_SVR4)
117  { unsigned    r13 = 0;
118    asm volatile ("mr %0, 13" : "=r" ((r13)));
119   
120    the_context->gpr13 = r13;
121  }
122#elif (PPC_ABI == PPC_ABI_EABI)
123  { unsigned32  r2 = 0;
124    unsigned    r13 = 0;
125    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
126 
127    the_context->gpr2 = r2;
128    the_context->gpr13 = r13;
129  }
130#else
131#error unsupported PPC_ABI
132#endif
133}
134
135
136
137/*PAGE
138 *
139 *  _CPU_Install_interrupt_stack
140 */
141
142void _CPU_Install_interrupt_stack( void )
143{
144}
145
146/*PAGE
147 *
148 *  This is the PowerPC specific implementation of the routine which
149 *  returns TRUE if an interrupt is in progress.
150 */
151
152boolean _ISR_Is_in_progress( void )
153{
154  /*
155   *  Until the patch on PR288 is in all new exception BSPs, this is
156   *  the safest thing to do.
157   */
158#ifdef mpc8260
159  return (_ISR_Nest_level != 0);
160#else
161  register unsigned int isr_nesting_level;
162  /*
163   * Move from special purpose register 0 (mfspr SPRG0, r3)
164   */
165  asm volatile ("mfspr  %0, 272" : "=r" (isr_nesting_level));
166  return isr_nesting_level;
167#endif
168}
169
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