source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c @ a6f84b27

5
Last change on this file since a6f84b27 was a6f84b27, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 1, 2017 at 8:57:46 AM

powerpc: Add 64-bit context/interrupt support

Update #3082.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 */
4
5/*
6 *  Author:  Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be found in
27 *  the file LICENSE in this distribution or at
28 *  http://www.rtems.org/license/LICENSE.
29 */
30
31#include <string.h>
32
33#include <rtems/system.h>
34#include <rtems/score/isr.h>
35#include <rtems/score/context.h>
36#include <rtems/score/thread.h>
37#include <rtems/score/interr.h>
38#include <rtems/score/cpu.h>
39#include <rtems/score/tls.h>
40#include <rtems/powerpc/powerpc.h>
41
42/*  _CPU_Initialize
43 *
44 *  This routine performs processor dependent initialization.
45 */
46void _CPU_Initialize(void)
47{
48#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
49  _CPU_Initialize_altivec();
50#endif
51}
52
53/*
54 *  _CPU_Context_Initialize
55 */
56void _CPU_Context_Initialize(
57  Context_Control  *the_context,
58  void             *stack_base,
59  size_t            size,
60  uint32_t          new_level,
61  void             *entry_point,
62  bool              is_fp,
63  void             *tls_area
64)
65{
66  ppc_context *the_ppc_context;
67  uint32_t   msr_value;
68  uintptr_t  sp;
69  uintptr_t  stack_alignment;
70
71  sp = (uintptr_t) stack_base + size - PPC_MINIMUM_STACK_FRAME_SIZE;
72
73  stack_alignment = CPU_STACK_ALIGNMENT;
74  sp &= ~(stack_alignment - 1);
75
76  sp = (uintptr_t) memset((void *) sp, 0, PPC_MINIMUM_STACK_FRAME_SIZE);
77
78  _CPU_MSR_GET( msr_value );
79
80  the_ppc_context = ppc_get_context( the_context );
81
82  /*
83   * Setting the interrupt mask here is not strictly necessary
84   * since the IRQ level will be established from _Thread_Handler()
85   * again, as soon as the task starts execution.
86   * Because we have to establish a defined state anyways we
87   * can as well leave this code here.
88   * I.e., simply (and unconditionally) saying
89   *
90   *   msr_value &= ~ppc_interrupt_get_disable_mask();
91   *
92   * would be an alternative.
93   */
94
95  if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
96    msr_value |= ppc_interrupt_get_disable_mask();
97  }
98  else {
99    msr_value &= ~ppc_interrupt_get_disable_mask();
100  }
101
102#ifdef PPC_MULTILIB_FPU
103  /*
104   *  The FP bit of the MSR should only be enabled if this is a floating
105   *  point task.  Unfortunately, the vfprintf_r routine in newlib
106   *  ends up pushing a floating point register regardless of whether or
107   *  not a floating point number is being printed.  Serious restructuring
108   *  of vfprintf.c will be required to avoid this behavior.  At this
109   *  time (7 July 1997), this restructuring is not being done.
110   */
111  msr_value |= MSR_FP;
112#endif
113
114#ifdef PPC_MULTILIB_ALTIVEC
115  msr_value |= MSR_VE;
116
117  the_ppc_context->vrsave = 0;
118#endif
119
120  the_ppc_context->gpr1 = sp;
121  the_ppc_context->msr = msr_value;
122  the_ppc_context->lr = (uintptr_t) entry_point;
123  the_ppc_context->isr_dispatch_disable = 0;
124
125#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
126  _CPU_Context_initialize_altivec( the_ppc_context );
127#endif
128
129  if ( tls_area != NULL ) {
130    void *tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
131
132    the_ppc_context->tp = (uintptr_t) tls_block + 0x7000;
133  }
134}
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