1 | /* |
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2 | * PowerPC CPU Dependent Source |
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3 | * |
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4 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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5 | * |
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6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of i-cubed limited not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * i-cubed limited makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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20 | * |
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21 | * COPYRIGHT (c) 1989-1997. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * |
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24 | * The license and distribution terms for this file may be found in |
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25 | * the file LICENSE in this distribution or at |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | */ |
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28 | |
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29 | #include <string.h> |
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30 | |
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31 | #include <rtems/system.h> |
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32 | #include <rtems/score/isr.h> |
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33 | #include <rtems/score/context.h> |
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34 | #include <rtems/score/thread.h> |
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35 | #include <rtems/score/interr.h> |
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36 | #include <rtems/score/cpu.h> |
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37 | #include <rtems/powerpc/powerpc.h> |
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38 | |
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39 | /* _CPU_Initialize |
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40 | * |
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41 | * This routine performs processor dependent initialization. |
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42 | * |
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43 | * INPUT PARAMETERS: NONE |
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44 | */ |
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45 | |
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46 | void _CPU_Initialize(void) |
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47 | { |
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48 | /* Do nothing */ |
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49 | #ifdef __ALTIVEC__ |
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50 | _CPU_Initialize_altivec(); |
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51 | #endif |
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52 | } |
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53 | |
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54 | /*PAGE |
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55 | * |
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56 | * _CPU_Context_Initialize |
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57 | */ |
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58 | |
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59 | void _CPU_Context_Initialize( |
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60 | Context_Control *the_context, |
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61 | uint32_t *stack_base, |
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62 | uint32_t size, |
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63 | uint32_t new_level, |
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64 | void *entry_point, |
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65 | bool is_fp |
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66 | ) |
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67 | { |
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68 | uint32_t msr_value; |
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69 | uint32_t sp; |
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70 | |
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71 | sp = (uint32_t)stack_base + size - PPC_MINIMUM_STACK_FRAME_SIZE; |
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72 | |
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73 | sp &= ~(CPU_STACK_ALIGNMENT-1); |
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74 | |
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75 | *((uint32_t*)sp) = 0; |
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76 | |
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77 | _CPU_MSR_GET( msr_value ); |
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78 | |
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79 | /* |
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80 | * Setting the interrupt mask here is not strictly necessary |
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81 | * since the IRQ level will be established from _Thread_Handler() |
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82 | * again, as soon as the task starts execution. |
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83 | * Because we have to establish a defined state anyways we |
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84 | * can as well leave this code here. |
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85 | * I.e., simply (and unconditionally) saying |
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86 | * |
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87 | * msr_value &= ~ppc_interrupt_get_disable_mask(); |
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88 | * |
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89 | * would be an alternative. |
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90 | */ |
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91 | |
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92 | if (!(new_level & CPU_MODES_INTERRUPT_MASK)) { |
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93 | msr_value |= ppc_interrupt_get_disable_mask(); |
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94 | } |
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95 | else { |
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96 | msr_value &= ~ppc_interrupt_get_disable_mask(); |
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97 | } |
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98 | |
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99 | /* |
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100 | * The FP bit of the MSR should only be enabled if this is a floating |
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101 | * point task. Unfortunately, the vfprintf_r routine in newlib |
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102 | * ends up pushing a floating point register regardless of whether or |
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103 | * not a floating point number is being printed. Serious restructuring |
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104 | * of vfprintf.c will be required to avoid this behavior. At this |
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105 | * time (7 July 1997), this restructuring is not being done. |
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106 | */ |
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107 | |
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108 | /* Make sure integer tasks have no FPU access in order to |
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109 | * catch violations. Gcc may implicitely use the FPU and |
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110 | * data corruption may happen. |
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111 | * Since we set the_contex->msr using our current MSR, |
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112 | * we must make sure MSR_FP is off if (!is_fp)... |
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113 | * Unfortunately, this means that users of vfprintf_r have to use FP |
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114 | * tasks or fix vfprintf. Furthermore, users of int-only tasks |
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115 | * must prevent gcc from using the FPU (currently -msoft-float is the |
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116 | * only way...) |
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117 | */ |
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118 | if ( is_fp ) |
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119 | msr_value |= PPC_MSR_FP; |
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120 | else |
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121 | msr_value &= ~PPC_MSR_FP; |
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122 | |
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123 | memset( the_context, 0, sizeof( *the_context ) ); |
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124 | |
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125 | PPC_CONTEXT_SET_SP( the_context, sp ); |
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126 | PPC_CONTEXT_SET_PC( the_context, (uint32_t) entry_point ); |
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127 | PPC_CONTEXT_SET_MSR( the_context, msr_value ); |
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128 | |
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129 | #ifndef __SPE__ |
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130 | #if (PPC_ABI == PPC_ABI_SVR4) |
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131 | /* |
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132 | * SVR4 says R2 is for 'system-reserved' use; it cannot hurt to |
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133 | * propagate R2 to all task contexts. |
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134 | */ |
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135 | { uint32_t r2 = 0; |
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136 | unsigned r13 = 0; |
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137 | __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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138 | |
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139 | the_context->gpr2 = r2; |
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140 | the_context->gpr13 = r13; |
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141 | } |
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142 | #elif (PPC_ABI == PPC_ABI_EABI) |
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143 | { uint32_t r2 = 0; |
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144 | unsigned r13 = 0; |
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145 | __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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146 | |
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147 | the_context->gpr2 = r2; |
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148 | the_context->gpr13 = r13; |
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149 | } |
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150 | #else |
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151 | #error unsupported PPC_ABI |
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152 | #endif |
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153 | #endif /* __SPE__ */ |
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154 | |
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155 | #ifdef __ALTIVEC__ |
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156 | _CPU_Context_initialize_altivec(the_context); |
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157 | #endif |
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158 | } |
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159 | |
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160 | /*PAGE |
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161 | * |
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162 | * _CPU_Install_interrupt_stack |
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163 | */ |
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164 | |
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165 | void _CPU_Install_interrupt_stack( void ) |
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166 | { |
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167 | } |
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168 | |
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169 | /* _CPU_ISR_install_vector |
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170 | * |
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171 | * This kernel routine installs the RTEMS handler for the |
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172 | * specified vector. |
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173 | * |
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174 | * Input parameters: |
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175 | * vector - interrupt vector number |
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176 | * old_handler - former ISR for this vector number |
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177 | * new_handler - replacement ISR for this vector number |
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178 | * |
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179 | * Output parameters: NONE |
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180 | */ |
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181 | |
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182 | void _CPU_ISR_install_vector( |
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183 | uint32_t vector, |
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184 | proc_ptr new_handler, |
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185 | proc_ptr *old_handler |
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186 | ) |
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187 | { |
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188 | BSP_panic("_CPU_ISR_install_vector called\n"); |
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189 | } |
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