source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h @ e71a3a84

4.115
Last change on this file since e71a3a84 was e71a3a84, checked in by Joel Sherrill <joel.sherrill@…>, on 01/28/11 at 20:38:13

2011-01-28 Joel Sherrill <joel.sherrilL@…>

  • mpc5xx/exceptions/raw_exception.c, mpc5xx/exceptions/raw_exception.h, mpc5xx/include/console.h, mpc5xx/include/mpc5xx.h, mpc5xx/irq/irq.c, mpc5xx/irq/irq.h, mpc5xx/irq/irq_asm.S, mpc5xx/vectors/vectors.h, mpc5xx/vectors/vectors_init.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, new-exceptions/bspsupport/irq.c, new-exceptions/bspsupport/irq_supp.h, new-exceptions/bspsupport/nested_irq_test.c, new-exceptions/bspsupport/ppc_exc_address.c, new-exceptions/bspsupport/ppc_exc_categories.c, new-exceptions/bspsupport/ppc_exc_global_handler.c, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/ppc_exc_prologue.c, new-exceptions/bspsupport/ppc_exc_test.c, new-exceptions/bspsupport/vectors.h, shared/include/byteorder.h, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/include/io.h, shared/include/mmu.h, shared/include/page.h, shared/include/pgtable.h, shared/include/spr.h: Fix typo where license said found in found in.
  • Property mode set to 100644
File size: 14.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 * @ingroup ppc_exc_frame
6 *
7 * @brief PowerPC Exceptions API.
8 */
9
10/*
11 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
12 *                    Canon Centre Recherche France.
13 *
14 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
15 *
16 * Copyright (C) 2009 embedded brains GmbH.
17 *
18 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
19 * to support 603, 603e, 604, 604e exceptions
20 *
21 * Moved to "libcpu/powerpc/new-exceptions" and consolidated
22 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
23 * to be common for all PPCs with new exceptions.
24 *
25 * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h".
26 * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h".
27 *
28 * The license and distribution terms for this file may be
29 * found in the file LICENSE in this distribution or at
30 * http://www.rtems.com/license/LICENSE.
31 *
32 * $Id$
33 */
34
35/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
36
37#ifndef LIBCPU_VECTORS_H
38#define LIBCPU_VECTORS_H
39
40#include <libcpu/powerpc-utility.h>
41
42/**
43 * @defgroup ppc_exc PowerPC Exceptions
44 *
45 * @brief XXX
46 *
47 * @{
48 */
49
50#define ASM_RESET_VECTOR                     0x01
51#define ASM_MACH_VECTOR                      0x02
52#define ASM_PROT_VECTOR                      0x03
53#define ASM_ISI_VECTOR                       0x04
54#define ASM_EXT_VECTOR                       0x05
55#define ASM_ALIGN_VECTOR                     0x06
56#define ASM_PROG_VECTOR                      0x07
57#define ASM_FLOAT_VECTOR                     0x08
58#define ASM_DEC_VECTOR                       0x09
59#define ASM_SYS_VECTOR                       0x0C
60#define ASM_TRACE_VECTOR                     0x0D
61
62#define ASM_PPC405_APU_UNAVAIL_VECTOR        ASM_60X_VEC_ASSIST_VECTOR
63
64#define ASM_8XX_FLOATASSIST_VECTOR           0x0E
65#define ASM_8XX_SOFTEMUL_VECTOR              0x10
66#define ASM_8XX_ITLBMISS_VECTOR              0x11
67#define ASM_8XX_DTLBMISS_VECTOR              0x12
68#define ASM_8XX_ITLBERROR_VECTOR             0x13
69#define ASM_8XX_DTLBERROR_VECTOR             0x14
70#define ASM_8XX_DBREAK_VECTOR                0x1C
71#define ASM_8XX_IBREAK_VECTOR                0x1D
72#define ASM_8XX_PERIFBREAK_VECTOR            0x1E
73#define ASM_8XX_DEVPORT_VECTOR               0x1F
74
75#define ASM_5XX_FLOATASSIST_VECTOR           0x0E
76#define ASM_5XX_SOFTEMUL_VECTOR              0x10
77#define ASM_5XX_IPROT_VECTOR                 0x13
78#define ASM_5XX_DPROT_VECTOR                 0x14
79#define ASM_5XX_DBREAK_VECTOR                0x1C
80#define ASM_5XX_IBREAK_VECTOR                0x1D
81#define ASM_5XX_MEBREAK_VECTOR               0x1E
82#define ASM_5XX_NMEBREAK_VECTOR              0x1F
83
84#define ASM_60X_VEC_VECTOR                   0x0A
85#define ASM_60X_PERFMON_VECTOR               0x0F
86#define ASM_60X_IMISS_VECTOR                 0x10
87#define ASM_60X_DLMISS_VECTOR                0x11
88#define ASM_60X_DSMISS_VECTOR                0x12
89#define ASM_60X_ADDR_VECTOR                  0x13
90#define ASM_60X_SYSMGMT_VECTOR               0x14
91#define ASM_60X_VEC_ASSIST_VECTOR            0x16
92#define ASM_60X_ITM_VECTOR                   0x17
93
94/* Book E */
95#define ASM_BOOKE_CRIT_VECTOR                0x01
96/* We could use the std. decrementer vector # on bookE, too,
97 * but the bookE decrementer has slightly different semantics
98 * so we use a different vector (which happens to be
99 * the PIT vector on the 405 which is like the booke decrementer)
100 */
101#define ASM_BOOKE_DEC_VECTOR                 0x10
102#define ASM_BOOKE_ITLBMISS_VECTOR            0x11
103#define ASM_BOOKE_DTLBMISS_VECTOR            0x12
104#define ASM_BOOKE_FIT_VECTOR                 0x13
105#define ASM_BOOKE_WDOG_VECTOR                0x14
106#define ASM_BOOKE_APU_VECTOR                 0x18
107#define ASM_BOOKE_DEBUG_VECTOR               ASM_TRACE_VECTOR
108
109/* e200 and e500 */
110#define ASM_E500_SPE_UNAVAILABLE_VECTOR      ASM_60X_VEC_VECTOR
111#define ASM_E500_EMB_FP_DATA_VECTOR          0x19
112#define ASM_E500_EMB_FP_ROUND_VECTOR         0x1A
113#define ASM_E500_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
114
115/* e300 */
116#define ASM_E300_CRIT_VECTOR                 0x0A
117#define ASM_E300_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
118#define ASM_E300_IMISS_VECTOR                ASM_60X_IMISS_VECTOR  /* Special case: Shadowed GPRs */
119#define ASM_E300_DLMISS_VECTOR               ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */
120#define ASM_E300_DSMISS_VECTOR               ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */
121#define ASM_E300_ADDR_VECTOR                 ASM_60X_ADDR_VECTOR
122#define ASM_E300_SYSMGMT_VECTOR              ASM_60X_SYSMGMT_VECTOR
123
124/*
125 * If you change that number make sure to adjust the wrapper code in ppc_exc.S
126 * and that ppc_exc_handler_table will be correctly initialized.
127 */
128#define LAST_VALID_EXC                       0x1F
129
130/* DO NOT USE -- this symbol is DEPRECATED
131 * (only used by libbsp/shared/vectors/vectors.S
132 * which should not be used by new BSPs).
133 */
134#define ASM_60X_VEC_VECTOR_OFFSET            0xf20
135
136#define ASM_PPC405_FIT_VECTOR_OFFSET         0x1010
137#define ASM_PPC405_WDOG_VECTOR_OFFSET        0x1020
138#define ASM_PPC405_TRACE_VECTOR_OFFSET       0x2000
139
140/** @} */
141
142/**
143 * @defgroup ppc_exc_frame PowerPC Exception Frame
144 *
145 * @brief XXX
146 *
147 * @{
148 */
149
150/*
151 * The callee (high level exception code written in C)
152 * will store the Link Registers (return address) at entry r1 + 4 !!!.
153 * So let room for it!!!.
154 */
155#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
156#define SRR0_FRAME_OFFSET 8
157#define SRR1_FRAME_OFFSET 12
158#define EXCEPTION_NUMBER_OFFSET 16
159#define GPR0_OFFSET 20
160#define GPR1_OFFSET 24
161#define GPR2_OFFSET 28
162#define GPR3_OFFSET 32
163#define GPR4_OFFSET 36
164#define GPR5_OFFSET 40
165#define GPR6_OFFSET 44
166#define GPR7_OFFSET 48
167#define GPR8_OFFSET 52
168#define GPR9_OFFSET 56
169#define GPR10_OFFSET 60
170#define GPR11_OFFSET 64
171#define GPR12_OFFSET 68
172#define GPR13_OFFSET 72
173#define GPR14_OFFSET 76
174#define GPR15_OFFSET 80
175#define GPR16_OFFSET 84
176#define GPR17_OFFSET 88
177#define GPR18_OFFSET 92
178#define GPR19_OFFSET 96
179#define GPR20_OFFSET 100
180#define GPR21_OFFSET 104
181#define GPR22_OFFSET 108
182#define GPR23_OFFSET 112
183#define GPR24_OFFSET 116
184#define GPR25_OFFSET 120
185#define GPR26_OFFSET 124
186#define GPR27_OFFSET 128
187#define GPR28_OFFSET 132
188#define GPR29_OFFSET 136
189#define GPR30_OFFSET 140
190#define GPR31_OFFSET 144
191#define EXC_CR_OFFSET 148
192#define EXC_CTR_OFFSET 152
193#define EXC_XER_OFFSET 156
194#define EXC_LR_OFFSET 160
195
196#define EXC_GENERIC_SIZE 176
197
198#ifdef __ALTIVEC__
199#define EXC_VEC_OFFSET EXC_GENERIC_SIZE
200#ifndef PPC_CACHE_ALIGNMENT
201#error "Missing include file!"
202#endif
203/*   20 volatile registers
204 * + cache-aligned area for vcsr, vrsave
205 * + area for alignment
206 */
207#define EXC_VEC_SIZE   (16*20 + 2*PPC_CACHE_ALIGNMENT)
208#else
209#define EXC_VEC_SIZE   (0)
210#endif
211
212/* Exception stack frame -> BSP_Exception_frame */
213#define FRAME_LINK_SPACE 8
214
215/*
216 * maintain the EABI requested 8 bytes aligment
217 * As SVR4 ABI requires 16, make it 16 (as some
218 * exception may need more registers to be processed...)
219 */
220#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE)
221
222/** @} */
223
224#ifndef ASM
225
226/**
227 * @ingroup ppc_exc_frame
228 *
229 * @{
230 */
231
232typedef struct {
233  unsigned EXC_SRR0;
234  unsigned EXC_SRR1;
235  unsigned _EXC_number;
236  unsigned GPR0;
237  unsigned GPR1;
238  unsigned GPR2;
239  unsigned GPR3;
240  unsigned GPR4;
241  unsigned GPR5;
242  unsigned GPR6;
243  unsigned GPR7;
244  unsigned GPR8;
245  unsigned GPR9;
246  unsigned GPR10;
247  unsigned GPR11;
248  unsigned GPR12;
249  unsigned GPR13;
250  unsigned GPR14;
251  unsigned GPR15;
252  unsigned GPR16;
253  unsigned GPR17;
254  unsigned GPR18;
255  unsigned GPR19;
256  unsigned GPR20;
257  unsigned GPR21;
258  unsigned GPR22;
259  unsigned GPR23;
260  unsigned GPR24;
261  unsigned GPR25;
262  unsigned GPR26;
263  unsigned GPR27;
264  unsigned GPR28;
265  unsigned GPR29;
266  unsigned GPR30;
267  unsigned GPR31;
268  unsigned EXC_CR;
269  unsigned EXC_CTR;
270  unsigned EXC_XER;
271  unsigned EXC_LR;
272  unsigned EXC_MSR;
273  unsigned EXC_DAR;
274} BSP_Exception_frame;
275
276/** @} */
277
278/**
279 * @ingroup ppc_exc
280 *
281 * @{
282 */
283
284/**
285 * @brief Global exception handler type.
286 */
287typedef void (*exception_handler_t)(BSP_Exception_frame*);
288
289/**
290 * @brief Global exception handler.
291 */
292extern exception_handler_t globalExceptHdl;
293
294/**
295 * @brief Default global exception handler.
296 */
297void C_exception_handler(BSP_Exception_frame* excPtr);
298
299void BSP_printStackTrace(BSP_Exception_frame *excPtr);
300
301/**
302 * @brief Exception categories.
303 *
304 * Exceptions of different categories use different SRR registers to save the
305 * machine state and do different things in the prologue and epilogue.
306 *
307 * For now, the CPU descriptions assume this fits into 8 bits.
308 */
309typedef enum {
310  PPC_EXC_INVALID = 0,
311  PPC_EXC_ASYNC = 1,
312  PPC_EXC_CLASSIC = 2,
313  PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
314  PPC_EXC_405_CRITICAL = 4,
315  PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
316  PPC_EXC_BOOKE_CRITICAL = 6,
317  PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
318  PPC_EXC_E500_MACHCHK  = 8,
319  PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC,
320  PPC_EXC_NAKED = 10
321} ppc_exc_category;
322
323/**
324 * @brief Categorie set type.
325 */
326typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1];
327
328static inline bool ppc_exc_is_valid_category(ppc_exc_category category)
329{
330  return (unsigned) category <= (unsigned) PPC_EXC_NAKED;
331}
332
333/**
334 * @brief Indicates if exception entry table resides in a writable memory.
335 *
336 * This variable is initialized to 'TRUE' by default;
337 * BSPs which have their vectors in ROM should set it
338 * to FALSE prior to initializing raw exceptions.
339 *
340 * I suspect the only candidate is the simulator.
341 * After all, the value of this variable is used to
342 * determine where to install the prologue code and
343 * installing to ROM on anyting that's real ROM
344 * will fail anyways.
345 *
346 * This should probably go away... (T.S. 2007/11/30)
347 */
348extern bool bsp_exceptions_in_RAM;
349
350/**
351 * @brief Vector base address for CPUs (for example e200 and e500) with IVPR
352 * and IVOR registers.
353 */
354extern uint32_t ppc_exc_vector_base;
355
356/**
357 * @brief Returns the entry address of the vector @a vector.
358 */
359void *ppc_exc_vector_address(unsigned vector);
360
361/**
362 * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if
363 * there is no category set available for this CPU.
364 */
365const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu);
366
367/**
368 * @brief Returns the category set for the current CPU, or @c NULL if there is
369 * no category set available for this CPU.
370 */
371static inline const ppc_exc_categories *ppc_exc_current_categories(void)
372{
373  return ppc_exc_categories_for_cpu(ppc_cpu_current());
374}
375
376/**
377 * @brief Returns the category for the vector @a vector using the category set
378 * @a categories.
379 */
380ppc_exc_category ppc_exc_category_for_vector(
381  const ppc_exc_categories *categories,
382  unsigned vector
383);
384
385/**
386 * @brief Makes a minimal prologue for the vector @a vector with the category
387 * @a category.
388 *
389 * The minimal prologue will be copied to @a prologue.  Not more than @a
390 * prologue_size bytes will be copied.  Returns the actual minimal prologue
391 * size in bytes in @a prologue_size.
392 *
393 * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made.
394 * @retval RTEMS_INVALID_ID Invalid vector number.
395 * @retval RTEMS_INVALID_NUMBER Invalid category.
396 * @retval RTEMS_INVALID_SIZE Prologue size to small.
397 */
398rtems_status_code ppc_exc_make_prologue(
399  unsigned vector,
400  ppc_exc_category category,
401  uint32_t *prologue,
402  size_t *prologue_size
403);
404
405/**
406 * @brief Initializes the exception handling.
407 *
408 * @retval RTEMS_SUCCESSFUL Successful initialization.
409 * @retval RTEMS_NOT_IMPLEMENTED No category set available for the current CPU.
410 * @retval RTEMS_NOT_CONFIGURED Register r13 does not point to the small data
411 * area anchor required by SVR4/EABI.
412 * @retval RTEMS_INTERNAL_ERROR Minimal prologue creation failed.
413 */
414rtems_status_code ppc_exc_initialize(
415  uint32_t interrupt_disable_mask,
416  uintptr_t interrupt_stack_begin,
417  uintptr_t interrupt_stack_size
418);
419
420/**
421 * @brief High-level exception handler type.
422 *
423 * Exception handlers should return zero if the exception was handled and
424 * normal execution may resume.
425 *
426 * They should return minus one to reject the exception resulting in the
427 * globalExcHdl() being called.
428 *
429 * Other return values are reserved.
430 */
431typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector);
432
433/**
434 * @brief Bits for MSR update.
435 *
436 * Bits in MSR that are enabled during execution of exception handlers / ISRs
437 * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
438 * be set to 0 during initialization)
439 *
440 * By default, the setting of these bits that is in effect when exception
441 * handling is initialized is used.
442 */
443extern uint32_t ppc_exc_msr_bits;
444
445/**
446 * @brief Cache write back check flag.
447 *
448 * (See README under CAVEATS). During initialization
449 * a check is performed to assert that write-back
450 * caching is enabled for memory accesses. If a BSP
451 * runs entirely without any caching then it should
452 * set this variable to zero prior to initializing
453 * exceptions in order to skip the test.
454 * NOTE: The code does NOT support mapping memory
455 *       with cache-attributes other than write-back
456 *       (unless the entire cache is physically disabled)
457 */
458extern uint32_t ppc_exc_cache_wb_check;
459
460/**
461 * @brief Set high-level exception handler.
462 *
463 * Hook C exception handlers.
464 *  - handlers for asynchronous exceptions run on the ISR stack
465 *    with thread-dispatching disabled.
466 *  - handlers for synchronous exceptions run on the task stack
467 *    with thread-dispatching enabled.
468 *
469 * If a particular slot is NULL then the traditional 'globalExcHdl' is used.
470 *
471 * ppc_exc_set_handler() registers a handler (returning 0 on success,
472 * -1 if the vector argument is too big).
473 *
474 * It is legal to set a NULL handler. This leads to the globalExcHdl
475 * being called if an exception for 'vector' occurs.
476 */
477rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl);
478
479/**
480 * @brief Returns the currently active high-level exception handler.
481 */
482ppc_exc_handler_t ppc_exc_get_handler(unsigned vector);
483
484/**
485 * @brief Function for DAR access.
486 *
487 * CPU support may store the address of a function here
488 * that can be used by the default exception handler to
489 * obtain fault-address info which is helpful. Unfortunately,
490 * the SPR holding this information is not uniform
491 * across PPC families so we need assistance from
492 * CPU support
493 */
494extern uint32_t (*ppc_exc_get_DAR)(void);
495
496void
497ppc_exc_wrapup(BSP_Exception_frame *f);
498
499/** @} */
500
501/*
502 * Compatibility with pc386
503 */
504typedef BSP_Exception_frame CPU_Exception_frame;
505typedef exception_handler_t cpuExcHandlerType;
506
507#endif /* ASM */
508
509#endif /* LIBCPU_VECTORS_H */
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