source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h @ 94e1931c

4.104.114.95
Last change on this file since 94e1931c was 94e1931c, checked in by Till Straumann <strauman@…>, on 12/08/07 at 23:43:24

2007-12-08 Till Straumann <strauman@…>

  • new-exceptions/bspsupport/, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_test.c, new-exceptions/bspsupport/vectors.h, new-exceptions/bspsupport/vectors_init.c, new-exceptions/bspsupport/irq.c, new-exceptions/bspsupport/ppc_exc_bspsupp.h, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/nested_irq_test.c: New files. Added 'middleware' code for helping BSPs implement exception and interrupt handling and implementing the 'new' RTEMS IRQ API (which I personally dislike).
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * vectors.h Exception frame related contant and API.
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to handle exceptions.
6 *
7 *  CopyRight (C) 1999 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15#ifndef LIBCPU_POWERPC_BSPSUPP_VECTORS_H
16#define LIBCPU_POWERPC_BSPSUPP_VECTORS_H
17#include <libcpu/raw_exception.h>
18
19/*
20 * The callee (high level exception code written in C)
21 * will store the Link Registers (return address) at entry r1 + 4 !!!.
22 * So let room for it!!!.
23 */
24#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
25#define SRR0_FRAME_OFFSET 8
26#define SRR1_FRAME_OFFSET 12
27#define EXCEPTION_NUMBER_OFFSET 16
28#define GPR0_OFFSET 20
29#define GPR1_OFFSET 24
30#define GPR2_OFFSET 28
31#define GPR3_OFFSET 32
32#define GPR4_OFFSET 36
33#define GPR5_OFFSET 40
34#define GPR6_OFFSET 44
35#define GPR7_OFFSET 48
36#define GPR8_OFFSET 52
37#define GPR9_OFFSET 56
38#define GPR10_OFFSET 60
39#define GPR11_OFFSET 64
40#define GPR12_OFFSET 68
41#define GPR13_OFFSET 72
42#define GPR14_OFFSET 76
43#define GPR15_OFFSET 80
44#define GPR16_OFFSET 84
45#define GPR17_OFFSET 88
46#define GPR18_OFFSET 92
47#define GPR19_OFFSET 96
48#define GPR20_OFFSET 100
49#define GPR21_OFFSET 104
50#define GPR22_OFFSET 108
51#define GPR23_OFFSET 112
52#define GPR24_OFFSET 116
53#define GPR25_OFFSET 120
54#define GPR26_OFFSET 124
55#define GPR27_OFFSET 128
56#define GPR28_OFFSET 132
57#define GPR29_OFFSET 136
58#define GPR30_OFFSET 140
59#define GPR31_OFFSET 144
60#define EXC_CR_OFFSET 148
61#define EXC_CTR_OFFSET 152
62#define EXC_XER_OFFSET 156
63#define EXC_LR_OFFSET 160
64/*
65 * maintain the EABI requested 8 bytes aligment
66 * As SVR4 ABI requires 16, make it 16 (as some
67 * exception may need more registers to be processed...)
68 */
69#define    EXCEPTION_FRAME_END 176
70
71#ifndef ASM
72
73/* codemove is like memmove, but it also gets the cache line size
74 * as 4th parameter to synchronize them. If this last parameter is
75 * zero, it performs more or less like memmove. No copy is performed if
76 * source and destination addresses are equal. However the caches
77 * are synchronized. Note that the size is always rounded up to the
78 * next mutiple of 4.
79 */
80extern void * codemove(void *, const void *, unsigned int, unsigned long);
81extern void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
82extern int  exception_always_enabled(const rtems_raw_except_connect_data* ptr);
83extern void initialize_exceptions();
84
85typedef struct _BSP_Exception_frame {
86  unsigned      EXC_SRR0;
87  unsigned      EXC_SRR1;
88  unsigned      _EXC_number;
89  unsigned      GPR0;
90  unsigned      GPR1;
91  unsigned      GPR2;
92  unsigned      GPR3;
93  unsigned      GPR4;
94  unsigned      GPR5;
95  unsigned      GPR6;
96  unsigned      GPR7;
97  unsigned      GPR8;
98  unsigned      GPR9;
99  unsigned      GPR10;
100  unsigned      GPR11;
101  unsigned      GPR12;
102  unsigned      GPR13;
103  unsigned      GPR14;
104  unsigned      GPR15;
105  unsigned      GPR16;
106  unsigned      GPR17;
107  unsigned      GPR18;
108  unsigned      GPR19;
109  unsigned      GPR20;
110  unsigned      GPR21;
111  unsigned      GPR22;
112  unsigned      GPR23;
113  unsigned      GPR24;
114  unsigned      GPR25;
115  unsigned      GPR26;
116  unsigned      GPR27;
117  unsigned      GPR28;
118  unsigned      GPR29;
119  unsigned      GPR30;
120  unsigned      GPR31;
121  unsigned      EXC_CR;
122  unsigned      EXC_CTR;
123  unsigned      EXC_XER;
124  unsigned      EXC_LR;
125  unsigned      EXC_MSR;
126  unsigned      EXC_DAR;
127} BSP_Exception_frame;
128
129typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
130extern exception_handler_t globalExceptHdl;
131/*
132 * Compatibility with pc386
133 */
134typedef BSP_Exception_frame CPU_Exception_frame;
135typedef exception_handler_t cpuExcHandlerType;
136
137/*
138 * dummy functions for exception interface
139 */
140void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
141int exception_always_enabled(const rtems_raw_except_connect_data* ptr);
142
143#endif /* ASM */
144
145#endif /* LIBCPU_POWERPC_BSPSUPP_VECTORS_H */
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