source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h @ 2888a65

4.115
Last change on this file since 2888a65 was 2888a65, checked in by Sebastian Huber <sebastian.huber@…>, on 02/17/11 at 11:19:43

2011-02-17 Sebastian Huber <sebastian.huber@…>

  • new-exceptions/bspsupport/vectors.h: Added defines PPC_EXC_GPR_TYPE, PPC_EXC_GPR_SIZE, PPC_EXC_GPR_OFFSET, PPC_EXC_MINIMAL_FRAME_SIZE, and PPC_EXC_FRAME_SIZE. Changed layout of BSP_Exception_frame.
  • Property mode set to 100644
File size: 15.6 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 * @ingroup ppc_exc_frame
6 *
7 * @brief PowerPC Exceptions API.
8 */
9
10/*
11 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
12 *                    Canon Centre Recherche France.
13 *
14 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
15 *
16 * Copyright (C) 2009 embedded brains GmbH.
17 *
18 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
19 * to support 603, 603e, 604, 604e exceptions
20 *
21 * Moved to "libcpu/powerpc/new-exceptions" and consolidated
22 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
23 * to be common for all PPCs with new exceptions.
24 *
25 * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h".
26 * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h".
27 *
28 * The license and distribution terms for this file may be
29 * found in the file LICENSE in this distribution or at
30 * http://www.rtems.com/license/LICENSE.
31 *
32 * $Id$
33 */
34
35/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
36
37#ifndef LIBCPU_VECTORS_H
38#define LIBCPU_VECTORS_H
39
40#include <libcpu/powerpc-utility.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46/**
47 * @defgroup ppc_exc PowerPC Exceptions
48 *
49 * @brief XXX
50 *
51 * @{
52 */
53
54#define ASM_RESET_VECTOR                     0x01
55#define ASM_MACH_VECTOR                      0x02
56#define ASM_PROT_VECTOR                      0x03
57#define ASM_ISI_VECTOR                       0x04
58#define ASM_EXT_VECTOR                       0x05
59#define ASM_ALIGN_VECTOR                     0x06
60#define ASM_PROG_VECTOR                      0x07
61#define ASM_FLOAT_VECTOR                     0x08
62#define ASM_DEC_VECTOR                       0x09
63#define ASM_SYS_VECTOR                       0x0C
64#define ASM_TRACE_VECTOR                     0x0D
65
66#define ASM_PPC405_APU_UNAVAIL_VECTOR        ASM_60X_VEC_ASSIST_VECTOR
67
68#define ASM_8XX_FLOATASSIST_VECTOR           0x0E
69#define ASM_8XX_SOFTEMUL_VECTOR              0x10
70#define ASM_8XX_ITLBMISS_VECTOR              0x11
71#define ASM_8XX_DTLBMISS_VECTOR              0x12
72#define ASM_8XX_ITLBERROR_VECTOR             0x13
73#define ASM_8XX_DTLBERROR_VECTOR             0x14
74#define ASM_8XX_DBREAK_VECTOR                0x1C
75#define ASM_8XX_IBREAK_VECTOR                0x1D
76#define ASM_8XX_PERIFBREAK_VECTOR            0x1E
77#define ASM_8XX_DEVPORT_VECTOR               0x1F
78
79#define ASM_5XX_FLOATASSIST_VECTOR           0x0E
80#define ASM_5XX_SOFTEMUL_VECTOR              0x10
81#define ASM_5XX_IPROT_VECTOR                 0x13
82#define ASM_5XX_DPROT_VECTOR                 0x14
83#define ASM_5XX_DBREAK_VECTOR                0x1C
84#define ASM_5XX_IBREAK_VECTOR                0x1D
85#define ASM_5XX_MEBREAK_VECTOR               0x1E
86#define ASM_5XX_NMEBREAK_VECTOR              0x1F
87
88#define ASM_60X_VEC_VECTOR                   0x0A
89#define ASM_60X_PERFMON_VECTOR               0x0F
90#define ASM_60X_IMISS_VECTOR                 0x10
91#define ASM_60X_DLMISS_VECTOR                0x11
92#define ASM_60X_DSMISS_VECTOR                0x12
93#define ASM_60X_ADDR_VECTOR                  0x13
94#define ASM_60X_SYSMGMT_VECTOR               0x14
95#define ASM_60X_VEC_ASSIST_VECTOR            0x16
96#define ASM_60X_ITM_VECTOR                   0x17
97
98/* Book E */
99#define ASM_BOOKE_CRIT_VECTOR                0x01
100/* We could use the std. decrementer vector # on bookE, too,
101 * but the bookE decrementer has slightly different semantics
102 * so we use a different vector (which happens to be
103 * the PIT vector on the 405 which is like the booke decrementer)
104 */
105#define ASM_BOOKE_DEC_VECTOR                 0x10
106#define ASM_BOOKE_ITLBMISS_VECTOR            0x11
107#define ASM_BOOKE_DTLBMISS_VECTOR            0x12
108#define ASM_BOOKE_FIT_VECTOR                 0x13
109#define ASM_BOOKE_WDOG_VECTOR                0x14
110#define ASM_BOOKE_APU_VECTOR                 0x18
111#define ASM_BOOKE_DEBUG_VECTOR               ASM_TRACE_VECTOR
112
113/* e200 and e500 */
114#define ASM_E500_SPE_UNAVAILABLE_VECTOR      ASM_60X_VEC_VECTOR
115#define ASM_E500_EMB_FP_DATA_VECTOR          0x19
116#define ASM_E500_EMB_FP_ROUND_VECTOR         0x1A
117#define ASM_E500_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
118
119/* e300 */
120#define ASM_E300_CRIT_VECTOR                 0x0A
121#define ASM_E300_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
122#define ASM_E300_IMISS_VECTOR                ASM_60X_IMISS_VECTOR  /* Special case: Shadowed GPRs */
123#define ASM_E300_DLMISS_VECTOR               ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */
124#define ASM_E300_DSMISS_VECTOR               ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */
125#define ASM_E300_ADDR_VECTOR                 ASM_60X_ADDR_VECTOR
126#define ASM_E300_SYSMGMT_VECTOR              ASM_60X_SYSMGMT_VECTOR
127
128/*
129 * If you change that number make sure to adjust the wrapper code in ppc_exc.S
130 * and that ppc_exc_handler_table will be correctly initialized.
131 */
132#define LAST_VALID_EXC                       0x1F
133
134/* DO NOT USE -- this symbol is DEPRECATED
135 * (only used by libbsp/shared/vectors/vectors.S
136 * which should not be used by new BSPs).
137 */
138#define ASM_60X_VEC_VECTOR_OFFSET            0xf20
139
140#define ASM_PPC405_FIT_VECTOR_OFFSET         0x1010
141#define ASM_PPC405_WDOG_VECTOR_OFFSET        0x1020
142#define ASM_PPC405_TRACE_VECTOR_OFFSET       0x2000
143
144/** @} */
145
146#define PPC_EXC_GPR_TYPE unsigned
147#define PPC_EXC_GPR_SIZE 4
148#define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_EXC_GPR_SIZE + 36)
149#define PPC_EXC_MINIMAL_FRAME_SIZE 96
150#define PPC_EXC_FRAME_SIZE 176
151
152/**
153 * @defgroup ppc_exc_frame PowerPC Exception Frame
154 *
155 * @brief XXX
156 *
157 * @{
158 */
159
160/*
161 * The callee (high level exception code written in C)
162 * will store the Link Registers (return address) at entry r1 + 4 !!!.
163 * So let room for it!!!.
164 */
165#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
166
167#define SRR0_FRAME_OFFSET 8
168#define SRR1_FRAME_OFFSET 12
169#define EXCEPTION_NUMBER_OFFSET 16
170#define EXC_CR_OFFSET 20
171#define EXC_CTR_OFFSET 24
172#define EXC_XER_OFFSET 28
173#define EXC_LR_OFFSET 32
174#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0)
175#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1)
176#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2)
177#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3)
178#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4)
179#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5)
180#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6)
181#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7)
182#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8)
183#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9)
184#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10)
185#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11)
186#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12)
187#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13)
188#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14)
189#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15)
190#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16)
191#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17)
192#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18)
193#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19)
194#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20)
195#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21)
196#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22)
197#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23)
198#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24)
199#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25)
200#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26)
201#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27)
202#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28)
203#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29)
204#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30)
205#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31)
206#define EXC_MSR_OFFSET PPC_EXC_GPR_OFFSET(32)
207#define EXC_DAR_OFFSET (4 + EXC_MSR_OFFSET)
208
209#define EXC_GENERIC_SIZE PPC_EXC_FRAME_SIZE
210
211#ifdef __ALTIVEC__
212#define EXC_VEC_OFFSET EXC_GENERIC_SIZE
213#ifndef PPC_CACHE_ALIGNMENT
214#error "Missing include file!"
215#endif
216/*   20 volatile registers
217 * + cache-aligned area for vcsr, vrsave
218 * + area for alignment
219 */
220#define EXC_VEC_SIZE   (16*20 + 2*PPC_CACHE_ALIGNMENT)
221#else
222#define EXC_VEC_SIZE   (0)
223#endif
224
225/* Exception stack frame -> BSP_Exception_frame */
226#define FRAME_LINK_SPACE 8
227
228/*
229 * maintain the EABI requested 8 bytes aligment
230 * As SVR4 ABI requires 16, make it 16 (as some
231 * exception may need more registers to be processed...)
232 */
233#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE)
234
235/** @} */
236
237#ifndef ASM
238
239/**
240 * @ingroup ppc_exc_frame
241 *
242 * @{
243 */
244
245typedef struct {
246  unsigned EXC_SRR0;
247  unsigned EXC_SRR1;
248  unsigned _EXC_number;
249  unsigned EXC_CR;
250  unsigned EXC_CTR;
251  unsigned EXC_XER;
252  unsigned EXC_LR;
253  PPC_EXC_GPR_TYPE GPR0;
254  PPC_EXC_GPR_TYPE GPR1;
255  PPC_EXC_GPR_TYPE GPR2;
256  PPC_EXC_GPR_TYPE GPR3;
257  PPC_EXC_GPR_TYPE GPR4;
258  PPC_EXC_GPR_TYPE GPR5;
259  PPC_EXC_GPR_TYPE GPR6;
260  PPC_EXC_GPR_TYPE GPR7;
261  PPC_EXC_GPR_TYPE GPR8;
262  PPC_EXC_GPR_TYPE GPR9;
263  PPC_EXC_GPR_TYPE GPR10;
264  PPC_EXC_GPR_TYPE GPR11;
265  PPC_EXC_GPR_TYPE GPR12;
266  PPC_EXC_GPR_TYPE GPR13;
267  PPC_EXC_GPR_TYPE GPR14;
268  PPC_EXC_GPR_TYPE GPR15;
269  PPC_EXC_GPR_TYPE GPR16;
270  PPC_EXC_GPR_TYPE GPR17;
271  PPC_EXC_GPR_TYPE GPR18;
272  PPC_EXC_GPR_TYPE GPR19;
273  PPC_EXC_GPR_TYPE GPR20;
274  PPC_EXC_GPR_TYPE GPR21;
275  PPC_EXC_GPR_TYPE GPR22;
276  PPC_EXC_GPR_TYPE GPR23;
277  PPC_EXC_GPR_TYPE GPR24;
278  PPC_EXC_GPR_TYPE GPR25;
279  PPC_EXC_GPR_TYPE GPR26;
280  PPC_EXC_GPR_TYPE GPR27;
281  PPC_EXC_GPR_TYPE GPR28;
282  PPC_EXC_GPR_TYPE GPR29;
283  PPC_EXC_GPR_TYPE GPR30;
284  PPC_EXC_GPR_TYPE GPR31;
285  unsigned EXC_MSR;
286  unsigned EXC_DAR;
287} BSP_Exception_frame;
288
289/** @} */
290
291/**
292 * @ingroup ppc_exc
293 *
294 * @{
295 */
296
297/**
298 * @brief Global exception handler type.
299 */
300typedef void (*exception_handler_t)(BSP_Exception_frame*);
301
302/**
303 * @brief Global exception handler.
304 */
305extern exception_handler_t globalExceptHdl;
306
307/**
308 * @brief Default global exception handler.
309 */
310void C_exception_handler(BSP_Exception_frame* excPtr);
311
312void BSP_printStackTrace(BSP_Exception_frame *excPtr);
313
314/**
315 * @brief Exception categories.
316 *
317 * Exceptions of different categories use different SRR registers to save the
318 * machine state and do different things in the prologue and epilogue.
319 *
320 * For now, the CPU descriptions assume this fits into 8 bits.
321 */
322typedef enum {
323  PPC_EXC_INVALID = 0,
324  PPC_EXC_ASYNC = 1,
325  PPC_EXC_CLASSIC = 2,
326  PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
327  PPC_EXC_405_CRITICAL = 4,
328  PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
329  PPC_EXC_BOOKE_CRITICAL = 6,
330  PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
331  PPC_EXC_E500_MACHCHK  = 8,
332  PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC,
333  PPC_EXC_NAKED = 10
334} ppc_exc_category;
335
336/**
337 * @brief Categorie set type.
338 */
339typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1];
340
341static inline bool ppc_exc_is_valid_category(ppc_exc_category category)
342{
343  return (unsigned) category <= (unsigned) PPC_EXC_NAKED;
344}
345
346/**
347 * @brief Indicates if exception entry table resides in a writable memory.
348 *
349 * This variable is initialized to 'TRUE' by default;
350 * BSPs which have their vectors in ROM should set it
351 * to FALSE prior to initializing raw exceptions.
352 *
353 * I suspect the only candidate is the simulator.
354 * After all, the value of this variable is used to
355 * determine where to install the prologue code and
356 * installing to ROM on anyting that's real ROM
357 * will fail anyways.
358 *
359 * This should probably go away... (T.S. 2007/11/30)
360 */
361extern bool bsp_exceptions_in_RAM;
362
363/**
364 * @brief Vector base address for CPUs (for example e200 and e500) with IVPR
365 * and IVOR registers.
366 */
367extern uint32_t ppc_exc_vector_base;
368
369/**
370 * @brief Returns the entry address of the vector @a vector.
371 */
372void *ppc_exc_vector_address(unsigned vector);
373
374/**
375 * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if
376 * there is no category set available for this CPU.
377 */
378const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu);
379
380/**
381 * @brief Returns the category set for the current CPU, or @c NULL if there is
382 * no category set available for this CPU.
383 */
384static inline const ppc_exc_categories *ppc_exc_current_categories(void)
385{
386  return ppc_exc_categories_for_cpu(ppc_cpu_current());
387}
388
389/**
390 * @brief Returns the category for the vector @a vector using the category set
391 * @a categories.
392 */
393ppc_exc_category ppc_exc_category_for_vector(
394  const ppc_exc_categories *categories,
395  unsigned vector
396);
397
398/**
399 * @brief Makes a minimal prologue for the vector @a vector with the category
400 * @a category.
401 *
402 * The minimal prologue will be copied to @a prologue.  Not more than @a
403 * prologue_size bytes will be copied.  Returns the actual minimal prologue
404 * size in bytes in @a prologue_size.
405 *
406 * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made.
407 * @retval RTEMS_INVALID_ID Invalid vector number.
408 * @retval RTEMS_INVALID_NUMBER Invalid category.
409 * @retval RTEMS_INVALID_SIZE Prologue size to small.
410 */
411rtems_status_code ppc_exc_make_prologue(
412  unsigned vector,
413  ppc_exc_category category,
414  uint32_t *prologue,
415  size_t *prologue_size
416);
417
418/**
419 * @brief Initializes the exception handling.
420 *
421 * @retval RTEMS_SUCCESSFUL Successful initialization.
422 * @retval RTEMS_NOT_IMPLEMENTED No category set available for the current CPU.
423 * @retval RTEMS_NOT_CONFIGURED Register r13 does not point to the small data
424 * area anchor required by SVR4/EABI.
425 * @retval RTEMS_INTERNAL_ERROR Minimal prologue creation failed.
426 */
427rtems_status_code ppc_exc_initialize(
428  uint32_t interrupt_disable_mask,
429  uintptr_t interrupt_stack_begin,
430  uintptr_t interrupt_stack_size
431);
432
433/**
434 * @brief High-level exception handler type.
435 *
436 * Exception handlers should return zero if the exception was handled and
437 * normal execution may resume.
438 *
439 * They should return minus one to reject the exception resulting in the
440 * globalExcHdl() being called.
441 *
442 * Other return values are reserved.
443 */
444typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector);
445
446/**
447 * @brief Bits for MSR update.
448 *
449 * Bits in MSR that are enabled during execution of exception handlers / ISRs
450 * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
451 * be set to 0 during initialization)
452 *
453 * By default, the setting of these bits that is in effect when exception
454 * handling is initialized is used.
455 */
456extern uint32_t ppc_exc_msr_bits;
457
458/**
459 * @brief Cache write back check flag.
460 *
461 * (See README under CAVEATS). During initialization
462 * a check is performed to assert that write-back
463 * caching is enabled for memory accesses. If a BSP
464 * runs entirely without any caching then it should
465 * set this variable to zero prior to initializing
466 * exceptions in order to skip the test.
467 * NOTE: The code does NOT support mapping memory
468 *       with cache-attributes other than write-back
469 *       (unless the entire cache is physically disabled)
470 */
471extern uint32_t ppc_exc_cache_wb_check;
472
473/**
474 * @brief Set high-level exception handler.
475 *
476 * Hook C exception handlers.
477 *  - handlers for asynchronous exceptions run on the ISR stack
478 *    with thread-dispatching disabled.
479 *  - handlers for synchronous exceptions run on the task stack
480 *    with thread-dispatching enabled.
481 *
482 * If a particular slot is NULL then the traditional 'globalExcHdl' is used.
483 *
484 * ppc_exc_set_handler() registers a handler (returning 0 on success,
485 * -1 if the vector argument is too big).
486 *
487 * It is legal to set a NULL handler. This leads to the globalExcHdl
488 * being called if an exception for 'vector' occurs.
489 */
490rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl);
491
492/**
493 * @brief Returns the currently active high-level exception handler.
494 */
495ppc_exc_handler_t ppc_exc_get_handler(unsigned vector);
496
497/**
498 * @brief Function for DAR access.
499 *
500 * CPU support may store the address of a function here
501 * that can be used by the default exception handler to
502 * obtain fault-address info which is helpful. Unfortunately,
503 * the SPR holding this information is not uniform
504 * across PPC families so we need assistance from
505 * CPU support
506 */
507extern uint32_t (*ppc_exc_get_DAR)(void);
508
509void
510ppc_exc_wrapup(BSP_Exception_frame *f);
511
512/** @} */
513
514/*
515 * Compatibility with pc386
516 */
517typedef BSP_Exception_frame CPU_Exception_frame;
518typedef exception_handler_t cpuExcHandlerType;
519
520#endif /* ASM */
521
522#ifdef __cplusplus
523}
524#endif
525
526#endif /* LIBCPU_VECTORS_H */
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