1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ppc_exc |
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5 | * @ingroup ppc_exc_frame |
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6 | * |
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7 | * @brief PowerPC Exceptions API. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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12 | * Canon Centre Recherche France. |
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13 | * |
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14 | * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> |
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15 | * |
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16 | * Copyright (C) 2009 embedded brains GmbH. |
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17 | * |
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18 | * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> |
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19 | * to support 603, 603e, 604, 604e exceptions |
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20 | * |
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21 | * Moved to "libcpu/powerpc/new-exceptions" and consolidated |
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22 | * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> |
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23 | * to be common for all PPCs with new exceptions. |
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24 | * |
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25 | * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". |
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26 | * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". |
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27 | * |
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28 | * The license and distribution terms for this file may be |
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29 | * found in the file LICENSE in this distribution or at |
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30 | * http://www.rtems.com/license/LICENSE. |
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31 | */ |
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32 | |
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33 | /* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */ |
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34 | |
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35 | #ifndef LIBCPU_VECTORS_H |
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36 | #define LIBCPU_VECTORS_H |
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37 | |
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38 | #include <libcpu/powerpc-utility.h> |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | /** |
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45 | * @defgroup ppc_exc PowerPC Exceptions |
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46 | * |
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47 | * @brief XXX |
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48 | * |
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49 | * @{ |
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50 | */ |
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51 | |
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52 | #define ASM_RESET_VECTOR 0x01 |
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53 | #define ASM_MACH_VECTOR 0x02 |
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54 | #define ASM_PROT_VECTOR 0x03 |
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55 | #define ASM_ISI_VECTOR 0x04 |
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56 | #define ASM_EXT_VECTOR 0x05 |
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57 | #define ASM_ALIGN_VECTOR 0x06 |
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58 | #define ASM_PROG_VECTOR 0x07 |
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59 | #define ASM_FLOAT_VECTOR 0x08 |
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60 | #define ASM_DEC_VECTOR 0x09 |
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61 | #define ASM_SYS_VECTOR 0x0C |
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62 | #define ASM_TRACE_VECTOR 0x0D |
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63 | |
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64 | #define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR |
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65 | |
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66 | #define ASM_8XX_FLOATASSIST_VECTOR 0x0E |
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67 | #define ASM_8XX_SOFTEMUL_VECTOR 0x10 |
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68 | #define ASM_8XX_ITLBMISS_VECTOR 0x11 |
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69 | #define ASM_8XX_DTLBMISS_VECTOR 0x12 |
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70 | #define ASM_8XX_ITLBERROR_VECTOR 0x13 |
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71 | #define ASM_8XX_DTLBERROR_VECTOR 0x14 |
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72 | #define ASM_8XX_DBREAK_VECTOR 0x1C |
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73 | #define ASM_8XX_IBREAK_VECTOR 0x1D |
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74 | #define ASM_8XX_PERIFBREAK_VECTOR 0x1E |
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75 | #define ASM_8XX_DEVPORT_VECTOR 0x1F |
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76 | |
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77 | #define ASM_5XX_FLOATASSIST_VECTOR 0x0E |
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78 | #define ASM_5XX_SOFTEMUL_VECTOR 0x10 |
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79 | #define ASM_5XX_IPROT_VECTOR 0x13 |
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80 | #define ASM_5XX_DPROT_VECTOR 0x14 |
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81 | #define ASM_5XX_DBREAK_VECTOR 0x1C |
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82 | #define ASM_5XX_IBREAK_VECTOR 0x1D |
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83 | #define ASM_5XX_MEBREAK_VECTOR 0x1E |
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84 | #define ASM_5XX_NMEBREAK_VECTOR 0x1F |
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85 | |
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86 | #define ASM_60X_VEC_VECTOR 0x0A |
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87 | #define ASM_60X_PERFMON_VECTOR 0x0F |
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88 | #define ASM_60X_IMISS_VECTOR 0x10 |
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89 | #define ASM_60X_DLMISS_VECTOR 0x11 |
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90 | #define ASM_60X_DSMISS_VECTOR 0x12 |
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91 | #define ASM_60X_ADDR_VECTOR 0x13 |
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92 | #define ASM_60X_SYSMGMT_VECTOR 0x14 |
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93 | #define ASM_60X_VEC_ASSIST_VECTOR 0x16 |
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94 | #define ASM_60X_ITM_VECTOR 0x17 |
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95 | |
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96 | /* Book E */ |
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97 | #define ASM_BOOKE_CRIT_VECTOR 0x01 |
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98 | /* We could use the std. decrementer vector # on bookE, too, |
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99 | * but the bookE decrementer has slightly different semantics |
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100 | * so we use a different vector (which happens to be |
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101 | * the PIT vector on the 405 which is like the booke decrementer) |
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102 | */ |
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103 | #define ASM_BOOKE_DEC_VECTOR 0x10 |
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104 | #define ASM_BOOKE_ITLBMISS_VECTOR 0x11 |
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105 | #define ASM_BOOKE_DTLBMISS_VECTOR 0x12 |
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106 | #define ASM_BOOKE_FIT_VECTOR 0x13 |
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107 | #define ASM_BOOKE_WDOG_VECTOR 0x14 |
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108 | #define ASM_BOOKE_APU_VECTOR 0x18 |
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109 | #define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR |
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110 | |
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111 | /* e200 and e500 */ |
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112 | #define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR |
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113 | #define ASM_E500_EMB_FP_DATA_VECTOR 0x19 |
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114 | #define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A |
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115 | #define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR |
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116 | |
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117 | /* e300 */ |
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118 | #define ASM_E300_CRIT_VECTOR 0x0A |
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119 | #define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR |
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120 | #define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */ |
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121 | #define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */ |
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122 | #define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */ |
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123 | #define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR |
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124 | #define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR |
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125 | |
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126 | /* |
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127 | * If you change that number make sure to adjust the wrapper code in ppc_exc.S |
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128 | * and that ppc_exc_handler_table will be correctly initialized. |
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129 | */ |
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130 | #define LAST_VALID_EXC 0x1F |
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131 | |
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132 | /* DO NOT USE -- this symbol is DEPRECATED |
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133 | * (only used by libbsp/shared/vectors/vectors.S |
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134 | * which should not be used by new BSPs). |
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135 | */ |
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136 | #define ASM_60X_VEC_VECTOR_OFFSET 0xf20 |
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137 | |
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138 | #define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010 |
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139 | #define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020 |
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140 | #define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000 |
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141 | |
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142 | /** @} */ |
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143 | |
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144 | #ifndef __SPE__ |
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145 | #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 36) |
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146 | #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4) |
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147 | #define PPC_EXC_MINIMAL_FRAME_SIZE 96 |
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148 | #define PPC_EXC_FRAME_SIZE 176 |
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149 | #else |
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150 | #define PPC_EXC_SPEFSCR_OFFSET 36 |
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151 | #define PPC_EXC_ACC_OFFSET 40 |
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152 | #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 48) |
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153 | #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4) |
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154 | #define PPC_EXC_MINIMAL_FRAME_SIZE 160 |
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155 | #define PPC_EXC_FRAME_SIZE 320 |
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156 | #endif |
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157 | |
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158 | /** |
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159 | * @defgroup ppc_exc_frame PowerPC Exception Frame |
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160 | * |
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161 | * @brief XXX |
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162 | * |
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163 | * @{ |
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164 | */ |
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165 | |
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166 | /* |
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167 | * The callee (high level exception code written in C) |
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168 | * will store the Link Registers (return address) at entry r1 + 4 !!!. |
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169 | * So let room for it!!!. |
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170 | */ |
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171 | #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 |
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172 | |
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173 | #define SRR0_FRAME_OFFSET 8 |
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174 | #define SRR1_FRAME_OFFSET 12 |
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175 | #define EXCEPTION_NUMBER_OFFSET 16 |
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176 | #define EXC_CR_OFFSET 20 |
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177 | #define EXC_CTR_OFFSET 24 |
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178 | #define EXC_XER_OFFSET 28 |
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179 | #define EXC_LR_OFFSET 32 |
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180 | #define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) |
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181 | #define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) |
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182 | #define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) |
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183 | #define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3) |
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184 | #define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4) |
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185 | #define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5) |
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186 | #define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6) |
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187 | #define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7) |
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188 | #define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8) |
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189 | #define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9) |
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190 | #define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10) |
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191 | #define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11) |
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192 | #define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12) |
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193 | #define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13) |
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194 | #define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14) |
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195 | #define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15) |
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196 | #define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16) |
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197 | #define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17) |
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198 | #define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18) |
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199 | #define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19) |
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200 | #define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20) |
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201 | #define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21) |
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202 | #define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22) |
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203 | #define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23) |
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204 | #define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24) |
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205 | #define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25) |
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206 | #define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26) |
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207 | #define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27) |
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208 | #define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28) |
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209 | #define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29) |
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210 | #define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) |
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211 | #define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) |
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212 | #define EXC_MSR_OFFSET PPC_EXC_GPR_OFFSET(32) |
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213 | #define EXC_DAR_OFFSET (4 + EXC_MSR_OFFSET) |
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214 | |
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215 | #define EXC_GENERIC_SIZE PPC_EXC_FRAME_SIZE |
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216 | |
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217 | #ifdef __ALTIVEC__ |
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218 | #define EXC_VEC_OFFSET EXC_GENERIC_SIZE |
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219 | #ifndef PPC_CACHE_ALIGNMENT |
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220 | #error "Missing include file!" |
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221 | #endif |
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222 | /* 20 volatile registers |
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223 | * + cache-aligned area for vcsr, vrsave |
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224 | * + area for alignment |
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225 | */ |
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226 | #define EXC_VEC_SIZE (16*20 + 2*PPC_CACHE_ALIGNMENT) |
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227 | #else |
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228 | #define EXC_VEC_SIZE (0) |
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229 | #endif |
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230 | |
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231 | /* Exception stack frame -> BSP_Exception_frame */ |
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232 | #define FRAME_LINK_SPACE 8 |
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233 | |
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234 | /* |
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235 | * maintain the EABI requested 8 bytes aligment |
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236 | * As SVR4 ABI requires 16, make it 16 (as some |
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237 | * exception may need more registers to be processed...) |
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238 | */ |
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239 | #define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE) |
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240 | |
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241 | /** @} */ |
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242 | |
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243 | #ifndef ASM |
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244 | |
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245 | /** |
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246 | * @ingroup ppc_exc_frame |
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247 | * |
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248 | * @{ |
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249 | */ |
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250 | |
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251 | typedef struct { |
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252 | unsigned EXC_SRR0; |
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253 | unsigned EXC_SRR1; |
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254 | unsigned _EXC_number; |
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255 | unsigned EXC_CR; |
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256 | unsigned EXC_CTR; |
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257 | unsigned EXC_XER; |
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258 | unsigned EXC_LR; |
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259 | #ifdef __SPE__ |
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260 | uint32_t EXC_SPEFSCR; |
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261 | uint64_t EXC_ACC; |
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262 | #endif |
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263 | PPC_GPR_TYPE GPR0; |
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264 | PPC_GPR_TYPE GPR1; |
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265 | PPC_GPR_TYPE GPR2; |
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266 | PPC_GPR_TYPE GPR3; |
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267 | PPC_GPR_TYPE GPR4; |
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268 | PPC_GPR_TYPE GPR5; |
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269 | PPC_GPR_TYPE GPR6; |
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270 | PPC_GPR_TYPE GPR7; |
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271 | PPC_GPR_TYPE GPR8; |
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272 | PPC_GPR_TYPE GPR9; |
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273 | PPC_GPR_TYPE GPR10; |
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274 | PPC_GPR_TYPE GPR11; |
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275 | PPC_GPR_TYPE GPR12; |
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276 | PPC_GPR_TYPE GPR13; |
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277 | PPC_GPR_TYPE GPR14; |
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278 | PPC_GPR_TYPE GPR15; |
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279 | PPC_GPR_TYPE GPR16; |
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280 | PPC_GPR_TYPE GPR17; |
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281 | PPC_GPR_TYPE GPR18; |
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282 | PPC_GPR_TYPE GPR19; |
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283 | PPC_GPR_TYPE GPR20; |
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284 | PPC_GPR_TYPE GPR21; |
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285 | PPC_GPR_TYPE GPR22; |
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286 | PPC_GPR_TYPE GPR23; |
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287 | PPC_GPR_TYPE GPR24; |
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288 | PPC_GPR_TYPE GPR25; |
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289 | PPC_GPR_TYPE GPR26; |
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290 | PPC_GPR_TYPE GPR27; |
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291 | PPC_GPR_TYPE GPR28; |
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292 | PPC_GPR_TYPE GPR29; |
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293 | PPC_GPR_TYPE GPR30; |
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294 | PPC_GPR_TYPE GPR31; |
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295 | unsigned EXC_MSR; |
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296 | unsigned EXC_DAR; |
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297 | } BSP_Exception_frame; |
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298 | |
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299 | /** @} */ |
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300 | |
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301 | /** |
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302 | * @ingroup ppc_exc |
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303 | * |
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304 | * @{ |
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305 | */ |
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306 | |
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307 | /** |
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308 | * @brief Global exception handler type. |
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309 | */ |
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310 | typedef void (*exception_handler_t)(BSP_Exception_frame*); |
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311 | |
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312 | /** |
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313 | * @brief Global exception handler. |
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314 | */ |
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315 | extern exception_handler_t globalExceptHdl; |
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316 | |
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317 | /** |
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318 | * @brief Default global exception handler. |
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319 | */ |
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320 | void C_exception_handler(BSP_Exception_frame* excPtr); |
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321 | |
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322 | void BSP_printStackTrace(BSP_Exception_frame *excPtr); |
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323 | |
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324 | /** |
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325 | * @brief Exception categories. |
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326 | * |
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327 | * Exceptions of different categories use different SRR registers to save the |
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328 | * machine state and do different things in the prologue and epilogue. |
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329 | * |
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330 | * For now, the CPU descriptions assume this fits into 8 bits. |
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331 | */ |
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332 | typedef enum { |
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333 | PPC_EXC_INVALID = 0, |
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334 | PPC_EXC_ASYNC = 1, |
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335 | PPC_EXC_CLASSIC = 2, |
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336 | PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, |
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337 | PPC_EXC_405_CRITICAL = 4, |
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338 | PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC, |
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339 | PPC_EXC_BOOKE_CRITICAL = 6, |
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340 | PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC, |
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341 | PPC_EXC_E500_MACHCHK = 8, |
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342 | PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC, |
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343 | PPC_EXC_NAKED = 10 |
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344 | } ppc_exc_category; |
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345 | |
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346 | /** |
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347 | * @brief Categorie set type. |
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348 | */ |
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349 | typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1]; |
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350 | |
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351 | static inline bool ppc_exc_is_valid_category(ppc_exc_category category) |
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352 | { |
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353 | return (unsigned) category <= (unsigned) PPC_EXC_NAKED; |
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354 | } |
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355 | |
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356 | /** |
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357 | * @brief Indicates if exception entry table resides in a writable memory. |
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358 | * |
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359 | * This variable is initialized to 'TRUE' by default; |
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360 | * BSPs which have their vectors in ROM should set it |
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361 | * to FALSE prior to initializing raw exceptions. |
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362 | * |
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363 | * I suspect the only candidate is the simulator. |
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364 | * After all, the value of this variable is used to |
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365 | * determine where to install the prologue code and |
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366 | * installing to ROM on anyting that's real ROM |
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367 | * will fail anyways. |
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368 | * |
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369 | * This should probably go away... (T.S. 2007/11/30) |
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370 | */ |
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371 | extern bool bsp_exceptions_in_RAM; |
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372 | |
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373 | /** |
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374 | * @brief Vector base address for CPUs (for example e200 and e500) with IVPR |
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375 | * and IVOR registers. |
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376 | */ |
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377 | extern uint32_t ppc_exc_vector_base; |
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378 | |
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379 | /** |
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380 | * @brief Returns the entry address of the vector @a vector. |
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381 | */ |
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382 | void *ppc_exc_vector_address(unsigned vector); |
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383 | |
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384 | /** |
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385 | * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if |
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386 | * there is no category set available for this CPU. |
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387 | */ |
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388 | const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu); |
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389 | |
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390 | /** |
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391 | * @brief Returns the category set for the current CPU, or @c NULL if there is |
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392 | * no category set available for this CPU. |
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393 | */ |
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394 | static inline const ppc_exc_categories *ppc_exc_current_categories(void) |
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395 | { |
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396 | return ppc_exc_categories_for_cpu(ppc_cpu_current()); |
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397 | } |
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398 | |
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399 | /** |
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400 | * @brief Returns the category for the vector @a vector using the category set |
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401 | * @a categories. |
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402 | */ |
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403 | ppc_exc_category ppc_exc_category_for_vector( |
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404 | const ppc_exc_categories *categories, |
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405 | unsigned vector |
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406 | ); |
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407 | |
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408 | /** |
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409 | * @brief Makes a minimal prologue for the vector @a vector with the category |
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410 | * @a category. |
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411 | * |
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412 | * The minimal prologue will be copied to @a prologue. Not more than @a |
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413 | * prologue_size bytes will be copied. Returns the actual minimal prologue |
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414 | * size in bytes in @a prologue_size. |
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415 | * |
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416 | * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made. |
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417 | * @retval RTEMS_INVALID_ID Invalid vector number. |
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418 | * @retval RTEMS_INVALID_NUMBER Invalid category. |
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419 | * @retval RTEMS_INVALID_SIZE Prologue size to small. |
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420 | */ |
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421 | rtems_status_code ppc_exc_make_prologue( |
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422 | unsigned vector, |
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423 | ppc_exc_category category, |
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424 | uint32_t *prologue, |
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425 | size_t *prologue_size |
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426 | ); |
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427 | |
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428 | /** |
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429 | * @brief Initializes the exception handling. |
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430 | * |
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431 | * @retval RTEMS_SUCCESSFUL Successful initialization. |
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432 | * @retval RTEMS_NOT_IMPLEMENTED No category set available for the current CPU. |
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433 | * @retval RTEMS_NOT_CONFIGURED Register r13 does not point to the small data |
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434 | * area anchor required by SVR4/EABI. |
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435 | * @retval RTEMS_INTERNAL_ERROR Minimal prologue creation failed. |
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436 | */ |
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437 | rtems_status_code ppc_exc_initialize( |
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438 | uint32_t interrupt_disable_mask, |
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439 | uintptr_t interrupt_stack_begin, |
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440 | uintptr_t interrupt_stack_size |
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441 | ); |
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442 | |
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443 | /** |
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444 | * @brief High-level exception handler type. |
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445 | * |
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446 | * Exception handlers should return zero if the exception was handled and |
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447 | * normal execution may resume. |
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448 | * |
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449 | * They should return minus one to reject the exception resulting in the |
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450 | * globalExcHdl() being called. |
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451 | * |
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452 | * Other return values are reserved. |
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453 | */ |
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454 | typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); |
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455 | |
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456 | /** |
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457 | * @brief Bits for MSR update. |
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458 | * |
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459 | * Bits in MSR that are enabled during execution of exception handlers / ISRs |
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460 | * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should |
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461 | * be set to 0 during initialization) |
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462 | * |
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463 | * By default, the setting of these bits that is in effect when exception |
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464 | * handling is initialized is used. |
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465 | */ |
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466 | extern uint32_t ppc_exc_msr_bits; |
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467 | |
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468 | /** |
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469 | * @brief Cache write back check flag. |
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470 | * |
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471 | * (See README under CAVEATS). During initialization |
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472 | * a check is performed to assert that write-back |
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473 | * caching is enabled for memory accesses. If a BSP |
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474 | * runs entirely without any caching then it should |
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475 | * set this variable to zero prior to initializing |
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476 | * exceptions in order to skip the test. |
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477 | * NOTE: The code does NOT support mapping memory |
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478 | * with cache-attributes other than write-back |
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479 | * (unless the entire cache is physically disabled) |
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480 | */ |
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481 | extern uint32_t ppc_exc_cache_wb_check; |
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482 | |
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483 | /** |
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484 | * @brief Set high-level exception handler. |
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485 | * |
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486 | * Hook C exception handlers. |
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487 | * - handlers for asynchronous exceptions run on the ISR stack |
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488 | * with thread-dispatching disabled. |
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489 | * - handlers for synchronous exceptions run on the task stack |
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490 | * with thread-dispatching enabled. |
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491 | * |
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492 | * If a particular slot is NULL then the traditional 'globalExcHdl' is used. |
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493 | * |
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494 | * ppc_exc_set_handler() registers a handler (returning 0 on success, |
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495 | * -1 if the vector argument is too big). |
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496 | * |
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497 | * It is legal to set a NULL handler. This leads to the globalExcHdl |
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498 | * being called if an exception for 'vector' occurs. |
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499 | */ |
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500 | rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl); |
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501 | |
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502 | /** |
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503 | * @brief Returns the currently active high-level exception handler. |
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504 | */ |
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505 | ppc_exc_handler_t ppc_exc_get_handler(unsigned vector); |
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506 | |
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507 | /** |
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508 | * @brief Function for DAR access. |
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509 | * |
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510 | * CPU support may store the address of a function here |
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511 | * that can be used by the default exception handler to |
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512 | * obtain fault-address info which is helpful. Unfortunately, |
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513 | * the SPR holding this information is not uniform |
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514 | * across PPC families so we need assistance from |
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515 | * CPU support |
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516 | */ |
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517 | extern uint32_t (*ppc_exc_get_DAR)(void); |
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518 | |
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519 | void |
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520 | ppc_exc_wrapup(BSP_Exception_frame *f); |
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521 | |
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522 | /** |
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523 | * @brief Standard aligment handler. |
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524 | * |
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525 | * @retval 0 Performed a dcbz instruction. |
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526 | * @retval -1 Otherwise. |
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527 | */ |
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528 | int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum); |
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529 | |
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530 | /** @} */ |
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531 | |
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532 | /* |
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533 | * Compatibility with pc386 |
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534 | */ |
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535 | typedef BSP_Exception_frame CPU_Exception_frame; |
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536 | typedef exception_handler_t cpuExcHandlerType; |
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537 | |
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538 | #endif /* ASM */ |
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539 | |
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540 | #ifdef __cplusplus |
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541 | } |
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542 | #endif |
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543 | |
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544 | #endif /* LIBCPU_VECTORS_H */ |
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