source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h @ 0f7b6eff

4.115
Last change on this file since 0f7b6eff was 0f7b6eff, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/17/11 at 03:30:08

2011-02-17 Ralf Corsépius <ralf.corsepius@…>

  • new-exceptions/bspsupport/vectors.h: Add extern "C" {}.
  • Property mode set to 100644
File size: 14.5 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 * @ingroup ppc_exc_frame
6 *
7 * @brief PowerPC Exceptions API.
8 */
9
10/*
11 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
12 *                    Canon Centre Recherche France.
13 *
14 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
15 *
16 * Copyright (C) 2009 embedded brains GmbH.
17 *
18 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
19 * to support 603, 603e, 604, 604e exceptions
20 *
21 * Moved to "libcpu/powerpc/new-exceptions" and consolidated
22 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
23 * to be common for all PPCs with new exceptions.
24 *
25 * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h".
26 * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h".
27 *
28 * The license and distribution terms for this file may be
29 * found in the file LICENSE in this distribution or at
30 * http://www.rtems.com/license/LICENSE.
31 *
32 * $Id$
33 */
34
35/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
36
37#ifndef LIBCPU_VECTORS_H
38#define LIBCPU_VECTORS_H
39
40#include <libcpu/powerpc-utility.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46/**
47 * @defgroup ppc_exc PowerPC Exceptions
48 *
49 * @brief XXX
50 *
51 * @{
52 */
53
54#define ASM_RESET_VECTOR                     0x01
55#define ASM_MACH_VECTOR                      0x02
56#define ASM_PROT_VECTOR                      0x03
57#define ASM_ISI_VECTOR                       0x04
58#define ASM_EXT_VECTOR                       0x05
59#define ASM_ALIGN_VECTOR                     0x06
60#define ASM_PROG_VECTOR                      0x07
61#define ASM_FLOAT_VECTOR                     0x08
62#define ASM_DEC_VECTOR                       0x09
63#define ASM_SYS_VECTOR                       0x0C
64#define ASM_TRACE_VECTOR                     0x0D
65
66#define ASM_PPC405_APU_UNAVAIL_VECTOR        ASM_60X_VEC_ASSIST_VECTOR
67
68#define ASM_8XX_FLOATASSIST_VECTOR           0x0E
69#define ASM_8XX_SOFTEMUL_VECTOR              0x10
70#define ASM_8XX_ITLBMISS_VECTOR              0x11
71#define ASM_8XX_DTLBMISS_VECTOR              0x12
72#define ASM_8XX_ITLBERROR_VECTOR             0x13
73#define ASM_8XX_DTLBERROR_VECTOR             0x14
74#define ASM_8XX_DBREAK_VECTOR                0x1C
75#define ASM_8XX_IBREAK_VECTOR                0x1D
76#define ASM_8XX_PERIFBREAK_VECTOR            0x1E
77#define ASM_8XX_DEVPORT_VECTOR               0x1F
78
79#define ASM_5XX_FLOATASSIST_VECTOR           0x0E
80#define ASM_5XX_SOFTEMUL_VECTOR              0x10
81#define ASM_5XX_IPROT_VECTOR                 0x13
82#define ASM_5XX_DPROT_VECTOR                 0x14
83#define ASM_5XX_DBREAK_VECTOR                0x1C
84#define ASM_5XX_IBREAK_VECTOR                0x1D
85#define ASM_5XX_MEBREAK_VECTOR               0x1E
86#define ASM_5XX_NMEBREAK_VECTOR              0x1F
87
88#define ASM_60X_VEC_VECTOR                   0x0A
89#define ASM_60X_PERFMON_VECTOR               0x0F
90#define ASM_60X_IMISS_VECTOR                 0x10
91#define ASM_60X_DLMISS_VECTOR                0x11
92#define ASM_60X_DSMISS_VECTOR                0x12
93#define ASM_60X_ADDR_VECTOR                  0x13
94#define ASM_60X_SYSMGMT_VECTOR               0x14
95#define ASM_60X_VEC_ASSIST_VECTOR            0x16
96#define ASM_60X_ITM_VECTOR                   0x17
97
98/* Book E */
99#define ASM_BOOKE_CRIT_VECTOR                0x01
100/* We could use the std. decrementer vector # on bookE, too,
101 * but the bookE decrementer has slightly different semantics
102 * so we use a different vector (which happens to be
103 * the PIT vector on the 405 which is like the booke decrementer)
104 */
105#define ASM_BOOKE_DEC_VECTOR                 0x10
106#define ASM_BOOKE_ITLBMISS_VECTOR            0x11
107#define ASM_BOOKE_DTLBMISS_VECTOR            0x12
108#define ASM_BOOKE_FIT_VECTOR                 0x13
109#define ASM_BOOKE_WDOG_VECTOR                0x14
110#define ASM_BOOKE_APU_VECTOR                 0x18
111#define ASM_BOOKE_DEBUG_VECTOR               ASM_TRACE_VECTOR
112
113/* e200 and e500 */
114#define ASM_E500_SPE_UNAVAILABLE_VECTOR      ASM_60X_VEC_VECTOR
115#define ASM_E500_EMB_FP_DATA_VECTOR          0x19
116#define ASM_E500_EMB_FP_ROUND_VECTOR         0x1A
117#define ASM_E500_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
118
119/* e300 */
120#define ASM_E300_CRIT_VECTOR                 0x0A
121#define ASM_E300_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
122#define ASM_E300_IMISS_VECTOR                ASM_60X_IMISS_VECTOR  /* Special case: Shadowed GPRs */
123#define ASM_E300_DLMISS_VECTOR               ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */
124#define ASM_E300_DSMISS_VECTOR               ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */
125#define ASM_E300_ADDR_VECTOR                 ASM_60X_ADDR_VECTOR
126#define ASM_E300_SYSMGMT_VECTOR              ASM_60X_SYSMGMT_VECTOR
127
128/*
129 * If you change that number make sure to adjust the wrapper code in ppc_exc.S
130 * and that ppc_exc_handler_table will be correctly initialized.
131 */
132#define LAST_VALID_EXC                       0x1F
133
134/* DO NOT USE -- this symbol is DEPRECATED
135 * (only used by libbsp/shared/vectors/vectors.S
136 * which should not be used by new BSPs).
137 */
138#define ASM_60X_VEC_VECTOR_OFFSET            0xf20
139
140#define ASM_PPC405_FIT_VECTOR_OFFSET         0x1010
141#define ASM_PPC405_WDOG_VECTOR_OFFSET        0x1020
142#define ASM_PPC405_TRACE_VECTOR_OFFSET       0x2000
143
144/** @} */
145
146/**
147 * @defgroup ppc_exc_frame PowerPC Exception Frame
148 *
149 * @brief XXX
150 *
151 * @{
152 */
153
154/*
155 * The callee (high level exception code written in C)
156 * will store the Link Registers (return address) at entry r1 + 4 !!!.
157 * So let room for it!!!.
158 */
159#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
160#define SRR0_FRAME_OFFSET 8
161#define SRR1_FRAME_OFFSET 12
162#define EXCEPTION_NUMBER_OFFSET 16
163#define GPR0_OFFSET 20
164#define GPR1_OFFSET 24
165#define GPR2_OFFSET 28
166#define GPR3_OFFSET 32
167#define GPR4_OFFSET 36
168#define GPR5_OFFSET 40
169#define GPR6_OFFSET 44
170#define GPR7_OFFSET 48
171#define GPR8_OFFSET 52
172#define GPR9_OFFSET 56
173#define GPR10_OFFSET 60
174#define GPR11_OFFSET 64
175#define GPR12_OFFSET 68
176#define GPR13_OFFSET 72
177#define GPR14_OFFSET 76
178#define GPR15_OFFSET 80
179#define GPR16_OFFSET 84
180#define GPR17_OFFSET 88
181#define GPR18_OFFSET 92
182#define GPR19_OFFSET 96
183#define GPR20_OFFSET 100
184#define GPR21_OFFSET 104
185#define GPR22_OFFSET 108
186#define GPR23_OFFSET 112
187#define GPR24_OFFSET 116
188#define GPR25_OFFSET 120
189#define GPR26_OFFSET 124
190#define GPR27_OFFSET 128
191#define GPR28_OFFSET 132
192#define GPR29_OFFSET 136
193#define GPR30_OFFSET 140
194#define GPR31_OFFSET 144
195#define EXC_CR_OFFSET 148
196#define EXC_CTR_OFFSET 152
197#define EXC_XER_OFFSET 156
198#define EXC_LR_OFFSET 160
199
200#define EXC_GENERIC_SIZE 176
201
202#ifdef __ALTIVEC__
203#define EXC_VEC_OFFSET EXC_GENERIC_SIZE
204#ifndef PPC_CACHE_ALIGNMENT
205#error "Missing include file!"
206#endif
207/*   20 volatile registers
208 * + cache-aligned area for vcsr, vrsave
209 * + area for alignment
210 */
211#define EXC_VEC_SIZE   (16*20 + 2*PPC_CACHE_ALIGNMENT)
212#else
213#define EXC_VEC_SIZE   (0)
214#endif
215
216/* Exception stack frame -> BSP_Exception_frame */
217#define FRAME_LINK_SPACE 8
218
219/*
220 * maintain the EABI requested 8 bytes aligment
221 * As SVR4 ABI requires 16, make it 16 (as some
222 * exception may need more registers to be processed...)
223 */
224#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE)
225
226/** @} */
227
228#ifndef ASM
229
230/**
231 * @ingroup ppc_exc_frame
232 *
233 * @{
234 */
235
236typedef struct {
237  unsigned EXC_SRR0;
238  unsigned EXC_SRR1;
239  unsigned _EXC_number;
240  unsigned GPR0;
241  unsigned GPR1;
242  unsigned GPR2;
243  unsigned GPR3;
244  unsigned GPR4;
245  unsigned GPR5;
246  unsigned GPR6;
247  unsigned GPR7;
248  unsigned GPR8;
249  unsigned GPR9;
250  unsigned GPR10;
251  unsigned GPR11;
252  unsigned GPR12;
253  unsigned GPR13;
254  unsigned GPR14;
255  unsigned GPR15;
256  unsigned GPR16;
257  unsigned GPR17;
258  unsigned GPR18;
259  unsigned GPR19;
260  unsigned GPR20;
261  unsigned GPR21;
262  unsigned GPR22;
263  unsigned GPR23;
264  unsigned GPR24;
265  unsigned GPR25;
266  unsigned GPR26;
267  unsigned GPR27;
268  unsigned GPR28;
269  unsigned GPR29;
270  unsigned GPR30;
271  unsigned GPR31;
272  unsigned EXC_CR;
273  unsigned EXC_CTR;
274  unsigned EXC_XER;
275  unsigned EXC_LR;
276  unsigned EXC_MSR;
277  unsigned EXC_DAR;
278} BSP_Exception_frame;
279
280/** @} */
281
282/**
283 * @ingroup ppc_exc
284 *
285 * @{
286 */
287
288/**
289 * @brief Global exception handler type.
290 */
291typedef void (*exception_handler_t)(BSP_Exception_frame*);
292
293/**
294 * @brief Global exception handler.
295 */
296extern exception_handler_t globalExceptHdl;
297
298/**
299 * @brief Default global exception handler.
300 */
301void C_exception_handler(BSP_Exception_frame* excPtr);
302
303void BSP_printStackTrace(BSP_Exception_frame *excPtr);
304
305/**
306 * @brief Exception categories.
307 *
308 * Exceptions of different categories use different SRR registers to save the
309 * machine state and do different things in the prologue and epilogue.
310 *
311 * For now, the CPU descriptions assume this fits into 8 bits.
312 */
313typedef enum {
314  PPC_EXC_INVALID = 0,
315  PPC_EXC_ASYNC = 1,
316  PPC_EXC_CLASSIC = 2,
317  PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
318  PPC_EXC_405_CRITICAL = 4,
319  PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
320  PPC_EXC_BOOKE_CRITICAL = 6,
321  PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
322  PPC_EXC_E500_MACHCHK  = 8,
323  PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC,
324  PPC_EXC_NAKED = 10
325} ppc_exc_category;
326
327/**
328 * @brief Categorie set type.
329 */
330typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1];
331
332static inline bool ppc_exc_is_valid_category(ppc_exc_category category)
333{
334  return (unsigned) category <= (unsigned) PPC_EXC_NAKED;
335}
336
337/**
338 * @brief Indicates if exception entry table resides in a writable memory.
339 *
340 * This variable is initialized to 'TRUE' by default;
341 * BSPs which have their vectors in ROM should set it
342 * to FALSE prior to initializing raw exceptions.
343 *
344 * I suspect the only candidate is the simulator.
345 * After all, the value of this variable is used to
346 * determine where to install the prologue code and
347 * installing to ROM on anyting that's real ROM
348 * will fail anyways.
349 *
350 * This should probably go away... (T.S. 2007/11/30)
351 */
352extern bool bsp_exceptions_in_RAM;
353
354/**
355 * @brief Vector base address for CPUs (for example e200 and e500) with IVPR
356 * and IVOR registers.
357 */
358extern uint32_t ppc_exc_vector_base;
359
360/**
361 * @brief Returns the entry address of the vector @a vector.
362 */
363void *ppc_exc_vector_address(unsigned vector);
364
365/**
366 * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if
367 * there is no category set available for this CPU.
368 */
369const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu);
370
371/**
372 * @brief Returns the category set for the current CPU, or @c NULL if there is
373 * no category set available for this CPU.
374 */
375static inline const ppc_exc_categories *ppc_exc_current_categories(void)
376{
377  return ppc_exc_categories_for_cpu(ppc_cpu_current());
378}
379
380/**
381 * @brief Returns the category for the vector @a vector using the category set
382 * @a categories.
383 */
384ppc_exc_category ppc_exc_category_for_vector(
385  const ppc_exc_categories *categories,
386  unsigned vector
387);
388
389/**
390 * @brief Makes a minimal prologue for the vector @a vector with the category
391 * @a category.
392 *
393 * The minimal prologue will be copied to @a prologue.  Not more than @a
394 * prologue_size bytes will be copied.  Returns the actual minimal prologue
395 * size in bytes in @a prologue_size.
396 *
397 * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made.
398 * @retval RTEMS_INVALID_ID Invalid vector number.
399 * @retval RTEMS_INVALID_NUMBER Invalid category.
400 * @retval RTEMS_INVALID_SIZE Prologue size to small.
401 */
402rtems_status_code ppc_exc_make_prologue(
403  unsigned vector,
404  ppc_exc_category category,
405  uint32_t *prologue,
406  size_t *prologue_size
407);
408
409/**
410 * @brief Initializes the exception handling.
411 *
412 * @retval RTEMS_SUCCESSFUL Successful initialization.
413 * @retval RTEMS_NOT_IMPLEMENTED No category set available for the current CPU.
414 * @retval RTEMS_NOT_CONFIGURED Register r13 does not point to the small data
415 * area anchor required by SVR4/EABI.
416 * @retval RTEMS_INTERNAL_ERROR Minimal prologue creation failed.
417 */
418rtems_status_code ppc_exc_initialize(
419  uint32_t interrupt_disable_mask,
420  uintptr_t interrupt_stack_begin,
421  uintptr_t interrupt_stack_size
422);
423
424/**
425 * @brief High-level exception handler type.
426 *
427 * Exception handlers should return zero if the exception was handled and
428 * normal execution may resume.
429 *
430 * They should return minus one to reject the exception resulting in the
431 * globalExcHdl() being called.
432 *
433 * Other return values are reserved.
434 */
435typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector);
436
437/**
438 * @brief Bits for MSR update.
439 *
440 * Bits in MSR that are enabled during execution of exception handlers / ISRs
441 * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
442 * be set to 0 during initialization)
443 *
444 * By default, the setting of these bits that is in effect when exception
445 * handling is initialized is used.
446 */
447extern uint32_t ppc_exc_msr_bits;
448
449/**
450 * @brief Cache write back check flag.
451 *
452 * (See README under CAVEATS). During initialization
453 * a check is performed to assert that write-back
454 * caching is enabled for memory accesses. If a BSP
455 * runs entirely without any caching then it should
456 * set this variable to zero prior to initializing
457 * exceptions in order to skip the test.
458 * NOTE: The code does NOT support mapping memory
459 *       with cache-attributes other than write-back
460 *       (unless the entire cache is physically disabled)
461 */
462extern uint32_t ppc_exc_cache_wb_check;
463
464/**
465 * @brief Set high-level exception handler.
466 *
467 * Hook C exception handlers.
468 *  - handlers for asynchronous exceptions run on the ISR stack
469 *    with thread-dispatching disabled.
470 *  - handlers for synchronous exceptions run on the task stack
471 *    with thread-dispatching enabled.
472 *
473 * If a particular slot is NULL then the traditional 'globalExcHdl' is used.
474 *
475 * ppc_exc_set_handler() registers a handler (returning 0 on success,
476 * -1 if the vector argument is too big).
477 *
478 * It is legal to set a NULL handler. This leads to the globalExcHdl
479 * being called if an exception for 'vector' occurs.
480 */
481rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl);
482
483/**
484 * @brief Returns the currently active high-level exception handler.
485 */
486ppc_exc_handler_t ppc_exc_get_handler(unsigned vector);
487
488/**
489 * @brief Function for DAR access.
490 *
491 * CPU support may store the address of a function here
492 * that can be used by the default exception handler to
493 * obtain fault-address info which is helpful. Unfortunately,
494 * the SPR holding this information is not uniform
495 * across PPC families so we need assistance from
496 * CPU support
497 */
498extern uint32_t (*ppc_exc_get_DAR)(void);
499
500void
501ppc_exc_wrapup(BSP_Exception_frame *f);
502
503/** @} */
504
505/*
506 * Compatibility with pc386
507 */
508typedef BSP_Exception_frame CPU_Exception_frame;
509typedef exception_handler_t cpuExcHandlerType;
510
511#endif /* ASM */
512
513#ifdef __cplusplus
514}
515#endif
516
517#endif /* LIBCPU_VECTORS_H */
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