source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c @ d7ed684

5
Last change on this file since d7ed684 was d7ed684, checked in by Sebastian Huber <sebastian.huber@…>, on 09/20/17 at 05:18:53

bsps/powerpc: Fix PPC_EXC_CONFIG_USE_FIXED_HANDLER

Fix link-time error on BSPs not using PPC_EXC_CONFIG_USE_FIXED_HANDLER.

Update #3085.

  • Property mode set to 100644
File size: 5.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 *
6 * @brief PowerPC Exceptions implementation.
7 */
8
9/*
10 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
11 *
12 * Copyright (C) 2009-2012 embedded brains GmbH.
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE.
17 */
18
19#include <string.h>
20
21#include <bsp/vectors.h>
22
23/* Offset into minimal prolog where vector number is hardcoded */
24#define PPC_EXC_PROLOG_VEC_OFFSET 2
25
26/* Symbols are defined by the linker */
27extern const char ppc_exc_min_prolog_size [];
28extern const char ppc_exc_tgpr_clr_prolog_size [];
29
30/* Special prologue for handling register shadowing on 603-style CPUs */
31extern const uint32_t ppc_exc_tgpr_clr_prolog [];
32
33/*
34 * Classic prologue which determines the vector dynamically from the offset
35 * address. This must only be used for classic, synchronous exceptions with a
36 * vector offset aligned on a 256-byte boundary.
37 */
38extern const uint32_t ppc_exc_min_prolog_auto [];
39
40/* Minimal prologue templates */
41extern const uint32_t ppc_exc_min_prolog_async_tmpl_std [];
42extern const uint32_t ppc_exc_min_prolog_sync_tmpl_std [];
43extern const uint32_t ppc_exc_min_prolog_async_tmpl_p405_crit [];
44extern const uint32_t ppc_exc_min_prolog_sync_tmpl_p405_crit [];
45extern const uint32_t ppc_exc_min_prolog_async_tmpl_bookE_crit [];
46extern const uint32_t ppc_exc_min_prolog_sync_tmpl_bookE_crit [];
47extern const uint32_t ppc_exc_min_prolog_sync_tmpl_e500_mchk [];
48extern const uint32_t ppc_exc_min_prolog_async_tmpl_e500_mchk [];
49extern const uint32_t ppc_exc_min_prolog_tmpl_naked [];
50extern const uint32_t ppc_exc_min_prolog_async_tmpl_normal [];
51
52static const uint32_t *const ppc_exc_prologue_templates [] = {
53  [PPC_EXC_CLASSIC] = ppc_exc_min_prolog_sync_tmpl_std,
54  [PPC_EXC_CLASSIC_ASYNC] = ppc_exc_min_prolog_async_tmpl_std,
55  [PPC_EXC_405_CRITICAL] = ppc_exc_min_prolog_sync_tmpl_p405_crit,
56  [PPC_EXC_405_CRITICAL_ASYNC] = ppc_exc_min_prolog_async_tmpl_p405_crit,
57  [PPC_EXC_BOOKE_CRITICAL] = ppc_exc_min_prolog_sync_tmpl_bookE_crit,
58  [PPC_EXC_BOOKE_CRITICAL_ASYNC] = ppc_exc_min_prolog_async_tmpl_bookE_crit,
59  [PPC_EXC_E500_MACHCHK] = ppc_exc_min_prolog_sync_tmpl_e500_mchk,
60  [PPC_EXC_E500_MACHCHK_ASYNC] = ppc_exc_min_prolog_async_tmpl_e500_mchk,
61  [PPC_EXC_NAKED] = ppc_exc_min_prolog_tmpl_naked
62};
63
64static bool ppc_exc_create_branch_op(
65  unsigned vector,
66  void *vector_base,
67  uint32_t *prologue,
68  size_t prologue_size
69)
70{
71  static const uintptr_t BRANCH_OP_CODE = 18 << 26;
72/*  static const uintptr_t BRANCH_OP_LINK = 0x1; */
73  static const uintptr_t BRANCH_OP_ABS = 0x2;
74  static const uintptr_t BRANCH_OP_MSK = 0x3ffffff;
75  size_t branch_op_index = prologue_size / 4 - 1;
76  uintptr_t vector_address =
77    (uintptr_t) ppc_exc_vector_address(vector, vector_base);
78  uintptr_t branch_op_address = vector_address + 4 * branch_op_index;
79
80  /* This value may have BRANCH_OP_LINK set */
81  uintptr_t target_address = prologue [branch_op_index];
82
83  uintptr_t branch_target_address = target_address - branch_op_address;
84
85  /*
86   * We prefer to use a relative branch.  This has the benefit that custom
87   * minimal prologues in a read-only area are relocatable.
88   */
89  if ((branch_target_address & ~BRANCH_OP_MSK) != 0) {
90    /* Target to far for relative branch (PC ± 32M) */
91    if (target_address >= 0xfe000001 || target_address < 0x01fffffd) {
92      /* Can use an absolute branch */
93      branch_target_address = (target_address | BRANCH_OP_ABS) & BRANCH_OP_MSK;
94    } else {
95      return false;
96    }
97  }
98
99  prologue [branch_op_index] = BRANCH_OP_CODE | branch_target_address;
100
101  return true;
102}
103
104rtems_status_code ppc_exc_make_prologue(
105  unsigned vector,
106  void *vector_base,
107  ppc_exc_category category,
108  uint32_t *prologue,
109  size_t *prologue_size
110)
111{
112  const uint32_t *prologue_template = NULL;
113  size_t prologue_template_size = 0;
114  bool fixup_vector = false;
115
116  if (!ppc_exc_is_valid_category(category)) {
117    return RTEMS_INVALID_NUMBER;
118  }
119
120  if (
121    ppc_cpu_has_shadowed_gprs()
122      && (vector == ASM_60X_IMISS_VECTOR
123        || vector == ASM_60X_DLMISS_VECTOR
124        || vector == ASM_60X_DSMISS_VECTOR)
125  ) {
126    prologue_template = ppc_exc_tgpr_clr_prolog;
127    prologue_template_size = (size_t) ppc_exc_tgpr_clr_prolog_size;
128  } else if (
129    category == PPC_EXC_CLASSIC
130      && ppc_cpu_is_bookE() != PPC_BOOKE_STD
131      && ppc_cpu_is_bookE() != PPC_BOOKE_E500
132  ) {
133    prologue_template = ppc_exc_min_prolog_auto;
134    prologue_template_size = (size_t) ppc_exc_min_prolog_size;
135#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
136  } else if (
137    category == PPC_EXC_CLASSIC_ASYNC
138      && ppc_cpu_is_bookE() == PPC_BOOKE_E500
139      && (ppc_interrupt_get_disable_mask() & MSR_CE) == 0
140  ) {
141    prologue_template = ppc_exc_min_prolog_async_tmpl_normal;
142    prologue_template_size = 16;
143    fixup_vector = true;
144#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
145  } else {
146    prologue_template = ppc_exc_prologue_templates [category];
147    prologue_template_size = (size_t) ppc_exc_min_prolog_size;
148    fixup_vector = true;
149  }
150
151  if (prologue_template_size <= *prologue_size) {
152    *prologue_size = prologue_template_size;
153
154    memcpy(prologue, prologue_template, prologue_template_size);
155
156    if (
157      !ppc_exc_create_branch_op(
158        vector,
159        vector_base,
160        prologue,
161        prologue_template_size
162      )
163    ) {
164      return RTEMS_INVALID_ADDRESS;
165    }
166
167    if (fixup_vector) {
168      if (vector <= 0x7fffU) {
169        prologue [PPC_EXC_PROLOG_VEC_OFFSET] =
170          (prologue [PPC_EXC_PROLOG_VEC_OFFSET] & 0xffff8000U)
171            | (vector & 0x7fffU);
172      } else {
173        return RTEMS_INVALID_ID;
174      }
175    }
176  } else {
177    return RTEMS_INVALID_SIZE;
178  }
179
180  return RTEMS_SUCCESSFUL;
181}
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