1 | /* PowerPC exception handling middleware; consult README for more |
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2 | * information. |
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3 | * |
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4 | * Author: Till Straumann <strauman@slac.stanford.edu>, 2007 |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <bsp/vectors.h> |
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12 | |
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13 | #include <rtems/score/threaddispatch.h> |
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14 | |
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15 | /* Provide temp. storage space for a few registers. |
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16 | * This is used by the assembly code prior to setting up |
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17 | * the stack. |
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18 | * One set is needed for each exception type with its |
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19 | * own SRR0/SRR1 pair since such exceptions may nest. |
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20 | * |
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21 | * NOTE: The assembly code needs these variables to |
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22 | * be in the .sdata section and accesses them |
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23 | * via R13. |
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24 | */ |
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25 | uint32_t ppc_exc_lock_std = 0; |
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26 | uint32_t ppc_exc_lock_crit = 0; |
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27 | uint32_t ppc_exc_lock_mchk = 0; |
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28 | |
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29 | uint32_t ppc_exc_vector_register_std = 0; |
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30 | uint32_t ppc_exc_vector_register_crit = 0; |
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31 | uint32_t ppc_exc_vector_register_mchk = 0; |
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32 | |
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33 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
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34 | |
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35 | /* MSR bits to enable once critical status info is saved and the stack |
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36 | * is switched; must be set depending on CPU type |
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37 | * |
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38 | * Default is set here for classic PPC CPUs with a MMU |
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39 | * but is overridden from vectors_init.c |
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40 | */ |
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41 | uint32_t ppc_exc_msr_bits = MSR_IR | MSR_DR | MSR_RI; |
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42 | |
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43 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
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44 | |
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45 | int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector) |
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46 | { |
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47 | return -1; |
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48 | } |
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49 | |
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50 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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51 | |
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52 | exception_handler_t globalExceptHdl = C_exception_handler; |
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53 | |
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54 | /* Table of C-handlers */ |
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55 | ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1] = { |
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56 | [0 ... LAST_VALID_EXC] = ppc_exc_handler_default |
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57 | }; |
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58 | |
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59 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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60 | |
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61 | ppc_exc_handler_t ppc_exc_get_handler(unsigned vector) |
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62 | { |
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63 | if ( |
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64 | vector <= LAST_VALID_EXC |
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65 | && ppc_exc_handler_table [vector] != ppc_exc_handler_default |
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66 | ) { |
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67 | return ppc_exc_handler_table [vector]; |
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68 | } else { |
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69 | return NULL; |
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70 | } |
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71 | } |
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72 | |
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73 | rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t handler) |
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74 | { |
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75 | if (vector <= LAST_VALID_EXC) { |
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76 | if (handler == NULL) { |
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77 | handler = ppc_exc_handler_default; |
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78 | } |
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79 | |
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80 | if (ppc_exc_handler_table [vector] != handler) { |
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81 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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82 | ppc_exc_handler_table [vector] = handler; |
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83 | #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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84 | return RTEMS_RESOURCE_IN_USE; |
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85 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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86 | } |
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87 | |
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88 | return RTEMS_SUCCESSFUL; |
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89 | } else { |
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90 | return RTEMS_INVALID_ID; |
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91 | } |
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92 | } |
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93 | |
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94 | void ppc_exc_wrapup(BSP_Exception_frame *frame) |
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95 | { |
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96 | Per_CPU_Control *cpu_self; |
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97 | |
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98 | cpu_self = _Per_CPU_Get(); |
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99 | |
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100 | if (cpu_self->isr_dispatch_disable) { |
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101 | return; |
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102 | } |
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103 | |
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104 | while (cpu_self->dispatch_necessary) { |
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105 | uint32_t msr; |
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106 | rtems_interrupt_level level; |
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107 | |
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108 | cpu_self->isr_dispatch_disable = 1; |
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109 | cpu_self->thread_dispatch_disable_level = 1; |
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110 | msr = ppc_machine_state_register(); |
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111 | _Thread_Do_dispatch(cpu_self, msr | MSR_EE); |
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112 | rtems_interrupt_local_disable(level); |
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113 | (void) level; |
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114 | cpu_self = _Per_CPU_Get(); |
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115 | } |
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116 | |
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117 | cpu_self->isr_dispatch_disable = 0; |
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118 | } |
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