source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c @ a4bca685

5
Last change on this file since a4bca685 was a4bca685, checked in by Sebastian Huber <sebastian.huber@…>, on 09/21/17 at 11:32:25

bsps/powerpc: Fix robust thread dispatch

Implement thread dispatch code in ppc_exc_wrapup() similar to
ppc_exc_interrupt().

Update #2811.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/* PowerPC exception handling middleware; consult README for more
2 * information.
3 *
4 * Author: Till Straumann <strauman@slac.stanford.edu>, 2007
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#include <bsp/vectors.h>
12
13#include <rtems/score/threaddispatch.h>
14
15/* Provide temp. storage space for a few registers.
16 * This is used by the assembly code prior to setting up
17 * the stack.
18 * One set is needed for each exception type with its
19 * own SRR0/SRR1 pair since such exceptions may nest.
20 *
21 * NOTE: The assembly code needs these variables to
22 *       be in the .sdata section and accesses them
23 *       via R13.
24 */
25uint32_t ppc_exc_lock_std  = 0;
26uint32_t ppc_exc_lock_crit = 0;
27uint32_t ppc_exc_lock_mchk = 0;
28
29uint32_t ppc_exc_vector_register_std  = 0;
30uint32_t ppc_exc_vector_register_crit = 0;
31uint32_t ppc_exc_vector_register_mchk = 0;
32
33#ifndef PPC_EXC_CONFIG_BOOKE_ONLY
34
35/* MSR bits to enable once critical status info is saved and the stack
36 * is switched; must be set depending on CPU type
37 *
38 * Default is set here for classic PPC CPUs with a MMU
39 * but is overridden from vectors_init.c
40 */
41uint32_t ppc_exc_msr_bits = MSR_IR | MSR_DR | MSR_RI;
42
43#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */
44
45int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector)
46{
47  return -1;
48}
49
50#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
51
52exception_handler_t globalExceptHdl = C_exception_handler;
53
54/* Table of C-handlers */
55ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1] = {
56  [0 ... LAST_VALID_EXC] = ppc_exc_handler_default
57};
58
59#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
60
61ppc_exc_handler_t ppc_exc_get_handler(unsigned vector)
62{
63  if (
64    vector <= LAST_VALID_EXC
65      && ppc_exc_handler_table [vector] != ppc_exc_handler_default
66  ) {
67    return ppc_exc_handler_table [vector];
68  } else {
69    return NULL;
70  }
71}
72
73rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t handler)
74{
75  if (vector <= LAST_VALID_EXC) {
76    if (handler == NULL) {
77      handler = ppc_exc_handler_default;
78    }
79
80    if (ppc_exc_handler_table [vector] != handler) {
81#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
82      ppc_exc_handler_table [vector] = handler;
83#else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
84      return RTEMS_RESOURCE_IN_USE;
85#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
86    }
87
88    return RTEMS_SUCCESSFUL;
89  } else {
90    return RTEMS_INVALID_ID;
91  }
92}
93
94void ppc_exc_wrapup(BSP_Exception_frame *frame)
95{
96  Per_CPU_Control *cpu_self;
97
98  cpu_self = _Per_CPU_Get();
99
100  if (cpu_self->isr_dispatch_disable) {
101    return;
102  }
103
104  while (cpu_self->dispatch_necessary) {
105    uint32_t msr;
106    rtems_interrupt_level level;
107
108    cpu_self->isr_dispatch_disable = 1;
109    cpu_self->thread_dispatch_disable_level = 1;
110    msr = ppc_machine_state_register();
111    _Thread_Do_dispatch(cpu_self, msr | MSR_EE);
112    rtems_interrupt_local_disable(level);
113    (void) level;
114    cpu_self = _Per_CPU_Get();
115  }
116
117  cpu_self->isr_dispatch_disable = 0;
118}
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