source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c @ 9b4422a2

4.115
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/* PowerPC exception handling middleware; consult README for more
2 * information.
3 *
4 * Author: Till Straumann <strauman@slac.stanford.edu>, 2007
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 */
10
11#include <rtems.h>
12#include <rtems/score/apiext.h>
13
14#include <bsp/vectors.h>
15
16/* Provide temp. storage space for a few registers.
17 * This is used by the assembly code prior to setting up
18 * the stack.
19 * One set is needed for each exception type with its
20 * own SRR0/SRR1 pair since such exceptions may nest.
21 *
22 * NOTE: The assembly code needs these variables to
23 *       be in the .sdata section and accesses them
24 *       via R13.
25 */
26uint32_t ppc_exc_lock_std  = 0;
27uint32_t ppc_exc_lock_crit = 0;
28uint32_t ppc_exc_lock_mchk = 0;
29
30uint32_t ppc_exc_vector_register_std  = 0;
31uint32_t ppc_exc_vector_register_crit = 0;
32uint32_t ppc_exc_vector_register_mchk = 0;
33
34/* MSR bits to enable once critical status info is saved and the stack
35 * is switched; must be set depending on CPU type
36 *
37 * Default is set here for classic PPC CPUs with a MMU
38 * but is overridden from vectors_init.c
39 */
40uint32_t ppc_exc_msr_bits = MSR_IR | MSR_DR | MSR_RI;
41
42static int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector)
43{
44  return -1;
45}
46
47/* Table of C-handlers */
48ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1] = {
49  [0 ... LAST_VALID_EXC] = ppc_exc_handler_default
50};
51
52ppc_exc_handler_t ppc_exc_get_handler(unsigned vector)
53{
54  if (
55    vector <= LAST_VALID_EXC
56      && ppc_exc_handler_table [vector] != ppc_exc_handler_default
57  ) {
58    return ppc_exc_handler_table [vector];
59  } else {
60    return NULL;
61  }
62}
63
64rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t handler)
65{
66  if (vector <= LAST_VALID_EXC) {
67    if (handler == NULL) {
68      ppc_exc_handler_table [vector] = ppc_exc_handler_default;
69    } else {
70      ppc_exc_handler_table [vector] = handler;
71    }
72
73    return RTEMS_SUCCESSFUL;
74  } else {
75    return RTEMS_INVALID_ID;
76  }
77}
78
79void ppc_exc_wrapup(BSP_Exception_frame *frame)
80{
81  /* dispatch_disable level is decremented from assembly code.  */
82  if ( _Thread_Dispatch_necessary ) {
83    /* FIXME: I believe it should be OK to re-enable
84     *        interrupts around the execution of _Thread_Dispatch();
85     */
86    _Thread_Dispatch();
87  }
88}
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