1 | /* |
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2 | * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bspopts.h> |
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16 | #include <rtems/score/percpu.h> |
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17 | #include <bsp/vectors.h> |
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18 | |
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19 | #define VECTOR_REGISTER r4 |
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20 | #define SELF_CPU_REGISTER r5 |
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21 | #define ISR_NEST_REGISTER r6 |
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22 | #define DISPATCH_LEVEL_REGISTER r7 |
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23 | #define HANDLER_REGISTER r8 |
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24 | #define SCRATCH_0_REGISTER r0 |
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25 | #define SCRATCH_1_REGISTER r3 |
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26 | #define SCRATCH_2_REGISTER r9 |
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27 | #define SCRATCH_3_REGISTER r10 |
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28 | #define SCRATCH_4_REGISTER r11 |
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29 | #define SCRATCH_5_REGISTER r12 |
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30 | #define FRAME_REGISTER r14 |
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31 | |
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32 | #define VECTOR_OFFSET GPR4_OFFSET |
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33 | #define SELF_CPU_OFFSET GPR5_OFFSET |
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34 | #define ISR_NEST_OFFSET GPR6_OFFSET |
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35 | #define DISPATCH_LEVEL_OFFSET GPR7_OFFSET |
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36 | #define HANDLER_OFFSET GPR8_OFFSET |
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37 | #define SCRATCH_0_OFFSET GPR0_OFFSET |
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38 | #define SCRATCH_1_OFFSET GPR3_OFFSET |
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39 | #define SCRATCH_2_OFFSET GPR9_OFFSET |
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40 | #define SCRATCH_3_OFFSET GPR10_OFFSET |
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41 | #define SCRATCH_4_OFFSET GPR11_OFFSET |
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42 | #define SCRATCH_5_OFFSET GPR12_OFFSET |
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43 | |
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44 | /* |
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45 | * The register 2 slot is free, since this is the read-only small data anchor. |
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46 | */ |
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47 | #define FRAME_OFFSET GPR2_OFFSET |
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48 | |
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49 | #ifdef RTEMS_PROFILING |
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50 | /* |
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51 | * The PPC_EXC_MINIMAL_FRAME_SIZE is enough to store this additional register. |
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52 | */ |
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53 | #define ENTRY_INSTANT_REGISTER r15 |
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54 | #define ENTRY_INSTANT_OFFSET GPR13_OFFSET |
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55 | |
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56 | .macro GET_TIME_BASE REG |
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57 | #ifdef ppc8540 |
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58 | mfspr \REG, TBRL |
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59 | #else /* ppc8540 */ |
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60 | mftb \REG |
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61 | #endif /* ppc8540 */ |
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62 | .endm |
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63 | #endif /* RTEMS_PROFILING */ |
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64 | |
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65 | #ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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66 | .global bsp_interrupt_dispatch |
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67 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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68 | |
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69 | .global ppc_exc_min_prolog_async_tmpl_normal |
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70 | .global ppc_exc_wrap_async_normal |
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71 | |
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72 | ppc_exc_min_prolog_async_tmpl_normal: |
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73 | |
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74 | stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) |
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75 | |
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76 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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77 | stw VECTOR_REGISTER, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) |
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78 | li VECTOR_REGISTER, 0xffff8000 |
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79 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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80 | |
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81 | /* |
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82 | * We store the absolute branch target address here. It will be used |
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83 | * to generate the branch operation in ppc_exc_make_prologue(). |
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84 | */ |
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85 | .int ppc_exc_wrap_async_normal |
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86 | |
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87 | ppc_exc_wrap_async_normal: |
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88 | |
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89 | #ifdef RTEMS_PROFILING |
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90 | /* Save non-volatile ENTRY_INSTANT_REGISTER */ |
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91 | stw ENTRY_INSTANT_REGISTER, ENTRY_INSTANT_OFFSET(r1) |
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92 | |
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93 | /* Get entry instant */ |
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94 | GET_TIME_BASE ENTRY_INSTANT_REGISTER |
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95 | #endif /* RTEMS_PROFILING */ |
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96 | |
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97 | /* Save non-volatile FRAME_REGISTER */ |
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98 | stw FRAME_REGISTER, FRAME_OFFSET(r1) |
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99 | |
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100 | #ifdef __SPE__ |
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101 | /* Enable SPE */ |
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102 | mfmsr FRAME_REGISTER |
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103 | oris FRAME_REGISTER, FRAME_REGISTER, MSR_SPE >> 16 |
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104 | mtmsr FRAME_REGISTER |
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105 | isync |
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106 | #endif |
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107 | |
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108 | #if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) |
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109 | /* Enable FPU and/or AltiVec */ |
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110 | mfmsr FRAME_REGISTER |
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111 | #ifdef PPC_MULTILIB_FPU |
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112 | ori FRAME_REGISTER, FRAME_REGISTER, MSR_FP |
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113 | #endif |
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114 | #ifdef PPC_MULTILIB_ALTIVEC |
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115 | oris FRAME_REGISTER, FRAME_REGISTER, MSR_VE >> 16 |
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116 | #endif |
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117 | mtmsr FRAME_REGISTER |
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118 | isync |
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119 | #endif |
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120 | |
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121 | /* Move frame pointer to non-volatile FRAME_REGISTER */ |
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122 | mr FRAME_REGISTER, r1 |
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123 | |
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124 | /* Load ISR nest level and thread dispatch disable level */ |
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125 | PPC_GPR_STORE SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1) |
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126 | GET_SELF_CPU_CONTROL SELF_CPU_REGISTER |
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127 | PPC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) |
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128 | lwz ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) |
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129 | PPC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) |
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130 | lwz DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) |
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131 | |
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132 | PPC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) |
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133 | |
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134 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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135 | #ifdef __SPE__ |
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136 | /* |
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137 | * Save high order part of VECTOR_REGISTER here. The low order part |
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138 | * was saved in the minimal prologue. |
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139 | */ |
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140 | evmergehi SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, VECTOR_REGISTER |
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141 | stw SCRATCH_0_REGISTER, VECTOR_OFFSET(r1) |
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142 | #endif |
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143 | #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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144 | /* The vector register has no special purpose in this case */ |
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145 | PPC_GPR_STORE VECTOR_REGISTER, VECTOR_OFFSET(r1) |
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146 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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147 | |
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148 | PPC_GPR_STORE HANDLER_REGISTER, HANDLER_OFFSET(r1) |
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149 | |
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150 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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151 | /* |
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152 | * Load the handler address. Get the handler table index from the |
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153 | * vector number. We have to discard the exception type. Take only |
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154 | * the least significant five bits (= LAST_VALID_EXC + 1) from the |
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155 | * vector register. Multiply by four (= size of function pointer). |
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156 | */ |
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157 | rlwinm SCRATCH_0_REGISTER, VECTOR_REGISTER, 2, 25, 29 |
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158 | lis HANDLER_REGISTER, ppc_exc_handler_table@h |
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159 | ori HANDLER_REGISTER, HANDLER_REGISTER, ppc_exc_handler_table@l |
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160 | lwzx HANDLER_REGISTER, HANDLER_REGISTER, SCRATCH_0_REGISTER |
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161 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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162 | |
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163 | PPC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) |
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164 | PPC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) |
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165 | PPC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) |
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166 | PPC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) |
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167 | PPC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) |
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168 | |
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169 | /* Save SRR0, SRR1, CR, CTR, XER, and LR */ |
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170 | mfsrr0 SCRATCH_0_REGISTER |
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171 | mfsrr1 SCRATCH_1_REGISTER |
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172 | mfcr SCRATCH_2_REGISTER |
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173 | mfctr SCRATCH_3_REGISTER |
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174 | mfxer SCRATCH_4_REGISTER |
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175 | mflr SCRATCH_5_REGISTER |
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176 | stw SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) |
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177 | stw SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) |
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178 | stw SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1) |
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179 | stw SCRATCH_3_REGISTER, EXC_CTR_OFFSET(r1) |
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180 | stw SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) |
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181 | stw SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) |
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182 | |
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183 | #ifdef __SPE__ |
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184 | /* Save SPEFSCR and ACC */ |
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185 | mfspr SCRATCH_0_REGISTER, FSL_EIS_SPEFSCR |
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186 | evxor SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, SCRATCH_1_REGISTER |
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187 | evmwumiaa SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, SCRATCH_1_REGISTER |
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188 | stw SCRATCH_0_REGISTER, PPC_EXC_SPEFSCR_OFFSET(r1) |
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189 | evstdd SCRATCH_1_REGISTER, PPC_EXC_ACC_OFFSET(r1) |
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190 | #endif |
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191 | |
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192 | #ifdef PPC_MULTILIB_ALTIVEC |
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193 | /* Save volatile AltiVec context */ |
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194 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(0) |
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195 | stvx v0, r1, SCRATCH_0_REGISTER |
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196 | mfvscr v0 |
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197 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(1) |
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198 | stvx v1, r1, SCRATCH_0_REGISTER |
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199 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(2) |
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200 | stvx v2, r1, SCRATCH_0_REGISTER |
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201 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(3) |
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202 | stvx v3, r1, SCRATCH_0_REGISTER |
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203 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(4) |
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204 | stvx v4, r1, SCRATCH_0_REGISTER |
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205 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(5) |
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206 | stvx v5, r1, SCRATCH_0_REGISTER |
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207 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(6) |
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208 | stvx v6, r1, SCRATCH_0_REGISTER |
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209 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(7) |
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210 | stvx v7, r1, SCRATCH_0_REGISTER |
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211 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(8) |
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212 | stvx v8, r1, SCRATCH_0_REGISTER |
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213 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(9) |
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214 | stvx v9, r1, SCRATCH_0_REGISTER |
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215 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(10) |
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216 | stvx v10, r1, SCRATCH_0_REGISTER |
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217 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(11) |
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218 | stvx v11, r1, SCRATCH_0_REGISTER |
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219 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(12) |
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220 | stvx v12, r1, SCRATCH_0_REGISTER |
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221 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(13) |
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222 | stvx v13, r1, SCRATCH_0_REGISTER |
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223 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(14) |
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224 | stvx v14, r1, SCRATCH_0_REGISTER |
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225 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(15) |
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226 | stvx v15, r1, SCRATCH_0_REGISTER |
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227 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(16) |
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228 | stvx v16, r1, SCRATCH_0_REGISTER |
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229 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(17) |
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230 | stvx v17, r1, SCRATCH_0_REGISTER |
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231 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(18) |
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232 | stvx v18, r1, SCRATCH_0_REGISTER |
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233 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(19) |
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234 | stvx v19, r1, SCRATCH_0_REGISTER |
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235 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VSCR_OFFSET |
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236 | stvewx v0, r1, SCRATCH_0_REGISTER |
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237 | #endif |
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238 | |
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239 | #ifdef PPC_MULTILIB_FPU |
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240 | /* Save volatile FPU context */ |
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241 | stfd f0, PPC_EXC_MIN_FR_OFFSET(0)(r1) |
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242 | mffs f0 |
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243 | stfd f1, PPC_EXC_MIN_FR_OFFSET(1)(r1) |
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244 | stfd f2, PPC_EXC_MIN_FR_OFFSET(2)(r1) |
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245 | stfd f3, PPC_EXC_MIN_FR_OFFSET(3)(r1) |
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246 | stfd f4, PPC_EXC_MIN_FR_OFFSET(4)(r1) |
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247 | stfd f5, PPC_EXC_MIN_FR_OFFSET(5)(r1) |
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248 | stfd f6, PPC_EXC_MIN_FR_OFFSET(6)(r1) |
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249 | stfd f7, PPC_EXC_MIN_FR_OFFSET(7)(r1) |
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250 | stfd f8, PPC_EXC_MIN_FR_OFFSET(8)(r1) |
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251 | stfd f9, PPC_EXC_MIN_FR_OFFSET(9)(r1) |
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252 | stfd f10, PPC_EXC_MIN_FR_OFFSET(10)(r1) |
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253 | stfd f11, PPC_EXC_MIN_FR_OFFSET(11)(r1) |
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254 | stfd f12, PPC_EXC_MIN_FR_OFFSET(12)(r1) |
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255 | stfd f13, PPC_EXC_MIN_FR_OFFSET(13)(r1) |
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256 | stfd f0, PPC_EXC_MIN_FPSCR_OFFSET(r1) |
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257 | #endif |
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258 | |
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259 | /* Increment ISR nest level and thread dispatch disable level */ |
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260 | cmpwi ISR_NEST_REGISTER, 0 |
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261 | addi ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1 |
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262 | addi DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1 |
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263 | stw ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) |
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264 | stw DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) |
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265 | |
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266 | /* Switch stack if necessary */ |
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267 | mfspr SCRATCH_0_REGISTER, SPRG1 |
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268 | iselgt r1, r1, SCRATCH_0_REGISTER |
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269 | |
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270 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
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271 | /* |
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272 | * Call high level exception handler. |
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273 | * |
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274 | * First parameter = exception frame pointer + FRAME_LINK_SPACE |
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275 | * Second parameter = vector number (r4 is the VECTOR_REGISTER) |
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276 | */ |
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277 | addi r3, FRAME_REGISTER, FRAME_LINK_SPACE |
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278 | rlwinm VECTOR_REGISTER, VECTOR_REGISTER, 0, 27, 31 |
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279 | mtctr HANDLER_REGISTER |
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280 | bctrl |
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281 | #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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282 | /* Call fixed high level handler */ |
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283 | bl bsp_interrupt_dispatch |
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284 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
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285 | |
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286 | /* Load ISR nest level and thread dispatch disable level */ |
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287 | GET_SELF_CPU_CONTROL SELF_CPU_REGISTER |
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288 | lwz ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) |
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289 | lwz DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) |
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290 | |
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291 | /* |
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292 | * Switch back to original stack (FRAME_REGISTER == r1 if we are still |
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293 | * on the IRQ stack) and restore FRAME_REGISTER. |
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294 | */ |
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295 | mr r1, FRAME_REGISTER |
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296 | lwz FRAME_REGISTER, FRAME_OFFSET(r1) |
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297 | |
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298 | /* Decrement ISR nest level and thread dispatch disable level */ |
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299 | #ifdef RTEMS_PROFILING |
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300 | subic. ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1 |
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301 | subi DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1 |
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302 | cmpwi cr2, DISPATCH_LEVEL_REGISTER, 0 |
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303 | #else /* RTEMS_PROFILING */ |
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304 | subi ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1 |
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305 | subic. DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1 |
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306 | #endif /* RTEMS_PROFILING */ |
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307 | stw ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) |
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308 | stw DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) |
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309 | |
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310 | #ifdef RTEMS_PROFILING |
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311 | /* Store profiling data if necessary */ |
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312 | bne profiling_done |
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313 | mr r3, SELF_CPU_REGISTER |
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314 | mr r4, ENTRY_INSTANT_REGISTER |
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315 | GET_TIME_BASE r5 |
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316 | bl _Profiling_Outer_most_interrupt_entry_and_exit |
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317 | profiling_done: |
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318 | #endif /* RTEMS_PROFILING */ |
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319 | |
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320 | /* Call thread dispatcher if necessary */ |
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321 | #ifdef RTEMS_PROFILING |
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322 | bne cr2, thread_dispatching_done |
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323 | #else /* RTEMS_PROFILING */ |
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324 | bne thread_dispatching_done |
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325 | #endif /* RTEMS_PROFILING */ |
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326 | bl _Thread_Dispatch |
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327 | thread_dispatching_done: |
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328 | |
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329 | #ifdef PPC_MULTILIB_ALTIVEC |
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330 | /* Restore volatile AltiVec context */ |
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331 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VSCR_OFFSET |
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332 | lvewx v0, r1, SCRATCH_0_REGISTER |
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333 | mtvscr v0 |
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334 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(0) |
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335 | lvx v0, r1, SCRATCH_0_REGISTER |
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336 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(1) |
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337 | lvx v1, r1, SCRATCH_0_REGISTER |
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338 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(2) |
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339 | lvx v2, r1, SCRATCH_0_REGISTER |
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340 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(3) |
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341 | lvx v3, r1, SCRATCH_0_REGISTER |
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342 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(4) |
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343 | lvx v4, r1, SCRATCH_0_REGISTER |
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344 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(5) |
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345 | lvx v5, r1, SCRATCH_0_REGISTER |
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346 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(6) |
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347 | lvx v6, r1, SCRATCH_0_REGISTER |
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348 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(7) |
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349 | lvx v7, r1, SCRATCH_0_REGISTER |
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350 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(8) |
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351 | lvx v8, r1, SCRATCH_0_REGISTER |
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352 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(9) |
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353 | lvx v9, r1, SCRATCH_0_REGISTER |
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354 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(10) |
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355 | lvx v10, r1, SCRATCH_0_REGISTER |
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356 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(11) |
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357 | lvx v11, r1, SCRATCH_0_REGISTER |
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358 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(12) |
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359 | lvx v12, r1, SCRATCH_0_REGISTER |
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360 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(13) |
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361 | lvx v13, r1, SCRATCH_0_REGISTER |
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362 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(14) |
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363 | lvx v14, r1, SCRATCH_0_REGISTER |
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364 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(15) |
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365 | lvx v15, r1, SCRATCH_0_REGISTER |
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366 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(16) |
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367 | lvx v16, r1, SCRATCH_0_REGISTER |
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368 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(17) |
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369 | lvx v17, r1, SCRATCH_0_REGISTER |
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370 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(18) |
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371 | lvx v18, r1, SCRATCH_0_REGISTER |
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372 | li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(19) |
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373 | lvx v19, r1, SCRATCH_0_REGISTER |
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374 | #endif |
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375 | |
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376 | #ifdef PPC_MULTILIB_FPU |
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377 | /* Restore volatile FPU context */ |
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378 | lfd f0, PPC_EXC_MIN_FPSCR_OFFSET(r1) |
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379 | mtfsf 0xff, f0 |
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380 | lfd f0, PPC_EXC_MIN_FR_OFFSET(0)(r1) |
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381 | lfd f1, PPC_EXC_MIN_FR_OFFSET(1)(r1) |
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382 | lfd f2, PPC_EXC_MIN_FR_OFFSET(2)(r1) |
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383 | lfd f3, PPC_EXC_MIN_FR_OFFSET(3)(r1) |
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384 | lfd f4, PPC_EXC_MIN_FR_OFFSET(4)(r1) |
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385 | lfd f5, PPC_EXC_MIN_FR_OFFSET(5)(r1) |
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386 | lfd f6, PPC_EXC_MIN_FR_OFFSET(6)(r1) |
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387 | lfd f7, PPC_EXC_MIN_FR_OFFSET(7)(r1) |
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388 | lfd f8, PPC_EXC_MIN_FR_OFFSET(8)(r1) |
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389 | lfd f9, PPC_EXC_MIN_FR_OFFSET(9)(r1) |
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390 | lfd f10, PPC_EXC_MIN_FR_OFFSET(10)(r1) |
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391 | lfd f11, PPC_EXC_MIN_FR_OFFSET(11)(r1) |
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392 | lfd f12, PPC_EXC_MIN_FR_OFFSET(12)(r1) |
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393 | lfd f13, PPC_EXC_MIN_FR_OFFSET(13)(r1) |
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394 | #endif |
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395 | |
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396 | #ifdef __SPE__ |
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397 | /* Load SPEFSCR and ACC */ |
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398 | lwz DISPATCH_LEVEL_REGISTER, PPC_EXC_SPEFSCR_OFFSET(r1) |
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399 | evldd HANDLER_REGISTER, PPC_EXC_ACC_OFFSET(r1) |
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400 | #endif |
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401 | |
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402 | /* |
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403 | * We must clear reservations here, since otherwise compare-and-swap |
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404 | * atomic operations with interrupts enabled may yield wrong results. |
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405 | * A compare-and-swap atomic operation is generated by the compiler |
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406 | * like this: |
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407 | * |
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408 | * .L1: |
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409 | * lwarx r9, r0, r3 |
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410 | * cmpw r9, r4 |
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411 | * bne- .L2 |
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412 | * stwcx. r5, r0, r3 |
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413 | * bne- .L1 |
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414 | * .L2: |
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415 | * |
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416 | * Consider the following scenario. A thread is interrupted right |
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417 | * before the stwcx. The interrupt updates the value using a |
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418 | * compare-and-swap sequence. Everything is fine up to this point. |
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419 | * The interrupt performs now a compare-and-swap sequence which fails |
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420 | * with a branch to .L2. The current processor has now a reservation. |
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421 | * The interrupt returns without further stwcx. The thread updates the |
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422 | * value using the unrelated reservation of the interrupt. |
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423 | */ |
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424 | li SCRATCH_0_REGISTER, FRAME_OFFSET |
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425 | stwcx. SCRATCH_0_REGISTER, r1, SCRATCH_0_REGISTER |
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426 | |
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427 | /* Load SRR0, SRR1, CR, CTR, XER, and LR */ |
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428 | lwz SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) |
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429 | lwz SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) |
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430 | lwz SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1) |
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431 | lwz SCRATCH_3_REGISTER, EXC_CTR_OFFSET(r1) |
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432 | lwz SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) |
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433 | lwz SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) |
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434 | |
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435 | PPC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) |
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436 | PPC_GPR_LOAD SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1) |
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437 | PPC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) |
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438 | |
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439 | #ifdef __SPE__ |
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440 | /* Restore SPEFSCR */ |
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441 | mtspr FSL_EIS_SPEFSCR, DISPATCH_LEVEL_REGISTER |
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442 | #endif |
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443 | PPC_GPR_LOAD DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) |
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444 | |
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445 | #ifdef __SPE__ |
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446 | /* Restore ACC */ |
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447 | evmra HANDLER_REGISTER, HANDLER_REGISTER |
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448 | #endif |
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449 | PPC_GPR_LOAD HANDLER_REGISTER, HANDLER_OFFSET(r1) |
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450 | |
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451 | /* Restore SRR0, SRR1, CR, CTR, XER, and LR */ |
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452 | mtsrr0 SCRATCH_0_REGISTER |
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453 | PPC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) |
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454 | mtsrr1 SCRATCH_1_REGISTER |
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455 | PPC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) |
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456 | mtcr SCRATCH_2_REGISTER |
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457 | PPC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) |
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458 | mtctr SCRATCH_3_REGISTER |
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459 | PPC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) |
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460 | mtxer SCRATCH_4_REGISTER |
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461 | PPC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) |
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462 | mtlr SCRATCH_5_REGISTER |
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463 | PPC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) |
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464 | |
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465 | #ifdef RTEMS_PROFILING |
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466 | /* Restore ENTRY_INSTANT_REGISTER */ |
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467 | lwz ENTRY_INSTANT_REGISTER, ENTRY_INSTANT_OFFSET(r1) |
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468 | #endif /* RTEMS_PROFILING */ |
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469 | |
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470 | /* Pop stack */ |
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471 | addi r1, r1, PPC_EXC_MINIMAL_FRAME_SIZE |
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472 | |
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473 | /* Return */ |
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474 | rfi |
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475 | |
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476 | /* Symbol provided for debugging and tracing */ |
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477 | ppc_exc_wrap_async_normal_end: |
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