[94e1931c] | 1 | /* |
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| 2 | * (c) 1999, Eric Valette valette@crf.canon.fr |
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| 3 | * |
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[3550621] | 4 | * Modified and partially rewritten by Till Straumann, 2007-2008 |
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[94e1931c] | 5 | * |
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[4bd4c9e] | 6 | * Modified by Sebastian Huber <sebastian.huber@embedded-brains.de>, 2008-2012. |
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[25a92bc1] | 7 | * |
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[94e1931c] | 8 | * Low-level assembly code for PPC exceptions (macros). |
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| 9 | * |
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| 10 | * This file was written with the goal to eliminate |
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| 11 | * ALL #ifdef <cpu_flavor> conditionals -- please do not |
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| 12 | * reintroduce such statements. |
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| 13 | */ |
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| 14 | |
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[d010b9d] | 15 | #include <bspopts.h> |
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[2d2de4eb] | 16 | #include <bsp/vectors.h> |
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[c6c998b] | 17 | #include <libcpu/powerpc-utility.h> |
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[3550621] | 18 | |
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[25a92bc1] | 19 | #define LT(cr) ((cr)*4+0) |
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| 20 | #define GT(cr) ((cr)*4+1) |
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| 21 | #define EQ(cr) ((cr)*4+2) |
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| 22 | |
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| 23 | /* Opcode of 'stw r1, off(r13)' */ |
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| 24 | #define STW_R1_R13(off) ((((36<<10)|(r1<<5)|(r13))<<16) | ((off)&0xffff)) |
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| 25 | |
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| 26 | #define FRAME_REGISTER r14 |
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| 27 | #define VECTOR_REGISTER r4 |
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| 28 | #define SCRATCH_REGISTER_0 r5 |
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| 29 | #define SCRATCH_REGISTER_1 r6 |
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| 30 | #define SCRATCH_REGISTER_2 r7 |
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| 31 | |
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| 32 | #define FRAME_OFFSET( r) GPR14_OFFSET( r) |
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| 33 | #define VECTOR_OFFSET( r) GPR4_OFFSET( r) |
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| 34 | #define SCRATCH_REGISTER_0_OFFSET( r) GPR5_OFFSET( r) |
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| 35 | #define SCRATCH_REGISTER_1_OFFSET( r) GPR6_OFFSET( r) |
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| 36 | #define SCRATCH_REGISTER_2_OFFSET( r) GPR7_OFFSET( r) |
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| 37 | |
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| 38 | #define CR_TYPE 2 |
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| 39 | #define CR_MSR 3 |
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| 40 | #define CR_LOCK 4 |
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[94e1931c] | 41 | |
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| 42 | /* |
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| 43 | * Minimal prologue snippets: |
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| 44 | * |
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| 45 | * Rationale: on some PPCs the vector offsets are spaced |
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| 46 | * as closely as 16 bytes. |
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| 47 | * |
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| 48 | * If we deal with asynchronous exceptions ('interrupts') |
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| 49 | * then we can use 4 instructions to |
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| 50 | * 1. atomically write lock to indicate ISR is in progress |
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| 51 | * (we cannot atomically increase the Thread_Dispatch_disable_level, |
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| 52 | * see README) |
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| 53 | * 2. save a register in special area |
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| 54 | * 3. load register with vector info |
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| 55 | * 4. branch |
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| 56 | * |
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| 57 | * If we deal with a synchronous exception (no stack switch |
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| 58 | * nor dispatch-disabling necessary) then it's easier: |
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| 59 | * 1. push stack frame |
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| 60 | * 2. save register on stack |
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| 61 | * 3. load register with vector info |
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| 62 | * 4. branch |
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| 63 | * |
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[359e537] | 64 | */ |
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[3550621] | 65 | |
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| 66 | /* |
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[25a92bc1] | 67 | ***************************************************************************** |
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[3550621] | 68 | * MACRO: PPC_EXC_MIN_PROLOG_ASYNC |
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[25a92bc1] | 69 | ***************************************************************************** |
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| 70 | * USES: VECTOR_REGISTER |
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| 71 | * ON EXIT: Vector in VECTOR_REGISTER |
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[3550621] | 72 | * |
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[25a92bc1] | 73 | * NOTES: VECTOR_REGISTER saved in special variable |
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| 74 | * 'ppc_exc_vector_register_\_PRI'. |
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[3550621] | 75 | * |
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| 76 | */ |
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[94e1931c] | 77 | .macro PPC_EXC_MIN_PROLOG_ASYNC _NAME _VEC _PRI _FLVR |
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[25a92bc1] | 78 | |
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[94e1931c] | 79 | .global ppc_exc_min_prolog_async_\_NAME |
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| 80 | ppc_exc_min_prolog_async_\_NAME: |
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[25a92bc1] | 81 | /* Atomically write lock variable in 1st instruction with non-zero |
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| 82 | * value (r1 is always nonzero; r13 could also be used) |
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[3550621] | 83 | * |
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| 84 | * NOTE: raising an exception and executing this first instruction |
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[25a92bc1] | 85 | * of the exception handler is apparently NOT atomic, i.e., a |
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| 86 | * low-priority IRQ could set the PC to this location and a |
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| 87 | * critical IRQ could intervene just at this point. |
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[3550621] | 88 | * |
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| 89 | * We check against this pathological case by checking the |
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| 90 | * opcode/instruction at the interrupted PC for matching |
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| 91 | * |
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| 92 | * stw r1, ppc_exc_lock_XXX@sdarel(r13) |
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| 93 | * |
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| 94 | * ASSUMPTION: |
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| 95 | * 1) ALL 'asynchronous' exceptions (which disable thread- |
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| 96 | * dispatching) execute THIS 'magical' instruction |
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| 97 | * FIRST. |
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| 98 | * 2) This instruction (including the address offset) |
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| 99 | * is not used anywhere else (probably a safe assumption). |
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[94e1931c] | 100 | */ |
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[25a92bc1] | 101 | stw r1, ppc_exc_lock_\_PRI@sdarel(r13) |
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| 102 | /* We have no stack frame yet; store VECTOR_REGISTER in special area; |
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[94e1931c] | 103 | * a higher-priority (critical) interrupt uses a different area |
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[359e537] | 104 | * (hence the different prologue snippets) (\PRI) |
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[94e1931c] | 105 | */ |
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[25a92bc1] | 106 | stw VECTOR_REGISTER, ppc_exc_vector_register_\_PRI@sdarel(r13) |
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| 107 | /* Load vector. |
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[94e1931c] | 108 | */ |
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[25a92bc1] | 109 | li VECTOR_REGISTER, ( \_VEC | 0xffff8000 ) |
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[10df690] | 110 | |
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| 111 | /* |
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| 112 | * We store the absolute branch target address here. It will be used |
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| 113 | * to generate the branch operation in ppc_exc_make_prologue(). |
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[94e1931c] | 114 | */ |
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[10df690] | 115 | .int ppc_exc_wrap_\_FLVR |
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[25a92bc1] | 116 | |
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[94e1931c] | 117 | .endm |
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| 118 | |
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[3550621] | 119 | /* |
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[25a92bc1] | 120 | ***************************************************************************** |
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[3550621] | 121 | * MACRO: PPC_EXC_MIN_PROLOG_SYNC |
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[25a92bc1] | 122 | ***************************************************************************** |
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| 123 | * USES: VECTOR_REGISTER |
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| 124 | * ON EXIT: vector in VECTOR_REGISTER |
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[3550621] | 125 | * |
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[25a92bc1] | 126 | * NOTES: exception stack frame pushed; VECTOR_REGISTER saved in frame |
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[3550621] | 127 | * |
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| 128 | */ |
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[25a92bc1] | 129 | .macro PPC_EXC_MIN_PROLOG_SYNC _NAME _VEC _PRI _FLVR |
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| 130 | |
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| 131 | .global ppc_exc_min_prolog_sync_\_NAME |
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[94e1931c] | 132 | ppc_exc_min_prolog_sync_\_NAME: |
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| 133 | stwu r1, -EXCEPTION_FRAME_END(r1) |
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[25a92bc1] | 134 | stw VECTOR_REGISTER, VECTOR_OFFSET(r1) |
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| 135 | li VECTOR_REGISTER, \_VEC |
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[10df690] | 136 | |
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| 137 | /* |
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| 138 | * We store the absolute branch target address here. It will be used |
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| 139 | * to generate the branch operation in ppc_exc_make_prologue(). |
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| 140 | */ |
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| 141 | .int ppc_exc_wrap_nopush_\_FLVR |
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[25a92bc1] | 142 | |
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[94e1931c] | 143 | .endm |
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[359e537] | 144 | |
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[3550621] | 145 | /* |
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[25a92bc1] | 146 | ***************************************************************************** |
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[3550621] | 147 | * MACRO: TEST_1ST_OPCODE_crit |
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[25a92bc1] | 148 | ***************************************************************************** |
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[3550621] | 149 | * |
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[5166513c] | 150 | * USES: REG, cr0 |
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[25a92bc1] | 151 | * ON EXIT: REG available (contains *pc - STW_R1_R13(0)), |
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[5166513c] | 152 | * return value in cr0. |
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[3550621] | 153 | * |
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[25a92bc1] | 154 | * test opcode interrupted by critical (asynchronous) exception; set CR_LOCK if |
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[3550621] | 155 | * |
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[25a92bc1] | 156 | * *SRR0 == 'stw r1, ppc_exc_lock_std@sdarel(r13)' |
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[3550621] | 157 | * |
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| 158 | */ |
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[25a92bc1] | 159 | .macro TEST_1ST_OPCODE_crit _REG |
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| 160 | |
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| 161 | lwz \_REG, SRR0_FRAME_OFFSET(FRAME_REGISTER) |
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| 162 | lwz \_REG, 0(\_REG) |
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| 163 | /* opcode now in REG */ |
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[3550621] | 164 | |
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[25a92bc1] | 165 | /* subtract upper 16bits of 'stw r1, 0(r13)' instruction */ |
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[3550621] | 166 | subis \_REG, \_REG, STW_R1_R13(0)@h |
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| 167 | /* |
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| 168 | * if what's left compares against the 'ppc_exc_lock_std@sdarel' |
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| 169 | * address offset then we have a match... |
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| 170 | */ |
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[c1072919] | 171 | cmplwi cr0, \_REG, ppc_exc_lock_std@sdarel |
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[3550621] | 172 | |
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| 173 | .endm |
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| 174 | |
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| 175 | /* |
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[25a92bc1] | 176 | ***************************************************************************** |
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[3550621] | 177 | * MACRO: TEST_LOCK_std |
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[25a92bc1] | 178 | ***************************************************************************** |
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[3550621] | 179 | * |
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[25a92bc1] | 180 | * USES: CR_LOCK |
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| 181 | * ON EXIT: CR_LOCK is set (indicates no lower-priority locks are engaged) |
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[3550621] | 182 | * |
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| 183 | */ |
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[25a92bc1] | 184 | .macro TEST_LOCK_std _FLVR |
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| 185 | /* 'std' is lowest level, i.e., can not be locked -> EQ(CR_LOCK) = 1 */ |
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| 186 | creqv EQ(CR_LOCK), EQ(CR_LOCK), EQ(CR_LOCK) |
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[94e1931c] | 187 | .endm |
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| 188 | |
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[3550621] | 189 | /* |
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[25a92bc1] | 190 | ****************************************************************************** |
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[3550621] | 191 | * MACRO: TEST_LOCK_crit |
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[25a92bc1] | 192 | ****************************************************************************** |
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[3550621] | 193 | * |
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[25a92bc1] | 194 | * USES: CR_LOCK, cr0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1 |
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| 195 | * ON EXIT: cr0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1 available, |
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| 196 | * returns result in CR_LOCK. |
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[3550621] | 197 | * |
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| 198 | * critical-exception wrapper has to check 'std' lock: |
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| 199 | * |
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[5166513c] | 200 | * Return CR_LOCK = ( (interrupt_mask & MSR_CE) != 0 |
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| 201 | && ppc_lock_std == 0 |
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[25a92bc1] | 202 | * && * SRR0 != <write std lock instruction> ) |
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[3550621] | 203 | * |
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| 204 | */ |
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[25a92bc1] | 205 | .macro TEST_LOCK_crit _FLVR |
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[5166513c] | 206 | /* If MSR_CE is not in the IRQ mask then we must never allow |
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| 207 | * thread-dispatching! |
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| 208 | */ |
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| 209 | GET_INTERRUPT_MASK mask=SCRATCH_REGISTER_1 |
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| 210 | /* EQ(cr0) = ((interrupt_mask & MSR_CE) == 0) */ |
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| 211 | andis. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_CE@h |
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[359e537] | 212 | beq TEST_LOCK_crit_done_\_FLVR |
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[25a92bc1] | 213 | |
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| 214 | /* STD interrupt could have been interrupted before executing the 1st |
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| 215 | * instruction which sets the lock; check this case by looking at the |
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| 216 | * opcode present at the interrupted PC location. |
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[3550621] | 217 | */ |
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[25a92bc1] | 218 | TEST_1ST_OPCODE_crit _REG=SCRATCH_REGISTER_0 |
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[3550621] | 219 | /* |
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[5166513c] | 220 | * At this point cr0 is set if |
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[3550621] | 221 | * |
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| 222 | * *(PC) == 'stw r1, ppc_exc_lock_std@sdarel(r13)' |
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| 223 | * |
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| 224 | */ |
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[359e537] | 225 | |
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[3550621] | 226 | /* check lock */ |
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[25a92bc1] | 227 | lwz SCRATCH_REGISTER_1, ppc_exc_lock_std@sdarel(r13) |
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[5166513c] | 228 | cmplwi CR_LOCK, SCRATCH_REGISTER_1, 0 |
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| 229 | |
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| 230 | /* set EQ(CR_LOCK) to result */ |
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| 231 | TEST_LOCK_crit_done_\_FLVR: |
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| 232 | /* If we end up here because the interrupt mask did not contain |
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| 233 | * MSR_CE then cr0 is set and therefore the value of CR_LOCK |
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| 234 | * does not matter since x && !1 == 0: |
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[3550621] | 235 | * |
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[5166513c] | 236 | * if ( (interrupt_mask & MSR_CE) == 0 ) { |
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| 237 | * EQ(CR_LOCK) = EQ(CR_LOCK) && ! ((interrupt_mask & MSR_CE) == 0) |
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| 238 | * } else { |
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| 239 | * EQ(CR_LOCK) = (ppc_exc_lock_std == 0) && ! (*pc == <write std lock instruction>) |
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| 240 | * } |
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[3550621] | 241 | */ |
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[5166513c] | 242 | crandc EQ(CR_LOCK), EQ(CR_LOCK), EQ(cr0) |
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[25a92bc1] | 243 | |
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[94e1931c] | 244 | .endm |
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| 245 | |
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[3550621] | 246 | /* |
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[25a92bc1] | 247 | ****************************************************************************** |
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[3550621] | 248 | * MACRO: TEST_LOCK_mchk |
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[25a92bc1] | 249 | ****************************************************************************** |
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| 250 | * |
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| 251 | * USES: CR_LOCK |
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| 252 | * ON EXIT: CR_LOCK is cleared. |
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| 253 | * |
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| 254 | * We never want to disable machine-check exceptions to avoid a checkstop. This |
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| 255 | * means that we cannot use enabling/disabling this type of exception for |
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| 256 | * protection of critical OS data structures. Therefore, calling OS primitives |
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| 257 | * from a machine-check handler is ILLEGAL. Since machine-checks can happen |
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| 258 | * anytime it is not legal to perform a context switch (since the exception |
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| 259 | * could hit a IRQ protected section of code). We simply let this test return |
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| 260 | * 0 so that ppc_exc_wrapup is never called after handling a machine-check. |
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[3550621] | 261 | */ |
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[25a92bc1] | 262 | .macro TEST_LOCK_mchk _SRR0 _FLVR |
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| 263 | |
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| 264 | crxor EQ(CR_LOCK), EQ(CR_LOCK), EQ(CR_LOCK) |
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| 265 | |
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[94e1931c] | 266 | .endm |
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[25a92bc1] | 267 | |
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[8bac485] | 268 | /* |
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[25a92bc1] | 269 | ****************************************************************************** |
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| 270 | * MACRO: RECOVER_CHECK_\PRI |
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| 271 | ****************************************************************************** |
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[8bac485] | 272 | * |
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[25a92bc1] | 273 | * USES: cr0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1 |
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| 274 | * ON EXIT: cr0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1 available |
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[8bac485] | 275 | * |
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[25a92bc1] | 276 | * Checks if the exception is recoverable for exceptions which need such a |
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| 277 | * test. |
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[8bac485] | 278 | */ |
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[25a92bc1] | 279 | |
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| 280 | /* Standard*/ |
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| 281 | .macro RECOVER_CHECK_std _FLVR |
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| 282 | |
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[f665f13] | 283 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
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| 284 | |
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[25a92bc1] | 285 | /* Check if exception is recoverable */ |
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| 286 | lwz SCRATCH_REGISTER_0, SRR1_FRAME_OFFSET(FRAME_REGISTER) |
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| 287 | lwz SCRATCH_REGISTER_1, ppc_exc_msr_bits@sdarel(r13) |
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| 288 | xor SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0 |
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| 289 | andi. SCRATCH_REGISTER_0, SCRATCH_REGISTER_1, MSR_RI |
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| 290 | |
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| 291 | recover_check_twiddle_std_\_FLVR: |
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| 292 | |
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| 293 | /* Not recoverable? */ |
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| 294 | bne recover_check_twiddle_std_\_FLVR |
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| 295 | |
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[f665f13] | 296 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
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| 297 | |
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[8bac485] | 298 | .endm |
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[94e1931c] | 299 | |
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[25a92bc1] | 300 | /* Critical */ |
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| 301 | .macro RECOVER_CHECK_crit _FLVR |
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| 302 | |
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| 303 | /* Nothing to do */ |
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| 304 | |
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| 305 | .endm |
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| 306 | |
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| 307 | /* Machine check */ |
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| 308 | .macro RECOVER_CHECK_mchk _FLVR |
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| 309 | |
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[f665f13] | 310 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
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| 311 | |
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[25a92bc1] | 312 | /* Check if exception is recoverable */ |
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| 313 | lwz SCRATCH_REGISTER_0, SRR1_FRAME_OFFSET(FRAME_REGISTER) |
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| 314 | lwz SCRATCH_REGISTER_1, ppc_exc_msr_bits@sdarel(r13) |
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| 315 | xor SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0 |
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| 316 | andi. SCRATCH_REGISTER_0, SCRATCH_REGISTER_1, MSR_RI |
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| 317 | |
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| 318 | recover_check_twiddle_mchk_\_FLVR: |
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| 319 | |
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| 320 | /* Not recoverable? */ |
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| 321 | bne recover_check_twiddle_mchk_\_FLVR |
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| 322 | |
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[f665f13] | 323 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
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| 324 | |
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[25a92bc1] | 325 | .endm |
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[3550621] | 326 | |
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| 327 | /* |
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[25a92bc1] | 328 | ****************************************************************************** |
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[3550621] | 329 | * MACRO: WRAP |
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[25a92bc1] | 330 | ****************************************************************************** |
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| 331 | * |
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| 332 | * Minimal prologue snippets jump into WRAP which calls the high level |
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| 333 | * exception handler. We must have this macro instantiated for each possible |
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| 334 | * flavor of exception so that we use the proper lock variable, SRR register |
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| 335 | * pair and RFI instruction. |
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| 336 | * |
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| 337 | * We have two types of exceptions: synchronous and asynchronous (= interrupt |
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| 338 | * like). The type is encoded in the vector register (= VECTOR_REGISTER). For |
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| 339 | * interrupt like exceptions the MSB in the vector register is set. The |
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| 340 | * exception type is kept in the comparison register CR_TYPE. Normal |
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| 341 | * exceptions (MSB is clear) use the task stack and a context switch may happen |
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| 342 | * at any time. The interrupt like exceptions disable thread dispatching and |
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| 343 | * switch to the interrupt stack (base address is in SPRG1). |
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| 344 | * |
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| 345 | * + |
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| 346 | * | |
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| 347 | * | Minimal prologue |
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| 348 | * | |
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| 349 | * + |
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| 350 | * | |
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| 351 | * | o Setup frame pointer |
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| 352 | * | o Save basic registers |
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| 353 | * | o Determine exception type: |
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| 354 | * | synchronous or asynchronous |
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| 355 | * | |
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| 356 | * +-----+ |
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| 357 | * Synchronous exceptions: | | Asynchronous exceptions: |
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| 358 | * | | |
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| 359 | * Save non-volatile registers | | o Increment thread dispatch |
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| 360 | * | | disable level |
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| 361 | * | | o Increment ISR nest level |
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| 362 | * | | o Clear lock |
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| 363 | * | | o Switch stack if necessary |
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| 364 | * | | |
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| 365 | * +---->+ |
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| 366 | * | |
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| 367 | * | o Save volatile registers |
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| 368 | * | o Change MSR if necessary |
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| 369 | * | o Call high level handler |
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| 370 | * | o Call global handler if necessary |
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| 371 | * | o Check if exception is recoverable |
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| 372 | * | |
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| 373 | * +-----+ |
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| 374 | * Synchronous exceptions: | | Asynchronous exceptions: |
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| 375 | * | | |
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| 376 | * Restore non-volatile registers | | o Decrement ISR nest level |
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| 377 | * | | o Switch stack |
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| 378 | * | | o Decrement thread dispatch |
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| 379 | * | | disable level |
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| 380 | * | | o Test lock |
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| 381 | * | | o May do a context switch |
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| 382 | * | | |
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| 383 | * +---->+ |
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| 384 | * | |
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| 385 | * | o Restore MSR if necessary |
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| 386 | * | o Restore volatile registers |
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| 387 | * | o Restore frame pointer |
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| 388 | * | o Return |
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| 389 | * | |
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| 390 | * + |
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[3550621] | 391 | */ |
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[94e1931c] | 392 | .macro WRAP _FLVR _PRI _SRR0 _SRR1 _RFI |
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[25a92bc1] | 393 | |
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[10df690] | 394 | .global ppc_exc_wrap_\_FLVR |
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| 395 | ppc_exc_wrap_\_FLVR: |
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[25a92bc1] | 396 | |
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| 397 | /* Push exception frame */ |
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| 398 | stwu r1, -EXCEPTION_FRAME_END(r1) |
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| 399 | |
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[10df690] | 400 | .global ppc_exc_wrap_nopush_\_FLVR |
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| 401 | ppc_exc_wrap_nopush_\_FLVR: |
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[25a92bc1] | 402 | |
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| 403 | /* Save frame register */ |
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| 404 | stw FRAME_REGISTER, FRAME_OFFSET(r1) |
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| 405 | |
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| 406 | wrap_no_save_frame_register_\_FLVR: |
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| 407 | |
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| 408 | /* |
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| 409 | * We save at first only some scratch registers |
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| 410 | * and the CR. We use a non-volatile register |
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| 411 | * for the exception frame pointer (= FRAME_REGISTER). |
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| 412 | */ |
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| 413 | |
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| 414 | /* Move frame address in non-volatile FRAME_REGISTER */ |
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| 415 | mr FRAME_REGISTER, r1 |
---|
| 416 | |
---|
| 417 | /* Save scratch registers */ |
---|
| 418 | stw SCRATCH_REGISTER_0, SCRATCH_REGISTER_0_OFFSET(FRAME_REGISTER) |
---|
| 419 | stw SCRATCH_REGISTER_1, SCRATCH_REGISTER_1_OFFSET(FRAME_REGISTER) |
---|
| 420 | stw SCRATCH_REGISTER_2, SCRATCH_REGISTER_2_OFFSET(FRAME_REGISTER) |
---|
| 421 | |
---|
| 422 | /* Save CR */ |
---|
| 423 | mfcr SCRATCH_REGISTER_0 |
---|
| 424 | stw SCRATCH_REGISTER_0, EXC_CR_OFFSET(FRAME_REGISTER) |
---|
| 425 | |
---|
| 426 | /* Check exception type and remember it in non-volatile CR_TYPE */ |
---|
| 427 | cmpwi CR_TYPE, VECTOR_REGISTER, 0 |
---|
| 428 | |
---|
| 429 | /* |
---|
| 430 | * Depending on the exception type we do now save the non-volatile |
---|
| 431 | * registers or disable thread dispatching and switch to the ISR stack. |
---|
| 432 | */ |
---|
| 433 | |
---|
| 434 | /* Branch for synchronous exceptions */ |
---|
| 435 | bge CR_TYPE, wrap_save_non_volatile_regs_\_FLVR |
---|
| 436 | |
---|
| 437 | /* |
---|
| 438 | * Increment the thread dispatch disable level in case a higher |
---|
| 439 | * priority exception occurs we don't want it to run the scheduler. It |
---|
| 440 | * is safe to increment this without disabling higher priority |
---|
| 441 | * exceptions since those will see that we wrote the lock anyways. |
---|
[94e1931c] | 442 | */ |
---|
| 443 | |
---|
[25a92bc1] | 444 | /* Increment ISR nest level and thread dispatch disable level */ |
---|
[c6c998b] | 445 | GET_SELF_CPU_CONTROL SCRATCH_REGISTER_2 |
---|
| 446 | lwz SCRATCH_REGISTER_0, PER_CPU_ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) |
---|
| 447 | lwz SCRATCH_REGISTER_1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_REGISTER_2) |
---|
[25a92bc1] | 448 | addi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1 |
---|
| 449 | addi SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1 |
---|
[c6c998b] | 450 | stw SCRATCH_REGISTER_0, PER_CPU_ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) |
---|
| 451 | stw SCRATCH_REGISTER_1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_REGISTER_2) |
---|
[25a92bc1] | 452 | |
---|
| 453 | /* |
---|
| 454 | * No higher-priority exception occurring after this point |
---|
| 455 | * can cause a context switch. |
---|
[94e1931c] | 456 | */ |
---|
| 457 | |
---|
[25a92bc1] | 458 | /* Clear lock */ |
---|
| 459 | li SCRATCH_REGISTER_0, 0 |
---|
| 460 | stw SCRATCH_REGISTER_0, ppc_exc_lock_\_PRI@sdarel(r13) |
---|
| 461 | |
---|
| 462 | /* Switch stack if necessary */ |
---|
| 463 | mfspr SCRATCH_REGISTER_0, SPRG1 |
---|
| 464 | cmpw SCRATCH_REGISTER_0, r1 |
---|
| 465 | blt wrap_stack_switch_\_FLVR |
---|
| 466 | mfspr SCRATCH_REGISTER_1, SPRG2 |
---|
| 467 | cmpw SCRATCH_REGISTER_1, r1 |
---|
| 468 | blt wrap_stack_switch_done_\_FLVR |
---|
| 469 | |
---|
| 470 | wrap_stack_switch_\_FLVR: |
---|
| 471 | |
---|
| 472 | mr r1, SCRATCH_REGISTER_0 |
---|
[94e1931c] | 473 | |
---|
[25a92bc1] | 474 | wrap_stack_switch_done_\_FLVR: |
---|
| 475 | |
---|
| 476 | /* |
---|
| 477 | * Load the pristine VECTOR_REGISTER from a special location for |
---|
| 478 | * asynchronous exceptions. The synchronous exceptions save the |
---|
| 479 | * VECTOR_REGISTER in their minimal prologue. |
---|
[94e1931c] | 480 | */ |
---|
[25a92bc1] | 481 | lwz SCRATCH_REGISTER_2, ppc_exc_vector_register_\_PRI@sdarel(r13) |
---|
| 482 | |
---|
| 483 | /* Save pristine vector register */ |
---|
| 484 | stw SCRATCH_REGISTER_2, VECTOR_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 485 | |
---|
[25a92bc1] | 486 | wrap_disable_thread_dispatching_done_\_FLVR: |
---|
| 487 | |
---|
| 488 | /* |
---|
| 489 | * We now have SCRATCH_REGISTER_0, SCRATCH_REGISTER_1, |
---|
| 490 | * SCRATCH_REGISTER_2 and CR available. VECTOR_REGISTER still holds |
---|
| 491 | * the vector (and exception type). FRAME_REGISTER is a pointer to the |
---|
| 492 | * exception frame (always on the stack of the interrupted context). |
---|
| 493 | * r1 is the stack pointer, either on the task stack or on the ISR |
---|
| 494 | * stack. CR_TYPE holds the exception type. |
---|
[94e1931c] | 495 | */ |
---|
| 496 | |
---|
[25a92bc1] | 497 | /* Save SRR0 */ |
---|
| 498 | mfspr SCRATCH_REGISTER_0, \_SRR0 |
---|
| 499 | stw SCRATCH_REGISTER_0, SRR0_FRAME_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 500 | |
---|
[25a92bc1] | 501 | /* Save SRR1 */ |
---|
| 502 | mfspr SCRATCH_REGISTER_0, \_SRR1 |
---|
| 503 | stw SCRATCH_REGISTER_0, SRR1_FRAME_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 504 | |
---|
[25a92bc1] | 505 | /* Save CTR */ |
---|
| 506 | mfctr SCRATCH_REGISTER_0 |
---|
| 507 | stw SCRATCH_REGISTER_0, EXC_CTR_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 508 | |
---|
[25a92bc1] | 509 | /* Save XER */ |
---|
| 510 | mfxer SCRATCH_REGISTER_0 |
---|
| 511 | stw SCRATCH_REGISTER_0, EXC_XER_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 512 | |
---|
[25a92bc1] | 513 | /* Save LR */ |
---|
| 514 | mflr SCRATCH_REGISTER_0 |
---|
| 515 | stw SCRATCH_REGISTER_0, EXC_LR_OFFSET(FRAME_REGISTER) |
---|
[94e1931c] | 516 | |
---|
[25a92bc1] | 517 | /* Save volatile registers */ |
---|
| 518 | stw r0, GPR0_OFFSET(FRAME_REGISTER) |
---|
| 519 | stw r3, GPR3_OFFSET(FRAME_REGISTER) |
---|
| 520 | stw r8, GPR8_OFFSET(FRAME_REGISTER) |
---|
| 521 | stw r9, GPR9_OFFSET(FRAME_REGISTER) |
---|
| 522 | stw r10, GPR10_OFFSET(FRAME_REGISTER) |
---|
| 523 | stw r11, GPR11_OFFSET(FRAME_REGISTER) |
---|
| 524 | stw r12, GPR12_OFFSET(FRAME_REGISTER) |
---|
| 525 | |
---|
| 526 | /* Save read-only small data area anchor (EABI) */ |
---|
| 527 | stw r2, GPR2_OFFSET(FRAME_REGISTER) |
---|
| 528 | |
---|
| 529 | /* Save vector number and exception type */ |
---|
| 530 | stw VECTOR_REGISTER, EXCEPTION_NUMBER_OFFSET(FRAME_REGISTER) |
---|
| 531 | |
---|
[f665f13] | 532 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
---|
| 533 | |
---|
[25a92bc1] | 534 | /* Load MSR bit mask */ |
---|
| 535 | lwz SCRATCH_REGISTER_0, ppc_exc_msr_bits@sdarel(r13) |
---|
| 536 | |
---|
| 537 | /* |
---|
| 538 | * Change the MSR if necessary (MMU, RI), |
---|
| 539 | * remember decision in non-volatile CR_MSR |
---|
| 540 | */ |
---|
| 541 | cmpwi CR_MSR, SCRATCH_REGISTER_0, 0 |
---|
| 542 | bne CR_MSR, wrap_change_msr_\_FLVR |
---|
| 543 | |
---|
| 544 | wrap_change_msr_done_\_FLVR: |
---|
| 545 | |
---|
[f665f13] | 546 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
---|
| 547 | |
---|
[c7f8408d] | 548 | #ifdef __ALTIVEC__ |
---|
| 549 | LA SCRATCH_REGISTER_0, _CPU_save_altivec_volatile |
---|
| 550 | mtctr SCRATCH_REGISTER_0 |
---|
| 551 | addi r3, FRAME_REGISTER, EXC_VEC_OFFSET |
---|
| 552 | bctrl |
---|
| 553 | /* |
---|
| 554 | * Establish defaults for vrsave and vscr |
---|
| 555 | */ |
---|
| 556 | li SCRATCH_REGISTER_0, 0 |
---|
| 557 | mtvrsave SCRATCH_REGISTER_0 |
---|
| 558 | /* |
---|
| 559 | * Use java/c9x mode; clear saturation bit |
---|
| 560 | */ |
---|
| 561 | vxor 0, 0, 0 |
---|
| 562 | mtvscr 0 |
---|
| 563 | /* |
---|
| 564 | * Reload VECTOR_REGISTER |
---|
| 565 | */ |
---|
| 566 | lwz VECTOR_REGISTER, EXCEPTION_NUMBER_OFFSET(FRAME_REGISTER) |
---|
| 567 | #endif |
---|
| 568 | |
---|
[25a92bc1] | 569 | /* |
---|
| 570 | * Call high level exception handler |
---|
| 571 | */ |
---|
| 572 | |
---|
| 573 | /* |
---|
| 574 | * Get the handler table index from the vector number. We have to |
---|
| 575 | * discard the exception type. Take only the least significant five |
---|
| 576 | * bits (= LAST_VALID_EXC + 1) from the vector register. Multiply by |
---|
| 577 | * four (= size of function pointer). |
---|
[94e1931c] | 578 | */ |
---|
[25a92bc1] | 579 | rlwinm SCRATCH_REGISTER_1, VECTOR_REGISTER, 2, 25, 29 |
---|
| 580 | |
---|
| 581 | /* Load handler table address */ |
---|
| 582 | LA SCRATCH_REGISTER_0, ppc_exc_handler_table |
---|
[94e1931c] | 583 | |
---|
[25a92bc1] | 584 | /* Load handler address */ |
---|
| 585 | lwzx SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1 |
---|
[94e1931c] | 586 | |
---|
[3550621] | 587 | /* |
---|
[25a92bc1] | 588 | * First parameter = exception frame pointer + FRAME_LINK_SPACE |
---|
[3550621] | 589 | * |
---|
[25a92bc1] | 590 | * We add FRAME_LINK_SPACE to the frame pointer because the high level |
---|
| 591 | * handler expects a BSP_Exception_frame structure. |
---|
[3550621] | 592 | */ |
---|
[359e537] | 593 | addi r3, FRAME_REGISTER, FRAME_LINK_SPACE |
---|
[94e1931c] | 594 | |
---|
[25a92bc1] | 595 | /* |
---|
| 596 | * Second parameter = vector number (r4 is the VECTOR_REGISTER) |
---|
[3550621] | 597 | * |
---|
[25a92bc1] | 598 | * Discard the exception type and store the vector number |
---|
| 599 | * in the vector register. Take only the least significant |
---|
| 600 | * five bits (= LAST_VALID_EXC + 1). |
---|
| 601 | */ |
---|
| 602 | rlwinm VECTOR_REGISTER, VECTOR_REGISTER, 0, 27, 31 |
---|
| 603 | |
---|
| 604 | /* Call handler */ |
---|
| 605 | mtctr SCRATCH_REGISTER_0 |
---|
| 606 | bctrl |
---|
| 607 | |
---|
| 608 | /* Check return value and call global handler if necessary */ |
---|
| 609 | cmpwi r3, 0 |
---|
| 610 | bne wrap_call_global_handler_\_FLVR |
---|
| 611 | |
---|
| 612 | wrap_handler_done_\_FLVR: |
---|
| 613 | |
---|
| 614 | /* Check if exception is recoverable */ |
---|
| 615 | RECOVER_CHECK_\_PRI _FLVR=\_FLVR |
---|
| 616 | |
---|
| 617 | /* |
---|
| 618 | * Depending on the exception type we do now restore the non-volatile |
---|
| 619 | * registers or enable thread dispatching and switch back from the ISR |
---|
| 620 | * stack. |
---|
| 621 | */ |
---|
| 622 | |
---|
| 623 | /* Branch for synchronous exceptions */ |
---|
| 624 | bge CR_TYPE, wrap_restore_non_volatile_regs_\_FLVR |
---|
| 625 | |
---|
| 626 | /* |
---|
| 627 | * Switch back to original stack (FRAME_REGISTER == r1 if we are still |
---|
| 628 | * on the IRQ stack). |
---|
| 629 | */ |
---|
| 630 | mr r1, FRAME_REGISTER |
---|
| 631 | |
---|
| 632 | /* |
---|
| 633 | * Check thread dispatch disable level AND lower priority locks (in |
---|
| 634 | * CR_LOCK): ONLY if the thread dispatch disable level == 0 AND no lock |
---|
| 635 | * is set then call ppc_exc_wrapup() which may do a context switch. We |
---|
| 636 | * can skip TEST_LOCK, because it has no side effects. |
---|
| 637 | */ |
---|
| 638 | |
---|
| 639 | /* Decrement ISR nest level and thread dispatch disable level */ |
---|
[c6c998b] | 640 | GET_SELF_CPU_CONTROL SCRATCH_REGISTER_2 |
---|
| 641 | lwz SCRATCH_REGISTER_0, PER_CPU_ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) |
---|
| 642 | lwz SCRATCH_REGISTER_1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_REGISTER_2) |
---|
[25a92bc1] | 643 | subi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1 |
---|
| 644 | subic. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1 |
---|
[c6c998b] | 645 | stw SCRATCH_REGISTER_0, PER_CPU_ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) |
---|
| 646 | stw SCRATCH_REGISTER_1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_REGISTER_2) |
---|
[25a92bc1] | 647 | |
---|
| 648 | /* Branch to skip thread dispatching */ |
---|
| 649 | bne wrap_thread_dispatching_done_\_FLVR |
---|
| 650 | |
---|
| 651 | /* Test lower-priority locks (result in non-volatile CR_LOCK) */ |
---|
| 652 | TEST_LOCK_\_PRI _FLVR=\_FLVR |
---|
| 653 | |
---|
| 654 | /* Branch to skip thread dispatching */ |
---|
| 655 | bne CR_LOCK, wrap_thread_dispatching_done_\_FLVR |
---|
| 656 | |
---|
| 657 | /* Load address of ppc_exc_wrapup() */ |
---|
| 658 | LA SCRATCH_REGISTER_0, ppc_exc_wrapup |
---|
| 659 | |
---|
| 660 | /* First parameter = exception frame pointer + FRAME_LINK_SPACE */ |
---|
[359e537] | 661 | addi r3, FRAME_REGISTER, FRAME_LINK_SPACE |
---|
[25a92bc1] | 662 | |
---|
| 663 | /* Call ppc_exc_wrapup() */ |
---|
| 664 | mtctr SCRATCH_REGISTER_0 |
---|
| 665 | bctrl |
---|
| 666 | |
---|
| 667 | wrap_thread_dispatching_done_\_FLVR: |
---|
| 668 | |
---|
[c7f8408d] | 669 | #ifdef __ALTIVEC__ |
---|
| 670 | LA SCRATCH_REGISTER_0, _CPU_load_altivec_volatile |
---|
| 671 | mtctr SCRATCH_REGISTER_0 |
---|
| 672 | addi r3, FRAME_REGISTER, EXC_VEC_OFFSET |
---|
| 673 | bctrl |
---|
| 674 | #endif |
---|
| 675 | |
---|
[f665f13] | 676 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
---|
| 677 | |
---|
[25a92bc1] | 678 | /* Restore MSR? */ |
---|
| 679 | bne CR_MSR, wrap_restore_msr_\_FLVR |
---|
| 680 | |
---|
| 681 | wrap_restore_msr_done_\_FLVR: |
---|
| 682 | |
---|
[f665f13] | 683 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
---|
| 684 | |
---|
[25a92bc1] | 685 | /* |
---|
| 686 | * At this point r1 is a valid exception frame pointer and |
---|
| 687 | * FRAME_REGISTER is no longer needed. |
---|
| 688 | */ |
---|
| 689 | |
---|
| 690 | /* Restore frame register */ |
---|
| 691 | lwz FRAME_REGISTER, FRAME_OFFSET(r1) |
---|
| 692 | |
---|
| 693 | /* Restore XER and CTR */ |
---|
[359e537] | 694 | lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1) |
---|
[25a92bc1] | 695 | lwz SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) |
---|
| 696 | mtxer SCRATCH_REGISTER_0 |
---|
| 697 | mtctr SCRATCH_REGISTER_1 |
---|
| 698 | |
---|
| 699 | /* Restore CR and LR */ |
---|
| 700 | lwz SCRATCH_REGISTER_0, EXC_CR_OFFSET(r1) |
---|
| 701 | lwz SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1) |
---|
| 702 | mtcr SCRATCH_REGISTER_0 |
---|
| 703 | mtlr SCRATCH_REGISTER_1 |
---|
| 704 | |
---|
| 705 | /* Restore volatile registers */ |
---|
| 706 | lwz r0, GPR0_OFFSET(r1) |
---|
| 707 | lwz r3, GPR3_OFFSET(r1) |
---|
| 708 | lwz r8, GPR8_OFFSET(r1) |
---|
| 709 | lwz r9, GPR9_OFFSET(r1) |
---|
| 710 | lwz r10, GPR10_OFFSET(r1) |
---|
| 711 | lwz r11, GPR11_OFFSET(r1) |
---|
| 712 | lwz r12, GPR12_OFFSET(r1) |
---|
| 713 | |
---|
| 714 | /* Restore read-only small data area anchor (EABI) */ |
---|
| 715 | lwz r2, GPR2_OFFSET(r1) |
---|
| 716 | |
---|
| 717 | /* Restore vector register */ |
---|
| 718 | lwz VECTOR_REGISTER, VECTOR_OFFSET(r1) |
---|
| 719 | |
---|
| 720 | /* |
---|
| 721 | * Disable all asynchronous exceptions which can do a thread dispatch. |
---|
| 722 | * See README. |
---|
[3550621] | 723 | */ |
---|
[25a92bc1] | 724 | INTERRUPT_DISABLE SCRATCH_REGISTER_1, SCRATCH_REGISTER_0 |
---|
| 725 | |
---|
| 726 | /* Restore scratch registers and SRRs */ |
---|
| 727 | lwz SCRATCH_REGISTER_0, SRR0_FRAME_OFFSET(r1) |
---|
| 728 | lwz SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) |
---|
| 729 | lwz SCRATCH_REGISTER_2, SCRATCH_REGISTER_2_OFFSET(r1) |
---|
| 730 | mtspr \_SRR0, SCRATCH_REGISTER_0 |
---|
| 731 | lwz SCRATCH_REGISTER_0, SCRATCH_REGISTER_0_OFFSET(r1) |
---|
| 732 | mtspr \_SRR1, SCRATCH_REGISTER_1 |
---|
| 733 | lwz SCRATCH_REGISTER_1, SCRATCH_REGISTER_1_OFFSET(r1) |
---|
| 734 | |
---|
| 735 | /* |
---|
| 736 | * We restore r1 from the frame rather than just popping (adding to |
---|
| 737 | * current r1) since the exception handler might have done strange |
---|
| 738 | * things (e.g. a debugger moving and relocating the stack). |
---|
| 739 | */ |
---|
| 740 | lwz r1, 0(r1) |
---|
| 741 | |
---|
| 742 | /* Return */ |
---|
[94e1931c] | 743 | \_RFI |
---|
[25a92bc1] | 744 | |
---|
[f665f13] | 745 | #ifndef PPC_EXC_CONFIG_BOOKE_ONLY |
---|
| 746 | |
---|
[25a92bc1] | 747 | wrap_change_msr_\_FLVR: |
---|
| 748 | |
---|
| 749 | mfmsr SCRATCH_REGISTER_1 |
---|
| 750 | or SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0 |
---|
| 751 | mtmsr SCRATCH_REGISTER_1 |
---|
| 752 | msync |
---|
| 753 | isync |
---|
| 754 | b wrap_change_msr_done_\_FLVR |
---|
| 755 | |
---|
| 756 | wrap_restore_msr_\_FLVR: |
---|
| 757 | |
---|
| 758 | lwz SCRATCH_REGISTER_0, ppc_exc_msr_bits@sdarel(r13) |
---|
| 759 | mfmsr SCRATCH_REGISTER_1 |
---|
| 760 | andc SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0 |
---|
| 761 | mtmsr SCRATCH_REGISTER_1 |
---|
| 762 | msync |
---|
| 763 | isync |
---|
| 764 | b wrap_restore_msr_done_\_FLVR |
---|
| 765 | |
---|
[f665f13] | 766 | #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ |
---|
| 767 | |
---|
[25a92bc1] | 768 | wrap_save_non_volatile_regs_\_FLVR: |
---|
| 769 | |
---|
| 770 | /* Load pristine stack pointer */ |
---|
| 771 | lwz SCRATCH_REGISTER_1, 0(FRAME_REGISTER) |
---|
| 772 | |
---|
| 773 | /* Save small data area anchor (SYSV) */ |
---|
| 774 | stw r13, GPR13_OFFSET(FRAME_REGISTER) |
---|
| 775 | |
---|
| 776 | /* Save pristine stack pointer */ |
---|
| 777 | stw SCRATCH_REGISTER_1, GPR1_OFFSET(FRAME_REGISTER) |
---|
| 778 | |
---|
| 779 | /* r14 is the FRAME_REGISTER and will be saved elsewhere */ |
---|
| 780 | |
---|
| 781 | /* Save non-volatile registers r15 .. r31 */ |
---|
[fdd9de80] | 782 | #ifndef __SPE__ |
---|
[25a92bc1] | 783 | stmw r15, GPR15_OFFSET(FRAME_REGISTER) |
---|
[fdd9de80] | 784 | #else |
---|
| 785 | stw r15, GPR15_OFFSET(FRAME_REGISTER) |
---|
| 786 | stw r16, GPR16_OFFSET(FRAME_REGISTER) |
---|
| 787 | stw r17, GPR17_OFFSET(FRAME_REGISTER) |
---|
| 788 | stw r18, GPR18_OFFSET(FRAME_REGISTER) |
---|
| 789 | stw r19, GPR19_OFFSET(FRAME_REGISTER) |
---|
| 790 | stw r20, GPR20_OFFSET(FRAME_REGISTER) |
---|
| 791 | stw r21, GPR21_OFFSET(FRAME_REGISTER) |
---|
| 792 | stw r22, GPR22_OFFSET(FRAME_REGISTER) |
---|
| 793 | stw r23, GPR23_OFFSET(FRAME_REGISTER) |
---|
| 794 | stw r24, GPR24_OFFSET(FRAME_REGISTER) |
---|
| 795 | stw r25, GPR25_OFFSET(FRAME_REGISTER) |
---|
| 796 | stw r26, GPR26_OFFSET(FRAME_REGISTER) |
---|
| 797 | stw r27, GPR27_OFFSET(FRAME_REGISTER) |
---|
| 798 | stw r28, GPR28_OFFSET(FRAME_REGISTER) |
---|
| 799 | stw r29, GPR29_OFFSET(FRAME_REGISTER) |
---|
| 800 | stw r30, GPR30_OFFSET(FRAME_REGISTER) |
---|
| 801 | stw r31, GPR31_OFFSET(FRAME_REGISTER) |
---|
| 802 | #endif |
---|
[25a92bc1] | 803 | |
---|
| 804 | b wrap_disable_thread_dispatching_done_\_FLVR |
---|
| 805 | |
---|
| 806 | wrap_restore_non_volatile_regs_\_FLVR: |
---|
| 807 | |
---|
| 808 | /* Load stack pointer */ |
---|
| 809 | lwz SCRATCH_REGISTER_0, GPR1_OFFSET(r1) |
---|
| 810 | |
---|
| 811 | /* Restore small data area anchor (SYSV) */ |
---|
| 812 | lwz r13, GPR13_OFFSET(r1) |
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[359e537] | 813 | |
---|
[25a92bc1] | 814 | /* r14 is the FRAME_REGISTER and will be restored elsewhere */ |
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| 815 | |
---|
| 816 | /* Restore non-volatile registers r15 .. r31 */ |
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[fdd9de80] | 817 | #ifndef __SPE__ |
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[25a92bc1] | 818 | lmw r15, GPR15_OFFSET(r1) |
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[fdd9de80] | 819 | #else |
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| 820 | lwz r15, GPR15_OFFSET(FRAME_REGISTER) |
---|
| 821 | lwz r16, GPR16_OFFSET(FRAME_REGISTER) |
---|
| 822 | lwz r17, GPR17_OFFSET(FRAME_REGISTER) |
---|
| 823 | lwz r18, GPR18_OFFSET(FRAME_REGISTER) |
---|
| 824 | lwz r19, GPR19_OFFSET(FRAME_REGISTER) |
---|
| 825 | lwz r20, GPR20_OFFSET(FRAME_REGISTER) |
---|
| 826 | lwz r21, GPR21_OFFSET(FRAME_REGISTER) |
---|
| 827 | lwz r22, GPR22_OFFSET(FRAME_REGISTER) |
---|
| 828 | lwz r23, GPR23_OFFSET(FRAME_REGISTER) |
---|
| 829 | lwz r24, GPR24_OFFSET(FRAME_REGISTER) |
---|
| 830 | lwz r25, GPR25_OFFSET(FRAME_REGISTER) |
---|
| 831 | lwz r26, GPR26_OFFSET(FRAME_REGISTER) |
---|
| 832 | lwz r27, GPR27_OFFSET(FRAME_REGISTER) |
---|
| 833 | lwz r28, GPR28_OFFSET(FRAME_REGISTER) |
---|
| 834 | lwz r29, GPR29_OFFSET(FRAME_REGISTER) |
---|
| 835 | lwz r30, GPR30_OFFSET(FRAME_REGISTER) |
---|
| 836 | lwz r31, GPR31_OFFSET(FRAME_REGISTER) |
---|
| 837 | #endif |
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[25a92bc1] | 838 | |
---|
| 839 | /* Restore stack pointer */ |
---|
| 840 | stw SCRATCH_REGISTER_0, 0(r1) |
---|
| 841 | |
---|
| 842 | b wrap_thread_dispatching_done_\_FLVR |
---|
| 843 | |
---|
| 844 | wrap_call_global_handler_\_FLVR: |
---|
| 845 | |
---|
| 846 | /* First parameter = exception frame pointer + FRAME_LINK_SPACE */ |
---|
[359e537] | 847 | addi r3, FRAME_REGISTER, FRAME_LINK_SPACE |
---|
[25a92bc1] | 848 | |
---|
[4bd4c9e] | 849 | #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER |
---|
| 850 | |
---|
[25a92bc1] | 851 | /* Load global handler address */ |
---|
| 852 | LW SCRATCH_REGISTER_0, globalExceptHdl |
---|
| 853 | |
---|
| 854 | /* Check address */ |
---|
| 855 | cmpwi SCRATCH_REGISTER_0, 0 |
---|
| 856 | beq wrap_handler_done_\_FLVR |
---|
| 857 | |
---|
| 858 | /* Call global handler */ |
---|
| 859 | mtctr SCRATCH_REGISTER_0 |
---|
| 860 | bctrl |
---|
| 861 | |
---|
[4bd4c9e] | 862 | #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
---|
| 863 | |
---|
| 864 | /* Call fixed global handler */ |
---|
| 865 | bl C_exception_handler |
---|
| 866 | |
---|
| 867 | #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ |
---|
| 868 | |
---|
[25a92bc1] | 869 | b wrap_handler_done_\_FLVR |
---|
| 870 | |
---|
[94e1931c] | 871 | .endm |
---|