source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 2.6 KB
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1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 *
6 * @brief PowerPC Exceptions implementation.
7 */
8
9/*
10 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
11 *                    Canon Centre Recherche France.
12 *
13 * Copyright (C) 2009 embedded brains GmbH.
14 *
15 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
16 * to support 603, 603e, 604, 604e exceptions
17 *
18 * Moved to "libcpu/powerpc/new-exceptions" and consolidated
19 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
20 * to be common for all PPCs with new exceptions.
21 *
22 * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.c".
23 *
24 * The license and distribution terms for this file may be
25 * found in the file LICENSE in this distribution or at
26 * http://www.rtems.org/license/LICENSE.
27 */
28
29#include <rtems.h>
30
31#include <bsp/vectors.h>
32
33/*
34 * XXX: These values are choosen to directly generate the vector offsets for an
35 * e200z1 which has hard wired IVORs (IVOR0=0x00, IVOR1=0x10, IVOR2=0x20, ...).
36 */
37static const uint8_t ivor_values [] = {
38  [ASM_BOOKE_CRIT_VECTOR] = 0,
39  [ASM_MACH_VECTOR] = 1,
40  [ASM_PROT_VECTOR] = 2,
41  [ASM_ISI_VECTOR] = 3,
42  [ASM_EXT_VECTOR] = 4,
43  [ASM_ALIGN_VECTOR] = 5,
44  [ASM_PROG_VECTOR] = 6,
45  [ASM_FLOAT_VECTOR] = 7,
46  [ASM_SYS_VECTOR] = 8,
47  [ASM_BOOKE_APU_VECTOR] = 9,
48  [ASM_BOOKE_DEC_VECTOR] = 10,
49  [ASM_BOOKE_FIT_VECTOR] = 11,
50  [ASM_BOOKE_WDOG_VECTOR] = 12,
51  [ASM_BOOKE_DTLBMISS_VECTOR] = 13,
52  [ASM_BOOKE_ITLBMISS_VECTOR] = 14,
53  [ASM_BOOKE_DEBUG_VECTOR] = 15,
54  [ASM_E500_SPE_UNAVAILABLE_VECTOR] = 16,
55  [ASM_E500_EMB_FP_DATA_VECTOR] = 17,
56  [ASM_E500_EMB_FP_ROUND_VECTOR] = 18,
57  [ASM_E500_PERFMON_VECTOR] = 19
58};
59
60void *ppc_exc_vector_address(unsigned vector, void *vector_base)
61{
62  uintptr_t vector_offset = vector << 8;
63
64  if (ppc_cpu_has_altivec()) {
65    if (vector == ASM_60X_VEC_VECTOR) {
66      vector_offset = ASM_60X_VEC_VECTOR_OFFSET;
67    }
68  }
69
70  if (ppc_cpu_is(PPC_405)) {
71    switch (vector) {
72      case ASM_BOOKE_FIT_VECTOR:
73        vector_offset = ASM_PPC405_FIT_VECTOR_OFFSET;
74        break;
75      case ASM_BOOKE_WDOG_VECTOR:
76        vector_offset = ASM_PPC405_WDOG_VECTOR_OFFSET;
77        break;
78      case ASM_TRACE_VECTOR:
79        vector_offset = ASM_PPC405_TRACE_VECTOR_OFFSET;
80        break;
81      case ASM_PPC405_APU_UNAVAIL_VECTOR:
82        vector_offset = ASM_60X_VEC_VECTOR_OFFSET;
83      default:
84        break;
85    }
86  }
87
88  if (
89    ppc_cpu_is_bookE() == PPC_BOOKE_STD
90      || ppc_cpu_is_bookE() == PPC_BOOKE_E500
91  ) {
92    if (vector < sizeof(ivor_values) / sizeof(ivor_values [0])) {
93      vector_offset = ((uintptr_t) ivor_values [vector]) << 4;
94    } else {
95      vector_offset = 0;
96    }
97  }
98
99  return (void *) ((uintptr_t) vector_base + vector_offset);
100}
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