source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S @ c499856

4.115
Last change on this file since c499856 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*
2 *  asm_utils.s
3 *
4 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
5 *
6 *  This file contains the low-level support for moving exception
7 *  exception code to appropriate location.
8 *
9 */
10
11#include <rtems/asm.h>
12#include <rtems/score/cpu.h>
13
14        .globl  codemove
15codemove:
16        .type   codemove,@function
17/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
18        cmplw   cr1,r3,r4
19        addi    r0,r5,3
20        srwi.   r0,r0,2
21        beq     cr1,4f  /* In place copy is not necessary */
22        beq     7f      /* Protect against 0 count */
23        mtctr   r0
24        bge     cr1,2f
25
26        la      r8,-4(r4)
27        la      r7,-4(r3)
281:      lwzu    r0,4(r8)
29        stwu    r0,4(r7)
30        bdnz    1b
31        b       4f
32
332:      slwi    r0,r0,2
34        add     r8,r4,r0
35        add     r7,r3,r0
363:      lwzu    r0,-4(r8)
37        stwu    r0,-4(r7)
38        bdnz    3b
39
40/* Now flush the cache: note that we must start from a cache aligned
41 * address. Otherwise we might miss one cache line.
42 */
434:      cmpwi   r6,0
44        add     r5,r3,r5
45        beq     7f      /* Always flush prefetch queue in any case */
46        subi    r0,r6,1
47        andc    r3,r3,r0
48        mr      r4,r3
495:      cmplw   r4,r5
50        dcbst   0,r4
51        add     r4,r4,r6
52        blt     5b
53        sync            /* Wait for all dcbst to complete on bus */
54        mr      r4,r3
556:      cmplw   r4,r5
56        icbi    0,r4
57        add     r4,r4,r6
58        blt     6b
597:      sync            /* Wait for all icbi to complete on bus */
60        isync
61        blr
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