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vectors.S @ 41ab6966

4.104.114.84.95

Last change on this file since 41ab6966 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 19:57:02

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

Property mode set to 100644

File size: 23.8 KB

Line
1	/* vectors.S 1.1 - 95/12/04
2	*
3	* This file contains the assembly code for the PowerPC MPC8xx
4	* interrupt veneers for RTEMS.
5	*
6	* Author: Jay Monkman (jmonkman@frasca.com)
7	*
8	* Copyright (C) 1998 by Frasca International, Inc.
9	*
10	* Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s:
11	*
12	* Author: Andrew Bray <andy@i-cubed.co.uk>
13	*
14	* COPYRIGHT (c) 1995 by i-cubed ltd.
15	*
16	* To anyone who acknowledges that this file is provided "AS IS"
17	* without any express or implied warranty:
18	* permission to use, copy, modify, and distribute this file
19	* for any purpose is hereby granted without fee, provided that
20	* the above copyright notice and this notice appears in all
21	* copies, and that the name of i-cubed limited not be used in
22	* advertising or publicity pertaining to distribution of the
23	* software without specific, written prior permission.
24	* i-cubed limited makes no representations about the suitability
25	* of this software for any purpose.
26	*
27	* Dwarf debugging info added by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
28	* Also, made changes to turn address translation back on.
29	*
30	* Modifications for to add DWARF debugging info, turn address translation on
31	* and to coexist with EPPCBug:
32	* Copyright (c) 1999, National Research Council of Canada
33	*
34	*/
35
36	/*
37	* The issue with this file is getting it loaded at the right place.
38	* The first vector MUST be at address 0x????0100.
39	* How this is achieved is dependant on the tool chain.
40	*
41	* However the basic mechanism for ELF assemblers is to create a
42	* section called ".vectors", which will be loaded to an address
43	* between 0x????0000 and 0x????0100 (inclusive) via a link script.
44	*
45	* The basic mechanism for XCOFF assemblers is to place it in the
46	* normal text section, and arrange for this file to be located
47	* at an appropriate position on the linker command line.
48	*
49	* The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
50	* offset from 0x????0000 to the first location in the file. This
51	* will be either 0x0000 or 0xfff0.
52	*
53	* If EPPCBUG_VECTORS is #defined, vectors 0x100 (system reset),
54	* 0x700 (program), 0xC00 (system call) and 0xD00 (trace) are set
55	* up identically to the EPPCBug vectors in order to preserve the
56	* firmware runtime environment.
57	*
58	* THE FOUR ABOVE VECTORS MAY NEED TO BE MODIFIED TO MATCH YOUR
59	* REVISION OF THE FIRMWARE.
60	*
61	* Coexisting with the firmware only makes sense when the
62	* PPC_VECTOR_FILE_BASE is 0.
63	*
64	* $Id$
65	*/
66
67	#include "asm.h"
68	#include <mpc8xx.h>
69
70	/* Location of your rtems source tree for source-level debugging purposes */
71	#define PATH_PREFIX "/home/stewart"
72
73	#ifndef PPC_VECTOR_FILE_BASE
74	#error "PPC_VECTOR_FILE_BASE is not defined."
75	#endif
76
77	/* Where this file will be loaded */
78	.set file_base, PPC_VECTOR_FILE_BASE
79
80	/* Offset to store reg 0 */
81
82	.set IP_LINK, 0
83	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
84	.set IP_0, (IP_LINK + 56)
85	#else
86	.set IP_0, (IP_LINK + 8)
87	#endif
88	.set IP_2, (IP_0 + 4)
89
90	.set IP_3, (IP_2 + 4)
91	.set IP_4, (IP_3 + 4)
92	.set IP_5, (IP_4 + 4)
93	.set IP_6, (IP_5 + 4)
94
95	.set IP_7, (IP_6 + 4)
96	.set IP_8, (IP_7 + 4)
97	.set IP_9, (IP_8 + 4)
98	.set IP_10, (IP_9 + 4)
99
100	.set IP_11, (IP_10 + 4)
101	.set IP_12, (IP_11 + 4)
102	.set IP_13, (IP_12 + 4)
103	.set IP_28, (IP_13 + 4)
104
105	.set IP_29, (IP_28 + 4)
106	.set IP_30, (IP_29 + 4)
107	.set IP_31, (IP_30 + 4)
108	.set IP_CR, (IP_31 + 4)
109
110	.set IP_CTR, (IP_CR + 4)
111	.set IP_XER, (IP_CTR + 4)
112	.set IP_LR, (IP_XER + 4)
113	.set IP_PC, (IP_LR + 4)
114
115	.set IP_MSR, (IP_PC + 4)
116
117	.set IP_END, (IP_MSR + 16)
118
119	/* Vector offsets */
120	.set begin_vector, 0x0000
121	.set reset_vector, 0x0100
122	.set mach_vector, 0x0200
123	.set dsi_vector, 0x0300
124	.set isi_vector, 0x0400
125	.set ext_vector, 0x0500
126	.set align_vector, 0x0600
127	.set prog_vector, 0x0700
128	.set float_vector, 0x0800
129	.set dec_vector, 0x0900
130	.set sys_vector, 0x0C00
131	.set trace_vector, 0x0d00
132	.set syscall_vector, 0x0c00
133	.set fpassist_vector, 0x0e00
134	.set software_vector, 0x1000
135	.set itlbm_vector, 0x1100
136	.set dtlbm_vector, 0x1200
137	.set itlbe_vector, 0x1300
138	.set dtlbe_vector, 0x1400
139	.set databkpt_vector, 0x1c00
140	.set insbkpt_vector, 0x1d00
141	.set perbkpt_vector, 0x1e00
142	.set dev_vector, 0x1f00
143	.set siu_vector, 0x2000
144	.set cpm_vector, 0x2400
145
146	/* Go to the right section */
147	#if PPC_ASM == PPC_ASM_XCOFF
148	.csect .text[PR]
149	#elif PPC_ASM == PPC_ASM_ELF
150	.section .vectors,"awx",@progbits
151	.L_text_b:
152	.L_LC1:
153	.previous
154
155	.section .debug_sfnames
156	.L_sfnames_b:
157	.byte PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
158	.byte 0
159	.L_F0:
160	.byte "vectors.S"
161	.byte 0
162	.previous
163
164	.section .line
165	.L_line_b:
166	.4byte .L_line_e-.L_line_b
167	.4byte .L_text_b
168	.L_LE1:
169	.L_line_last:
170	.4byte 0x0
171	.2byte 0xffff
172	.4byte .L_text_e-.L_text_b
173	.L_line_e:
174	.previous
175
176	.section .debug_srcinfo
177	.L_srcinfo_b:
178	.4byte .L_line_b
179	.4byte .L_sfnames_b
180	.4byte .L_text_b
181	.4byte .L_text_e
182	.4byte 0xffffffff
183	.4byte .L_LE1-.L_line_b
184	.4byte .L_F0-.L_sfnames_b
185	.4byte .L_line_last-.L_line_b
186	.4byte 0xffffffff
187	.previous
188
189	.section .debug_pubnames
190	.4byte .L_debug_b
191	.4byte .L_P0
192	.byte "__vectors"
193	.byte 0
194	.4byte 0x0
195	.byte 0
196	.previous
197
198	.section .debug_aranges
199	.4byte .L_debug_b
200	.4byte .L_text_b
201	.4byte .L_text_e-.L_text_b
202	.4byte 0
203	.4byte 0
204	.4byte 0
205	.4byte 0
206	.4byte 0
207	.4byte 0
208	.4byte 0x0
209	.4byte 0x0
210	.previous
211
212	.section .debug
213	.L_debug_b:
214	.L_D1:
215	.4byte .L_D1_e-.L_D1
216	.2byte 0x11 /* TAG_compile_unit */
217	.2byte 0x12 /* AT_sibling */
218	.4byte .L_D2
219	.2byte 0x38 /* AT_name */
220	.byte "vectors.S"
221	.byte 0
222	.2byte 0x258 /* AT_producer */
223	.byte "GAS 2.5.2"
224	.byte 0
225	.2byte 0x111 /* AT_low_pc */
226	.4byte .L_text_b
227	.2byte 0x121 /* AT_high_pc */
228	.4byte .L_text_e
229	.2byte 0x106 /* AT_stmt_list */
230	.4byte .L_line_b
231	.2byte 0x1b8 /* AT_comp_dir */
232	.byte PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
233	.byte 0
234	.2byte 0x8006 /* AT_sf_names */
235	.4byte .L_sfnames_b
236	.2byte 0x8016 /* AT_src_info */
237	.4byte .L_srcinfo_b
238	.L_D1_e:
239	.L_P0:
240	.L_D3:
241	.4byte .L_D3_e-.L_D3
242	.2byte 0x6 /* TAG_global_subroutine */
243	.2byte 0x12 /* AT_sibling */
244	.4byte .L_D4
245	.2byte 0x38 /* AT_name */
246	.byte "__vectors"
247	.byte 0
248	.2byte 0x278 /* AT_prototyped */
249	.byte 0
250	.2byte 0x111 /* AT_low_pc */
251	.4byte .L_text_b
252	.2byte 0x121 /* AT_high_pc */
253	.4byte .L_text_e
254	.2byte 0x8041 /* AT_body_begin */
255	.4byte .L_text_b
256	.2byte 0x8051 /* AT_body_end */
257	.4byte .L_text_e
258	.L_D3_e:
259
260	.L_D4:
261	.4byte .L_D4_e-.L_D4
262	.align 2
263	.L_D4_e:
264	.L_D2:
265	.previous
266
267	.section .vectors
268	#endif /* PPC_ASM_ELF */
269
270	PUBLIC_VAR (__vectors)
271	SYM (__vectors):
272
273
274	/* 0x100 -- Critical error handling */
275	.org reset_vector - file_base
276	base_vectors:
277
278	#ifdef EPPCBUG_VECTORS
279	mtsprg 0, r1
280	mflr r1
281	mtsprg 1, r1
282	bl 0xFE003EF8 /* 0xFE004004 */
283	#else
284	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
285	#if (PPC_HAS_FPU)
286	stwu r1, -(204 + 188 + IP_END)(r1)
287	#else
288	stwu r1, -(20*4 + IP_END)(r1)
289	#endif /* PPC_HAS_FPU */
290	#else
291	stwu r1, -(IP_END)(r1)
292	#endif /* PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27 */
293	stw r0, IP_0(r1)
294
295	/* Turn address translation back on to re-enable the caches. */
296	mfmsr r0
297	ori r0, r0, 0x30
298	mtmsr r0
299
300	li r0, PPC_IRQ_SYSTEM_RESET
301	b PROC (_ISR_Handler)
302	#endif /* EPPCBUG_VECTORS */
303
304
305	/* 0x200 -- Machine check exception */
306	.org mach_vector - file_base
307	#ifdef EPPCBUG_VECTORS
308	mtsprg 0, r1
309	mflr r1
310	mtsprg 1, r1
311	bl 0xFE003DF8 /* 0xFE004004 */
312	#else
313	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
314	#if (PPC_HAS_FPU)
315	stwu r1, -(204 + 188 + IP_END)(r1)
316	#else
317	stwu r1, -(20*4 + IP_END)(r1)
318	#endif
319	#else
320	stwu r1, -(IP_END)(r1)
321	#endif
322	stw r0, IP_0(r1)
323
324	/* Turn address translation back on to re-enable the caches. */
325	mfmsr r0
326	ori r0, r0, 0x30
327	mtmsr r0
328
329	li r0, PPC_IRQ_MCHECK
330	b PROC (_ISR_Handler)
331	#endif /* EPPCBUG_VECTORS */
332
333
334	/* 0x300 -- Protection exception */
335	.org dsi_vector - file_base
336	#ifdef EPPCBUG_VECTORS
337	mtsprg 0, r1
338	mflr r1
339	mtsprg 1, r1
340	bl 0xFE003CF8 /* 0xFE004004 */
341	#else
342	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
343	#if (PPC_HAS_FPU)
344	stwu r1, -(204 + 188 + IP_END)(r1)
345	#else
346	stwu r1, -(20*4 + IP_END)(r1)
347	#endif
348	#else
349	stwu r1, -(IP_END)(r1)
350	#endif
351	stw r0, IP_0(r1)
352
353	/* Turn address translation back on to re-enable the caches. */
354	mfmsr r0
355	ori r0, r0, 0x30
356	mtmsr r0
357
358	li r0, PPC_IRQ_PROTECT
359	b PROC (_ISR_Handler)
360	#endif /* EPPCBUG_VECTORS */
361
362
363	/* 0x400 -- Instruction Storage exception */
364	.org isi_vector - file_base
365	#ifdef EPPCBUG_VECTORS
366	mtsprg 0, r1
367	mflr r1
368	mtsprg 1, r1
369	bl 0xFE003BF8 /* 0xFE004004 */
370	#else
371	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
372	#if (PPC_HAS_FPU)
373	stwu r1, -(204 + 188 + IP_END)(r1)
374	#else
375	stwu r1, -(20*4 + IP_END)(r1)
376	#endif
377	#else
378	stwu r1, -(IP_END)(r1)
379	#endif
380	stw r0, IP_0(r1)
381
382	/* Turn address translation back on to re-enable the caches. */
383	mfmsr r0
384	ori r0, r0, 0x30
385	mtmsr r0
386
387	li r0, PPC_IRQ_ISI
388	b PROC (_ISR_Handler)
389	#endif /* EPPCBUG_VECTORS */
390
391
392	/* 0x500 -- External interrupt */
393	/* When an external interrupt occurs, we must find out what caused it */
394	/* before calling the RTEMS handler. First we use SIVEC to decide */
395	/* what signalled the interrupt to the SIU. */
396	.org ext_vector - file_base
397	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
398	#if (PPC_HAS_FPU)
399	stwu r1, -(204 + 188 + IP_END)(r1)
400	#else
401	stwu r1, -(20*4 + IP_END)(r1)
402	#endif
403	#else
404	stwu r1, -(IP_END)(r1)
405	#endif
406	stw r0, IP_0(r1)
407
408	/* Turn address translation back on to re-enable the caches. */
409	mfmsr r0
410	ori r0, r0, 0x30
411	mtmsr r0
412
413	stw r9, IP_9(r1) /* r9 will be restored in the next level */
414	stw r10, IP_10(r1)
415
416	lis r9, m8xx@ha
417	addi r9, r9, m8xx@l
418	lbz r10, 0x1c(r9) /* SIVEC */
419	rlwinm r10, r10, 4, 0, 27 /* each psuedo vector will have */
420	/* room for 16 instructions */
421	addis r10, r10, siu_vectors@ha
422	addi r10, r10, siu_vectors@l
423	mflr r0
424	mtlr r10
425	lwz r10, IP_10(r1)
426	blr
427
428
429	/* 0x600 -- Align exception */
430	.org align_vector - file_base
431	.extern align_h
432	b align_h
433
434
435	/* 0x700 -- Program exception */
436	.org prog_vector - file_base
437	#ifdef EPPCBUG_VECTORS
438	mtsprg 0, r1
439	mflr r1
440	mtsprg 1, r1
441	bl 0xFE0038F8 /* 0xFE004004 */
442	#else
443	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
444	#if (PPC_HAS_FPU)
445	stwu r1, -(204 + 188 + IP_END)(r1)
446	#else
447	stwu r1, -(20*4 + IP_END)(r1)
448	#endif
449	#else
450	stwu r1, -(IP_END)(r1)
451	#endif
452	stw r0, IP_0(r1)
453
454	/* Turn address translation back on to re-enable the caches. */
455	mfmsr r0
456	ori r0, r0, 0x30
457	mtmsr r0
458
459	li r0, PPC_IRQ_PROGRAM
460	b PROC (_ISR_Handler)
461	#endif /* EPPCBUG_VECTORS */
462
463
464	/* 0x800 -- Float exception */
465	.org float_vector - file_base
466	#ifdef EPPCBUG_VECTORS
467	mtsprg 0, r1
468	mflr r1
469	mtsprg 1, r1
470	bl 0xFE0037F8 /* 0xFE004004 */
471	#else
472	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
473	#if (PPC_HAS_FPU)
474	stwu r1, -(204 + 188 + IP_END)(r1)
475	#else
476	stwu r1, -(20*4 + IP_END)(r1)
477	#endif
478	#else
479	stwu r1, -(IP_END)(r1)
480	#endif
481	stw r0, IP_0(r1)
482
483	/* Turn address translation back on to re-enable the caches. */
484	mfmsr r0
485	ori r0, r0, 0x30
486	mtmsr r0
487
488	li r0, PPC_IRQ_NOFP
489	b PROC (_ISR_Handler)
490	#endif /* EPPCBUG_VECTORS */
491
492
493	/* 0x900 -- Decrementer exception */
494	.org dec_vector - file_base
495	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
496	#if (PPC_HAS_FPU)
497	stwu r1, -(204 + 188 + IP_END)(r1)
498	#else
499	stwu r1, -(20*4 + IP_END)(r1)
500	#endif
501	#else
502	stwu r1, -(IP_END)(r1)
503	#endif
504	stw r0, IP_0(r1)
505
506	/* Turn address translation back on to re-enable the caches. */
507	mfmsr r0
508	ori r0, r0, 0x30
509	mtmsr r0
510
511	li r0, PPC_IRQ_DECREMENTER
512	b PROC (_ISR_Handler)
513
514
515	/* 0xC00 -- System call */
516	.org sys_vector - file_base
517	#ifdef EPPCBUG_VECTORS
518	mtsprg 0, r1
519	mflr r1
520	mtsprg 1, r1
521	bl 0xFE0033F8 /* 0xFE004004 */
522	#else
523	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
524	#if (PPC_HAS_FPU)
525	stwu r1, -(204 + 188 + IP_END)(r1)
526	#else
527	stwu r1, -(20*4 + IP_END)(r1)
528	#endif
529	#else
530	stwu r1, -(IP_END)(r1)
531	#endif
532	stw r0, IP_0(r1)
533
534	/* Turn address translation back on to re-enable the caches. */
535	mfmsr r0
536	ori r0, r0, 0x30
537	mtmsr r0
538
539	li r0, PPC_IRQ_SCALL
540	b PROC (_ISR_Handler)
541	#endif /* EPPCBUG_VECTORS */
542
543
544	/* 0xD00 -- Trace interrupt */
545	.org trace_vector - file_base
546	#ifdef EPPCBUG_VECTORS
547	mtsprg 0, r1
548	mflr r1
549	mtsprg 1, r1
550	bl 0xFE0032F8 /* 0xFE004004 */
551	#else
552	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
553	#if (PPC_HAS_FPU)
554	stwu r1, -(204 + 188 + IP_END)(r1)
555	#else
556	stwu r1, -(20*4 + IP_END)(r1)
557	#endif
558	#else
559	stwu r1, -(IP_END)(r1)
560	#endif
561	stw r0, IP_0(r1)
562
563	/* Turn address translation back on to re-enable the caches. */
564	mfmsr r0
565	ori r0, r0, 0x30
566	mtmsr r0
567
568	li r0, PPC_IRQ_TRACE
569	b PROC (_ISR_Handler)
570	#endif /* EPPCBUG_VECTORS */
571
572
573	#ifdef EPPCBUG_VECTORS
574	/* 0xE00 -- Floating Point Assist */
575	.org fpassist_vector - file_base
576	mtsprg 0, r1
577	mflr r1
578	mtsprg 1, r1
579	bl 0xFE0031F8 /* 0xFE004004 */
580
581	/* 0x1000 -- Software Emulation */
582	.org software_vector - file_base
583	software_vectors:
584	mtsprg 0, r1
585	mflr r1
586	mtsprg 1, r1
587	bl 0xFE002FF8 /* 0xFE004004 */
588	#endif
589
590
591	/* 0x1100 -- Intruction TLB Miss */
592	.org itlbm_vector - file_base
593	itlbm_vectors:
594	#ifdef EPPCBUG_VECTORS
595	mtsprg 0, r1
596	mflr r1
597	mtsprg 1, r1
598	bl 0xFE002EF8 /* 0xFE004004 */
599	#else
600	mfspr r2, 784 /* MI_CTR */
601	mfspr r3, 792 /* MD_CTR */
602	mfspr r4, 787 /* MI_EPN */
603	mfspr r5, 789 /* MI_TWC */
604	mfspr r6, 797 /* MD_TWC */
605	mfspr r7, 789 /* MI_TWC */
606	mfspr r8, 790 /* MI_RPN */
607	mfspr r9, 798 /* MD_RPN */
608	mfspr r10, 796 /* M_TWB */
609	mfspr r11, 793 /* M_CASID */
610	mfspr r12, 786 /* MI_AP */
611	mfspr r13, 794 /* MD_AP */
612	mfspr r14, 799 /* M_TW */
613	mfspr r15, 816 /* MI_CAM */
614	mfspr r16, 817 /* MI_RAM0 */
615	mfspr r17, 818 /* MI_RAM1 */
616	mfspr r18, 824 /* MD_CAM */
617	mfspr r19, 825 /* M_RAM0 */
618	mfspr r20, 826 /* M_RAM1 */
619	.long 0
620	#endif /* EPPCBUG_VECTORS */
621
622
623	/* 0x1200 -- Data TLB Miss */
624	.org dtlbm_vector - file_base
625	dtlbm_vectors:
626	#ifdef EPPCBUG_VECTORS
627	mtsprg 0, r1
628	mflr r1
629	mtsprg 1, r1
630	bl 0xFE002DF8 /* 0xFE004004 */
631	#else
632	mfspr r1, 0x1a
633	mfspr r2, 784 /* MI_CTR */
634	mfspr r3, 792 /* MD_CTR */
635	lis r3, 0x400
636	mtspr 792, r3
637	mfspr r4, 787 /* MI_EPN */
638	mfspr r5, 789 /* MI_TWC */
639	mfspr r6, 797 /* MD_TWC */
640	mfspr r7, 789 /* MI_TWC */
641	mfspr r8, 790 /* MI_RPN */
642	mfspr r9, 798 /* MD_RPN */
643	mfspr r10, 796 /* M_TWB */
644	mfspr r11, 793 /* M_CASID */
645	mfspr r12, 786 /* MI_AP */
646	mfspr r13, 794 /* MD_AP */
647	mfspr r14, 799 /* M_TW */
648	mfspr r15, 816 /* MI_CAM */
649	mfspr r16, 817 /* MI_RAM0 */
650	mfspr r17, 818 /* MI_RAM1 */
651	mtspr 824, r18
652	mfspr r18, 824 /* MD_CAM */
653	mfspr r19, 825 /* M_RAM0 */
654	mfspr r20, 826 /* M_RAM1 */
655	.long 0
656	#endif /* EPPCBUG_VECTORS */
657
658
659	/* 0x1300 -- Instruction TLB Error */
660	.org itlbe_vector - file_base
661	itlbe_vectors:
662	#ifdef EPPCBUG_VECTORS
663	mtsprg 0, r1
664	mflr r1
665	mtsprg 1, r1
666	bl 0xFE002CF8 /* 0xFE004004 */
667	#else
668	mfspr r2, 784 /* MI_CTR */
669	mfspr r3, 792 /* MD_CTR */
670	mfspr r4, 787 /* MI_EPN */
671	mfspr r5, 789 /* MI_TWC */
672	mfspr r6, 797 /* MD_TWC */
673	mfspr r7, 789 /* MI_TWC */
674	mfspr r8, 790 /* MI_RPN */
675	mfspr r9, 798 /* MD_RPN */
676	mfspr r10, 796 /* M_TWB */
677	mfspr r11, 793 /* M_CASID */
678	mfspr r12, 786 /* MI_AP */
679	mfspr r13, 794 /* MD_AP */
680	mfspr r14, 799 /* M_TW */
681	mfspr r15, 816 /* MI_CAM */
682	mfspr r16, 817 /* MI_RAM0 */
683	mfspr r17, 818 /* MI_RAM1 */
684	mfspr r18, 824 /* MD_CAM */
685	mfspr r19, 825 /* M_RAM0 */
686	mfspr r20, 826 /* M_RAM1 */
687	.long 0
688	#endif /* EPPCBUG_VECTORS */
689
690
691	/* 0x1400 -- Data TLB Error */
692	.org dtlbe_vector - file_base
693	dtlbe_vectors:
694	#ifdef EPPCBUG_VECTORS
695	mtsprg 0, r1
696	mflr r1
697	mtsprg 1, r1
698	bl 0xFE002BF8 /* 0xFE004004 */
699	#else
700	mfspr r2, 784 /* MI_CTR */
701	mfspr r3, 792 /* MD_CTR */
702	mfspr r4, 787 /* MI_EPN */
703	mfspr r5, 789 /* MI_TWC */
704	mfspr r6, 797 /* MD_TWC */
705	mfspr r7, 789 /* MI_TWC */
706	mfspr r8, 790 /* MI_RPN */
707	mfspr r9, 798 /* MD_RPN */
708	mfspr r10, 796 /* M_TWB */
709	mfspr r11, 793 /* M_CASID */
710	mfspr r12, 786 /* MI_AP */
711	mfspr r13, 794 /* MD_AP */
712	mfspr r14, 799 /* M_TW */
713	mfspr r15, 816 /* MI_CAM */
714	mfspr r16, 817 /* MI_RAM0 */
715	mfspr r17, 818 /* MI_RAM1 */
716	mfspr r18, 824 /* MD_CAM */
717	mfspr r19, 825 /* M_RAM0 */
718	mfspr r20, 826 /* M_RAM1 */
719	.long 0
720	#endif /* EPPCBUG_VECTORS */
721
722
723	#ifdef EPPCBUG_VECTORS
724	/* 0x1C00 -- Data Breakpoint */
725	.org databkpt_vector - file_base
726	databkpt_vectors:
727	mtsprg 0, r1
728	mflr r1
729	mtsprg 1, r1
730	bl 0xFE0023F8 /* 0xFE004004 */
731
732	/* 0x1D00 -- Instruction Breakpoint */
733	.org insbkpt_vector - file_base
734	insbkpt_vectors:
735	mtsprg 0, r1
736	mflr r1
737	mtsprg 1, r1
738	bl 0xFE0022F8 /* 0xFE004004 */
739
740	/* 0x1E00 -- Peripheral Breakpoint */
741	.org perbkpt_vector - file_base
742	perbkpt_vectors:
743	mtsprg 0, r1
744	mflr r1
745	mtsprg 1, r1
746	bl 0xFE0021F8 /* 0xFE004004 */
747
748	/* 0x1F00 -- Non-Makable Development Port */
749	.org dev_vector - file_base
750	dev_vectors:
751	mtsprg 0, r1
752	mflr r1
753	mtsprg 1, r1
754	bl 0xFE0020F8 /* 0xFE004004 */
755	#endif
756
757
758
759	/* Now we look at what signaled the interrupt to the SIU. */
760	/* I needed to do this in order to decode the CPM interrupts before */
761	/* calling _ISR_Handler */
762
763	/* IRQ0 /
764	.org siu_vector - file_base
765	siu_vectors:
766	mtlr r0
767	lwz r9, IP_9(r1)
768	li r0, PPC_IRQ_IRQ0
769	b PROC (_ISR_Handler)
770
771	nop
772	nop
773	nop
774	nop
775	nop
776	nop
777	nop
778	nop
779	nop
780	nop
781	nop
782	nop
783
784	/* Level 0 */
785	mtlr r0
786	lwz r9, IP_9(r1)
787	li r0, PPC_IRQ_LVL0
788	b PROC (_ISR_Handler)
789
790	nop
791	nop
792	nop
793	nop
794	nop
795	nop
796	nop
797	nop
798	nop
799	nop
800	nop
801	nop
802
803	/* IRQ1 /
804	mtlr r0
805	lwz r9, IP_9(r1)
806	li r0, PPC_IRQ_IRQ1
807	b PROC (_ISR_Handler)
808
809	nop
810	nop
811	nop
812	nop
813	nop
814	nop
815	nop
816	nop
817	nop
818	nop
819	nop
820	nop
821
822	/* This is probably not the "correct" way to do this. I need to have a
823	* way of calling _ISR_Handler for the CPM interrupts and this is the
824	* simplest way I can think of. Since I have the CPM interrupt mapped
825	* to the SIU interrupt level 1 on the eth-comm board, I put it here.
826	* It would probably be ok if I moved this directory to under libbsp
827	* instead of libcpu. For now, deal with it.
828	*/
829	/* Level 1 - CPM */
830	/* Now we need to get the CPM interrupt vector */
831	/* Registers: */
832	/* R0 - has stored value of LR */
833	/* R9 - pointer to m8xx struct */
834	/* R10 has already been saved and restored */
835	li r10, 1
836	sth r10, 0x930(r9) /* CIVR */
837	lbz r10, 0x930(r9) /* if we use this as an offset into a */
838	rlwinm r10, r10, 1, 0, 31 /* table, each entry will have room */
839	/* 4 instructions. */
840	addis r10, r10, cpm_vectors@ha
841	addi r10, r10, cpm_vectors@l
842
843	mtlr r10
844	lwz r10, IP_10(r1)
845	blr
846
847	nop
848	nop
849	nop
850	nop
851	nop
852	nop
853	nop
854
855	#if 0
856	/* Level 1 */
857	mtlr r0
858	lwz r9, IP_9(r1)
859	li r0, PPC_IRQ_LVL1
860	b PROC (_ISR_Handler)
861
862	nop
863	nop
864	nop
865	nop
866	nop
867	nop
868	nop
869	nop
870	nop
871	nop
872	nop
873	nop
874	#endif
875
876	/* IRQ2 /
877	mtlr r0
878	lwz r9, IP_9(r1)
879	li r0, PPC_IRQ_IRQ2
880	b PROC (_ISR_Handler)
881
882	nop
883	nop
884	nop
885	nop
886	nop
887	nop
888	nop
889	nop
890	nop
891	nop
892	nop
893	nop
894
895	/* Level 2 */
896	mtlr r0
897	lwz r9, IP_9(r1)
898	li r0, PPC_IRQ_LVL2
899	b PROC (_ISR_Handler)
900
901	nop
902	nop
903	nop
904	nop
905	nop
906	nop
907	nop
908	nop
909	nop
910	nop
911	nop
912	nop
913
914	/* IRQ3 /
915	mtlr r0
916	lwz r9, IP_9(r1)
917	li r0, PPC_IRQ_IRQ3
918	b PROC (_ISR_Handler)
919
920	nop
921	nop
922	nop
923	nop
924	nop
925	nop
926	nop
927	nop
928	nop
929	nop
930	nop
931	nop
932
933	/* Level 3 */
934	mtlr r0
935	lwz r9, IP_9(r1)
936	li r0, PPC_IRQ_LVL3
937	b PROC (_ISR_Handler)
938
939	nop
940	nop
941	nop
942	nop
943	nop
944	nop
945	nop
946	nop
947	nop
948	nop
949	nop
950	nop
951
952	/* IRQ4 /
953	mtlr r0
954	lwz r9, IP_9(r1)
955	li r0, PPC_IRQ_IRQ4
956	b PROC (_ISR_Handler)
957
958	nop
959	nop
960	nop
961	nop
962	nop
963	nop
964	nop
965	nop
966	nop
967	nop
968	nop
969	nop
970
971	/* Level 4 */
972	mtlr r0
973	lwz r9, IP_9(r1)
974	li r0, PPC_IRQ_LVL4
975	b PROC (_ISR_Handler)
976
977	nop
978	nop
979	nop
980	nop
981	nop
982	nop
983	nop
984	nop
985	nop
986	nop
987	nop
988	nop
989
990	/* IRQ5 /
991	mtlr r0
992	lwz r9, IP_9(r1)
993	li r0, PPC_IRQ_IRQ5
994	b PROC (_ISR_Handler)
995
996	nop
997	nop
998	nop
999	nop
1000	nop
1001	nop
1002	nop
1003	nop
1004	nop
1005	nop
1006	nop
1007	nop
1008
1009	/* Level 5 */
1010	mtlr r0
1011	lwz r9, IP_9(r1)
1012	li r0, PPC_IRQ_LVL5
1013	b PROC (_ISR_Handler)
1014
1015	nop
1016	nop
1017	nop
1018	nop
1019	nop
1020	nop
1021	nop
1022	nop
1023	nop
1024	nop
1025	nop
1026	nop
1027
1028	/* IRQ6 /
1029	mtlr r0
1030	lwz r9, IP_9(r1)
1031	li r0, PPC_IRQ_IRQ6
1032	b PROC (_ISR_Handler)
1033
1034	nop
1035	nop
1036	nop
1037	nop
1038	nop
1039	nop
1040	nop
1041	nop
1042	nop
1043	nop
1044	nop
1045	nop
1046
1047	/* Level 6 */
1048	mtlr r0
1049	lwz r9, IP_9(r1)
1050	li r0, PPC_IRQ_LVL6
1051	b PROC (_ISR_Handler)
1052
1053	nop
1054	nop
1055	nop
1056	nop
1057	nop
1058	nop
1059	nop
1060	nop
1061	nop
1062	nop
1063	nop
1064	nop
1065
1066	/* IRQ7 /
1067	mtlr r0
1068	lwz r9, IP_9(r1)
1069	li r0, PPC_IRQ_IRQ7
1070	b PROC (_ISR_Handler)
1071
1072	nop
1073	nop
1074	nop
1075	nop
1076	nop
1077	nop
1078	nop
1079	nop
1080	nop
1081	nop
1082	nop
1083	nop
1084
1085	/* Level 7 */
1086	mtlr r0
1087	lwz r9, IP_9(r1)
1088	li r0, PPC_IRQ_LVL7
1089	b PROC (_ISR_Handler)
1090
1091	nop
1092	nop
1093	nop
1094	nop
1095	nop
1096	nop
1097	nop
1098	nop
1099	nop
1100	nop
1101	nop
1102	nop
1103
1104
1105	/* .org cpm_vector - file_base*/
1106	cpm_vectors:
1107	mtlr r0
1108	lwz r9, IP_9(r1)
1109	li r0, PPC_IRQ_CPM_ERROR
1110	b PROC (_ISR_Handler)
1111
1112	/* PC4 */
1113	mtlr r0
1114	lwz r9, IP_9(r1)
1115	li r0, PPC_IRQ_CPM_PC4
1116	b PROC (_ISR_Handler)
1117
1118	/* PC5 */
1119	mtlr r0
1120	lwz r9, IP_9(r1)
1121	li r0, PPC_IRQ_CPM_PC5
1122	b PROC (_ISR_Handler)
1123
1124	/* SMC2 / PIP */
1125	mtlr r0
1126	lwz r9, IP_9(r1)
1127	li r0, PPC_IRQ_CPM_SMC2
1128	b PROC (_ISR_Handler)
1129
1130	/* SMC1 */
1131	mtlr r0
1132	lwz r9, IP_9(r1)
1133	li r0, PPC_IRQ_CPM_SMC1
1134	b PROC (_ISR_Handler)
1135
1136	/* SPI */
1137	mtlr r0
1138	lwz r9, IP_9(r1)
1139	li r0, PPC_IRQ_CPM_SPI
1140	b PROC (_ISR_Handler)
1141
1142	/* PC6 */
1143	mtlr r0
1144	lwz r9, IP_9(r1)
1145	li r0, PPC_IRQ_CPM_PC6
1146	b PROC (_ISR_Handler)
1147
1148	/* Timer 4 */
1149	mtlr r0
1150	lwz r9, IP_9(r1)
1151	li r0, PPC_IRQ_CPM_TIMER4
1152	b PROC (_ISR_Handler)
1153
1154	/* Reserved - we should never see this */
1155	mtlr r0
1156	lwz r9, IP_9(r1)
1157	li r0, PPC_IRQ_CPM_RESERVED_8
1158	.long 0
1159
1160	/* PC7 */
1161	mtlr r0
1162	lwz r9, IP_9(r1)
1163	li r0, PPC_IRQ_CPM_PC7
1164	b PROC (_ISR_Handler)
1165
1166	/* PC8 */
1167	mtlr r0
1168	lwz r9, IP_9(r1)
1169	li r0, PPC_IRQ_CPM_PC8
1170	b PROC (_ISR_Handler)
1171
1172	/* PC9 */
1173	mtlr r0
1174	lwz r9, IP_9(r1)
1175	li r0, PPC_IRQ_CPM_PC9
1176	b PROC (_ISR_Handler)
1177
1178	/* Timer 3 */
1179	mtlr r0
1180	lwz r9, IP_9(r1)
1181	li r0, PPC_IRQ_CPM_TIMER3
1182	b PROC (_ISR_Handler)
1183
1184	/* Reserved - we should never get here */
1185	mtlr r0
1186	lwz r9, IP_9(r1)
1187	li r0, PPC_IRQ_CPM_RESERVED_D
1188	.long 0
1189
1190	/* PC10 */
1191	mtlr r0
1192	lwz r9, IP_9(r1)
1193	li r0, PPC_IRQ_CPM_PC10
1194	b PROC (_ISR_Handler)
1195
1196	/* PC11 */
1197	mtlr r0
1198	lwz r9, IP_9(r1)
1199	li r0, PPC_IRQ_CPM_PC11
1200	b PROC (_ISR_Handler)
1201
1202	/* I2C */
1203	mtlr r0
1204	lwz r9, IP_9(r1)
1205	li r0, PPC_IRQ_CPM_I2C
1206	b PROC (_ISR_Handler)
1207
1208	/* RISC Timer Table */
1209	mtlr r0
1210	lwz r9, IP_9(r1)
1211	li r0, PPC_IRQ_CPM_RISC_TIMER
1212	b PROC (_ISR_Handler)
1213
1214	/* Timer 2 */
1215	mtlr r0
1216	lwz r9, IP_9(r1)
1217	li r0, PPC_IRQ_CPM_TIMER2
1218	b PROC (_ISR_Handler)
1219
1220	/* Reserved - we should never get here */
1221	mtlr r0
1222	lwz r9, IP_9(r1)
1223	li r0, PPC_IRQ_CPM_RESERVED_13
1224	.long 0
1225
1226	/* IDMA2 */
1227	mtlr r0
1228	lwz r9, IP_9(r1)
1229	li r0, PPC_IRQ_CPM_IDMA2
1230	b PROC (_ISR_Handler)
1231
1232	/* IDMA1 */
1233	mtlr r0
1234	lwz r9, IP_9(r1)
1235	li r0, PPC_IRQ_CPM_IDMA1
1236	b PROC (_ISR_Handler)
1237
1238	/* SDMA Channel Bus Error */
1239	mtlr r0
1240	lwz r9, IP_9(r1)
1241	li r0, PPC_IRQ_CPM_SDMA_ERROR
1242	b PROC (_ISR_Handler)
1243
1244	/* PC12 */
1245	mtlr r0
1246	lwz r9, IP_9(r1)
1247	li r0, PPC_IRQ_CPM_PC12
1248	b PROC (_ISR_Handler)
1249
1250	/* PC13 */
1251	mtlr r0
1252	lwz r9, IP_9(r1)
1253	li r0, PPC_IRQ_CPM_PC13
1254	b PROC (_ISR_Handler)
1255
1256	/* Timer 1 */
1257	mtlr r0
1258	lwz r9, IP_9(r1)
1259	li r0, PPC_IRQ_CPM_TIMER1
1260	b PROC (_ISR_Handler)
1261
1262	/* PC14 */
1263	mtlr r0
1264	lwz r9, IP_9(r1)
1265	li r0, PPC_IRQ_CPM_PC14
1266	b PROC (_ISR_Handler)
1267
1268	/* SCC4 */
1269	mtlr r0
1270	lwz r9, IP_9(r1)
1271	li r0, PPC_IRQ_CPM_SCC4
1272	b PROC (_ISR_Handler)
1273
1274	/* SCC3 */
1275	mtlr r0
1276	lwz r9, IP_9(r1)
1277	li r0, PPC_IRQ_CPM_SCC3
1278	b PROC (_ISR_Handler)
1279
1280	/* SCC2 */
1281	mtlr r0
1282	lwz r9, IP_9(r1)
1283	li r0, PPC_IRQ_CPM_SCC2
1284	b PROC (_ISR_Handler)
1285
1286	/* SCC1 */
1287	mtlr r0
1288	lwz r9, IP_9(r1)
1289	li r0, PPC_IRQ_CPM_SCC1
1290	b PROC (_ISR_Handler)
1291
1292	/* PC15 */
1293	mtlr r0
1294	lwz r9, IP_9(r1)
1295	li r0, PPC_IRQ_CPM_PC15
1296	b PROC (_ISR_Handler)
1297
1298	.L_text_e:
1299
1300

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