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align_h.S @ 310a2ec

4.104.114.84.95

Last change on this file since 310a2ec was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 19:57:02

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

Property mode set to 100644

File size: 16.0 KB

Line
1	/* align_h.S 1.1 - 95/12/04
2	*
3	* This file contains the assembly code for the MPC860
4	* alignment exception handler for RTEMS.
5	*
6	* Based upon IBM provided code for the PowerPC 403 with the following release:
7	*
8	* This source code has been made available to you by IBM on an AS-IS
9	* basis. Anyone receiving this source is licensed under IBM
10	* copyrights to use it in any way he or she deems fit, including
11	* copying it, modifying it, compiling it, and redistributing it either
12	* with or without modifications. No license under IBM patents or
13	* patent applications is to be implied by the copyright license.
14	*
15	* Any user of this software should understand that IBM cannot provide
16	* technical support for this software and will not be responsible for
17	* any consequences resulting from the use of this software.
18	*
19	* Any person who transfers this source code or any derivative work
20	* must include the IBM copyright notice, this paragraph, and the
21	* preceding two paragraphs in the transferred software.
22	*
23	* COPYRIGHT I B M CORPORATION 1995
24	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
25	*
26	* Modifications:
27	*
28	* Author: Andrew Bray <andy@i-cubed.co.uk>
29	*
30	* COPYRIGHT (c) 1995 by i-cubed ltd.
31	*
32	* To anyone who acknowledges that this file is provided "AS IS"
33	* without any express or implied warranty:
34	* permission to use, copy, modify, and distribute this file
35	* for any purpose is hereby granted without fee, provided that
36	* the above copyright notice and this notice appears in all
37	* copies, and that the name of i-cubed limited not be used in
38	* advertising or publicity pertaining to distribution of the
39	* software without specific, written prior permission.
40	* i-cubed limited makes no representations about the suitability
41	* of this software for any purpose.
42	*
43	* Additional modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
44	* Removed saving and restoring of PPC403-specific SRR2 and SRR3.
45	* Access DAR instead of PPC403-specific DEAR.
46	*
47	* $Id$
48	*/
49
50	#include "asm.h"
51	#define ALIGN_REGS 0x0140
52
53	.set CACHE_SIZE,16 # cache line size of 32 bytes
54	.set CACHE_SIZE_L2,4 # cache line size, log 2
55
56	.set Open_gpr0,0
57	.set Open_gpr1,4
58	.set Open_gpr2,8
59	.set Open_gpr3,12
60	.set Open_gpr4,16
61	.set Open_gpr5,20
62	.set Open_gpr6,24
63	.set Open_gpr7,28
64	.set Open_gpr8,32
65	.set Open_gpr9,36
66	.set Open_gpr10,40
67	.set Open_gpr11,44
68	.set Open_gpr12,48
69	.set Open_gpr13,52
70	.set Open_gpr14,56
71	.set Open_gpr15,60
72	.set Open_gpr16,64
73	.set Open_gpr17,68
74	.set Open_gpr18,72
75	.set Open_gpr19,76
76	.set Open_gpr20,80
77	.set Open_gpr21,84
78	.set Open_gpr22,88
79	.set Open_gpr23,92
80	.set Open_gpr24,96
81	.set Open_gpr25,100
82	.set Open_gpr26,104
83	.set Open_gpr27,108
84	.set Open_gpr28,112
85	.set Open_gpr29,116
86	.set Open_gpr30,120
87	.set Open_gpr31,124
88	.set Open_xer,128
89	.set Open_lr,132
90	.set Open_ctr,136
91	.set Open_cr,140
92	.set Open_srr0,144
93	.set Open_srr1,148
94
95
96	/*
97	* This code makes several assumptions for processing efficiency
98	* * General purpose registers are continuous in the image, beginning with
99	* Open_gpr0
100	* * Hash table is highly dependent on opcodes - opcode changes will
101	* require rework of the instruction decode mechanism.
102	*/
103
104	.text
105	.globl align_h
106
107	.align CACHE_SIZE_L2
108	align_h:
109	/*-----------------------------------------------------------------------
110	* Store GPRs in Open Reg save area
111	* Set up r2 as base reg, r1 pointing to Open Reg save area
112	----------------------------------------------------------------------/
113	stmw r0,ALIGN_REGS(r0)
114	li r1,ALIGN_REGS
115	/*-----------------------------------------------------------------------
116	* Store special purpose registers in reg save area
117	----------------------------------------------------------------------/
118	mfxer r7
119	mflr r8
120	mfcr r9
121	mfctr r10
122	stw r7,Open_xer(r1)
123	stw r8,Open_lr(r1)
124	stw r9,Open_cr(r1)
125	stw r10,Open_ctr(r1)
126	mfspr r9, srr0 /* SRR 0 */
127	mfspr r10, srr1 /* SRR 1 */
128	stw r9,Open_srr0(r1)
129	stw r10,Open_srr1(r1)
130
131	/* Set up common registers */
132	mfspr r5, dar /* DAR: R5 is data (exception) address */
133	lwz r9,Open_srr0(r1) /* get faulting instruction */
134	addi r7,r9,4 /* bump instruction */
135	stw r7,Open_srr0(r1) /* restore to image */
136	lwz r9, 0(r9) /* retrieve actual instruction */
137	rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
138	rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
139	bl ref_point /* establish addressibility */
140	ref_point:
141	mflr r11 /* r11 is the anchor point for ref_point */
142	addi r10, r7, -31 /* r10 = r7 - 31 */
143	rlwinm r10,r10,2,2,31 /* r10 = 4 /
144	add r10, r10, r11 /* r10 += anchor point */
145	lwz r10, primary_jt-ref_point(r10)
146	mtlr r10
147	rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
148	la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
149	blr
150	primary_jt:
151	.long xform
152	.long lwz
153	.long lwzu
154	.long 0
155	.long 0
156	.long stw
157	.long stwu
158	.long 0
159	.long 0
160	.long lhz
161	.long lhzu
162	.long lha
163	.long lhau
164	.long sth
165	.long sthu
166	.long lmw
167	.long stmw
168	/*
169	* handlers
170	*/
171	/*
172	* xform instructions require an additional decode. Fortunately, a relatively
173	* simple hash step breaks the instructions out with no collisions
174	*/
175	xform:
176	rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
177	rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
178	add r10,r7,r10 /* r10 = r7 + r10 */
179	rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
180	add r10,r10,r11 /* r10 += anchor point */
181	lwz r10, secondary_ht-ref_point(r10)
182	mtlr r10
183	la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
184	rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
185	blrl
186
187	secondary_ht:
188	.long lhzux /* b 0 0x137 */
189	.long lhax /* b 1 0x157 */
190	.long lhaux /* b 2 0x177 */
191	.long sthx /* b 3 0x197 */
192	.long sthux /* b 4 0x1b7 */
193	.long 0 /* b 5 */
194	.long lwbrx /* b 6 0x216 */
195	.long 0 /* b 7 */
196	.long 0 /* b 8 */
197	.long 0 /* b 9 */
198	.long stwbrx /* b A 0x296 */
199	.long 0 /* b B */
200	.long 0 /* b C */
201	.long 0 /* b D */
202	.long lhbrx /* b E 0x316 */
203	.long 0 /* b F */
204	.long 0 /* b 10 */
205	.long 0 /* b 11 */
206	.long sthbrx /* b 12 0x396 */
207	.long 0 /* b 13 */
208	.long lwarx /* b 14 0x014 */
209	.long dcbz /* b 15 0x3f6 */
210	.long 0 /* b 16 */
211	.long lwzx /* b 17 0x017 */
212	.long lwzux /* b 18 0x037 */
213	.long 0 /* b 19 */
214	.long stwcx /* b 1A 0x096 */
215	.long stwx /* b 1B 0x097 */
216	.long stwux /* b 1C 0x0B7 */
217	.long 0 /* b 1D */
218	.long 0 /* b 1E */
219	.long lhzx /* b 1F 0x117 */
220
221	/*
222	* for all handlers
223	* r4 - Addressability to interrupt context
224	* r5 - DAR address (faulting data address)
225	* r6 - RA field * 4
226	* r7 - Address of GPR 0 in image
227	* r8 - RD field * 4
228	* r9 - Failing instruction
229	*/
230
231	/* Load halfword algebraic with update */
232	lhau:
233	/* Load halfword algebraic with update indexed */
234	lhaux:
235	stwx r5,r7,r6 /* update RA with effective addr */
236
237	/* Load halfword algebraic */
238	lha:
239	/* Load halfword algebraic indexed */
240	lhax:
241	lswi r10,r5,2 /* load two bytes into r10 */
242	srawi r10,r10,16 /* shift right 2 bytes, extending sign */
243	stwx r10,r7,r8 /* update reg image */
244	b align_complete /* return */
245
246	/* Load Half Word Byte-Reversed Indexed */
247	lhbrx:
248	lswi r10,r5,2 /* load two bytes from DEAR into r10 */
249	rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
250	stwbrx r10,r7,r8 /* store reversed in reg image */
251	b align_complete /* return */
252
253	/* Load Half Word and Zero with Update */
254	lhzu:
255	/* Load Half Word and Zero with Update Indexed */
256	lhzux:
257	stwx r5,r7,r6 /* update RA with effective addr */
258
259	/* Load Half Word and Zero */
260	lhz:
261	/* Load Half Word and Zero Indexed */
262	lhzx:
263	lswi r10,r5,2 /* load two bytes from DEAR into r10 */
264	rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
265	stwx r10,r7,r8 /* update reg image */
266	b align_complete /* return */
267
268	/*
269	* Load Multiple Word
270	*/
271	lmw:
272	lwzx r9,r6,r7 /* R9 contains saved value of RA */
273	addi r10,r7,324 / r10 points to r31 in image + 4 */
274	rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
275	subfic r8,r8,32 /* r8 is reg count to load */
276	mtctr r8 /* load counter */
277	addi r8,r8,-1 /* r8-- */
278	rlwinm r8,r8,2,2,31 /* r8 = 4 /
279	add r5,r5,r8 /* update DEAR to point to last reg */
280	lwmloop:
281	lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
282	stwu r11,-4(r10) /* load image and decrement pointer */
283	addi r5,r5,-4 /* decrement effective address */
284	bdnz lwmloop
285	stwx r9,r6,r7 /* restore RA (in case it was trashed) */
286	b align_complete /* return */
287
288	/*
289	* Load Word and Reserve Indexed
290	*/
291	lwarx:
292	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
293	stwx r10,r7,r8 /* update reg image */
294	rlwinm r5,r5,0,0,29 /* Word align address */
295	lwarx r10,0,r5 /* Set reservation */
296	b align_complete /* return */
297
298	/*
299	* Load Word Byte-Reversed Indexed
300	*/
301	lwbrx:
302	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
303	stwbrx r10,r7,r8 /* store reversed in reg image */
304	b align_complete /* return */
305
306	/* Load Word and Zero with Update */
307	lwzu:
308	/* Load Word and Zero with Update Indexed */
309	lwzux:
310	stwx r5,r7,r6 /* update RA with effective addr */
311
312	/* Load Word and Zero */
313	lwz:
314	/* Load Word and Zero Indexed */
315	lwzx:
316	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
317	stwx r10,r7,r8 /* update reg image */
318	b align_complete /* return */
319
320	/* Store instructions */
321
322	/* */
323	/* Store Half Word and Update */
324	sthu:
325	/* Store Half Word and Update Indexed */
326	sthux:
327	stwx r5,r7,r6 /* Update RA with effective address */
328
329	/* Store Half Word */
330	sth:
331	/* Store Half Word Indexed */
332	sthx:
333	lwzx r10,r8,r7 /* retrieve source register value */
334	rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
335	stswi r10,r5,2 /* store bytes to DEAR address */
336	b align_complete /* return */
337
338	/* */
339	/* Store Half Word Byte-Reversed Indexed */
340	sthbrx:
341	lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
342	stswi r10,r5,2 /* move two bytes to DEAR address */
343	b align_complete /* return */
344
345	/* */
346	/* Store Multiple Word */
347	stmw:
348	addi r10,r7,324 / r10 points to r31 in image + 4 */
349	rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
350	subfic r8,r8,32 /* r8 is reg count to load */
351	mtctr r8 /* load counter */
352	addi r8,r8,-1 /* r8-- */
353	rlwinm r8,r8,2,2,31 /* r8 = 4 /
354	add r5,r5,r8 /* update DEAR to point to last reg */
355	stmloop:
356	lwzu r11,-4(r10) /* get register value */
357	stswi r11,r5,4 /* output to DEAR address */
358	addi r5,r5,-4 /* decrement effective address */
359	bdnz stmloop
360	b align_complete /* return */
361
362	/* */
363	/* Store Word and Update */
364	stwu:
365	/* Store Word and Update Indexed */
366	stwux:
367	stwx r5,r7,r6 /* Update RA with effective address */
368
369	/* Store Word */
370	stw:
371	/* Store Word Indexed */
372	stwx:
373	lwzx r10,r8,r7 /* retrieve source register value */
374	stswi r10,r5,4 /* store bytes to DEAR address */
375	b align_complete /* return */
376
377	/* */
378	/* Store Word Byte-Reversed Indexed */
379	stwbrx:
380	lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
381	stswi r10,r5,4 /* move two bytes to DEAR address */
382	b align_complete /* return */
383
384	/* */
385	/* Store Word Conditional Indexed */
386	stwcx:
387	rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
388	lwz r11,0(r10) /* save original value of store */
389	stwcx. r11,r0,r10 /* attempt store to address */
390	bne stwcx_moveon /* store failed, move on */
391	stw r11,0(r10) /* repair damage */
392	lwzx r9,r7,r8 /* get register value */
393	stswi r10,r5,4 /* store bytes to DEAR address */
394	stwcx_moveon:
395	mfcr r11 /* get condition reg */
396	lwz r9,Open_cr(r1) /* get condition reg image */
397	rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
398	lwz r11,Open_xer(r1) /* get XER reg */
399	rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
400	stw r9,Open_cr(r1) /* store cr image */
401	b align_complete /* return */
402
403	/* */
404	/* Data Cache Block Zero */
405	dcbz:
406	rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
407	/* get address to nearest Cache line */
408	addi r5,r5,-4 /* adjust by a word */
409	addi r10,r0,CACHE_SIZE/4 /* set counter value */
410	mtctr r10
411	addi r11,r0,0 /* r11 = 0 */
412	dcbz_loop:
413	stwu r11,4(r5) /* store a word and update EA */
414	bdnz dcbz_loop
415	b align_complete /* return */
416
417	align_complete:
418	/*-----------------------------------------------------------------------
419	* Restore regs and return from the interrupt
420	----------------------------------------------------------------------/
421	lmw r26,Open_xer+ALIGN_REGS(r0)
422	mtxer r26
423	mtlr r27
424	mtctr r28
425	mtcrf 0xFF, r29
426	mtspr srr0, r30 /* SRR 0 */
427	mtspr srr1, r31 /* SRR 1 */
428	lmw r1,Open_gpr1+ALIGN_REGS(r0)
429	lwz r0,Open_gpr0+ALIGN_REGS(r0)
430	rfi

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