source: rtems/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @ 8ef3818

4.104.114.84.95
Last change on this file since 8ef3818 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 12, 2000 at 7:57:02 PM

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * mmu.c
3 *
4 * This file contains routines for initializing
5 * and manipulating the MMU on the MPC8xx.
6 *
7 * Copyright (c) 1999, National Research Council of Canada
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.OARcorp.com/rtems/license.html.
12 */
13
14#include <bsp.h>
15#include <mpc8xx/mmu.h>
16
17/*
18 * mmu_init
19 *
20 * This routine sets up the virtual memory maps on an MPC8xx.
21 * The MPC8xx does not support block address translation (BATs)
22 * and does not have segment registers. Thus, we must set up page
23 * translation. However, its MMU supports variable size pages
24 * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
25 *
26 * The MPC8xx has separate data and instruction 32-entry translation
27 * lookaside buffers (TLB). By mapping all of DRAM as one huge page,
28 * we can preload the TLBs and not have to be concerned with taking
29 * TLB miss exceptions.
30 *
31 * We set up the virtual memory map so that virtual address of a
32 * location is equal to its real address.
33 */
34void mmu_init( void )
35{
36  register unsigned32 reg1, i;
37
38  /*
39   * Initialize the TLBs
40   *
41   * Instruction address translation and data address translation
42   * must be disabled during initialization (IR=0, DR=0 in MSR).
43   * We can assume the MSR has already been set this way.
44   */
45
46  /*   
47   * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
48   *    GPM [0]                 0b0 = PowerPC mode
49   *    PPM [1]                 0b0 = Page resolution of protection
50   *    CIDEF [2]               0b0/0b1 = Default cache-inhibit attribute =
51   *                                                    NO for IMMU, YES for DMMU!
52   *    reserved/WTDEF [3]      0b0 = Default write-through attribute = not
53   *    RSV4x [4]               0b0 = 4 entries not reserved
54   *    reserved/TWAM [5]       0b0/0b1 = 4-Kbyte page hardware assist
55   *    PPCS [6]                0b0 = Ignore user/supervisor state
56   *    reserved [7-18]         0x00
57   *    xTLB_INDX [19-23]       31 = 0x1F
58   *    reserved [24-31]        0x00
59   *   
60   * Note: It is important that cache-inhibit be set as the default for the
61   * data cache when the DMMU is disabled in order to prevent internal memory
62   * mapped registers from being cached accidentally when address translation
63   * is turned off at the start of exception processing.
64   */
65  reg1 = M8xx_MI_CTR_ITLB_INDX(31);
66  _mtspr( M8xx_MI_CTR, reg1 );
67  reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
68  _mtspr( M8xx_MD_CTR, reg1 );
69  _isync;
70 
71  /*
72   * Invalidate all TLB entries in both TLBs.
73   * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
74   *       all 32 entries are invalidated.
75   */
76  __asm__ volatile ("tlbia\n"::);
77  _isync;
78 
79  /*
80   * Set Current Address Space ID Register (M_CASID).
81   * Supervisor: CASID = 0
82   */
83  reg1 = 0;
84  _mtspr( M8xx_M_CASID, reg1 );
85
86  /*
87   * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
88   * We ignore the Access Protection Group (APG) mechanism globally
89   * by setting all of the Mx_AP fields to 0b01 : client access
90   * permission is defined by page protection bits.
91   */
92  reg1 = 0x55555555;
93  _mtspr( M8xx_MI_AP, reg1 );
94  _mtspr( M8xx_MD_AP, reg1 );
95
96  /* 
97   * Load both 32-entry TLBs with values from the MMU_TLB_table
98   * which is defined in the BSP.
99   * Note the _TLB_Table must have at most 32 entries. This code
100   * makes no effort to enforce this restriction.
101   */
102  for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
103    reg1 = MMU_TLB_table[i].mmu_epn;
104    _mtspr( M8xx_MI_EPN, reg1 );
105    _mtspr( M8xx_MD_EPN, reg1 );
106    reg1 = MMU_TLB_table[i].mmu_twc;
107    _mtspr( M8xx_MI_TWC, reg1 );
108    _mtspr( M8xx_MD_TWC, reg1 );
109    reg1 = MMU_TLB_table[i].mmu_rpn;    /* RPN must be written last! */
110    _mtspr( M8xx_MI_RPN, reg1 );
111    _mtspr( M8xx_MD_RPN, reg1 );
112  }
113
114  /*
115   * Turn on address translation by setting MSR[IR] and MSR[DR].
116   */ 
117  _CPU_MSR_Value( reg1 );
118  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
119  _CPU_MSR_SET( reg1 );
120}
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