source: rtems/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @ 66c373bf

4.104.114.84.95
Last change on this file since 66c373bf was 66c373bf, checked in by Ralf Corsepius <ralf.corsepius@…>, on 03/31/04 at 02:04:00

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • mpc505/timer/timer.c, mpc5xx/timer/timer.c, mpc6xx/clock/c_clock.c, mpc6xx/timer/timer.c, mpc8260/clock/clock.c, mpc8260/console-generic/console-generic.c, mpc8260/cpm/cp.c, mpc8260/cpm/dpram.c, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/include/mpc8260.h, mpc8260/mmu/mmu.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/cpm/cp.c, mpc8xx/cpm/dpram.c, mpc8xx/include/cpm.h, mpc8xx/include/mmu.h, mpc8xx/include/mpc8xx.h, mpc8xx/mmu/mmu.c, mpc8xx/timer/timer.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console405.c, ppc403/ictrl/ictrl.c, ppc403/ictrl/ictrl.h, ppc403/timer/timer.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/src/cache.c: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * mmu.c
3 *
4 * This file contains routines for initializing
5 * and manipulating the MMU on the MPC8xx.
6 *
7 * Copyright (c) 1999, National Research Council of Canada
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.rtems.com/license/LICENSE.
12 */
13
14#include <rtems.h>
15#include <mpc8xx.h>
16#include <mpc8xx/mmu.h>
17
18/*
19 * mmu_init
20 *
21 * This routine sets up the virtual memory maps on an MPC8xx.
22 * The MPC8xx does not support block address translation (BATs)
23 * and does not have segment registers. Thus, we must set up page
24 * translation. However, its MMU supports variable size pages
25 * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
26 *
27 * The MPC8xx has separate data and instruction 32-entry translation
28 * lookaside buffers (TLB). By mapping all of DRAM as one huge page,
29 * we can preload the TLBs and not have to be concerned with taking
30 * TLB miss exceptions.
31 *
32 * We set up the virtual memory map so that virtual address of a
33 * location is equal to its real address.
34 */
35void mmu_init( void )
36{
37  register uint32_t   reg1, i;
38
39  /*
40   * Initialize the TLBs
41   *
42   * Instruction address translation and data address translation
43   * must be disabled during initialization (IR=0, DR=0 in MSR).
44   * We can assume the MSR has already been set this way.
45   */
46
47  /*   
48   * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
49   *    GPM [0]                 0b0 = PowerPC mode
50   *    PPM [1]                 0b0 = Page resolution of protection
51   *    CIDEF [2]               0b0/0b1 = Default cache-inhibit attribute =
52   *                                                    NO for IMMU, YES for DMMU!
53   *    reserved/WTDEF [3]      0b0 = Default write-through attribute = not
54   *    RSV4x [4]               0b0 = 4 entries not reserved
55   *    reserved/TWAM [5]       0b0/0b1 = 4-Kbyte page hardware assist
56   *    PPCS [6]                0b0 = Ignore user/supervisor state
57   *    reserved [7-18]         0x00
58   *    xTLB_INDX [19-23]       31 = 0x1F
59   *    reserved [24-31]        0x00
60   *   
61   * Note: It is important that cache-inhibit be set as the default for the
62   * data cache when the DMMU is disabled in order to prevent internal memory
63   * mapped registers from being cached accidentally when address translation
64   * is turned off at the start of exception processing.
65   */
66  reg1 = M8xx_MI_CTR_ITLB_INDX(31);
67  _mtspr( M8xx_MI_CTR, reg1 );
68  reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
69  _mtspr( M8xx_MD_CTR, reg1 );
70  _isync;
71 
72  /*
73   * Invalidate all TLB entries in both TLBs.
74   * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
75   *       all 32 entries are invalidated.
76   */
77  __asm__ volatile ("tlbia\n"::);
78  _isync;
79 
80  /*
81   * Set Current Address Space ID Register (M_CASID).
82   * Supervisor: CASID = 0
83   */
84  reg1 = 0;
85  _mtspr( M8xx_M_CASID, reg1 );
86
87  /*
88   * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
89   * We ignore the Access Protection Group (APG) mechanism globally
90   * by setting all of the Mx_AP fields to 0b01 : client access
91   * permission is defined by page protection bits.
92   */
93  reg1 = 0x55555555;
94  _mtspr( M8xx_MI_AP, reg1 );
95  _mtspr( M8xx_MD_AP, reg1 );
96
97  /* 
98   * Load both 32-entry TLBs with values from the MMU_TLB_table
99   * which is defined in the BSP.
100   * Note the _TLB_Table must have at most 32 entries. This code
101   * makes no effort to enforce this restriction.
102   */
103  for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
104    reg1 = MMU_TLB_table[i].mmu_epn;
105    _mtspr( M8xx_MI_EPN, reg1 );
106    _mtspr( M8xx_MD_EPN, reg1 );
107    reg1 = MMU_TLB_table[i].mmu_twc;
108    _mtspr( M8xx_MI_TWC, reg1 );
109    _mtspr( M8xx_MD_TWC, reg1 );
110    reg1 = MMU_TLB_table[i].mmu_rpn;    /* RPN must be written last! */
111    _mtspr( M8xx_MI_RPN, reg1 );
112    _mtspr( M8xx_MD_RPN, reg1 );
113  }
114
115  /*
116   * Turn on address translation by setting MSR[IR] and MSR[DR].
117   */
118  _CPU_MSR_GET( reg1 );
119  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
120  _CPU_MSR_SET( reg1 );
121}
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