1 | /* |
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2 | * mmu.c |
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3 | * |
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4 | * This file contains routines for initializing |
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5 | * and manipulating the MMU on the MPC8xx. |
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6 | * |
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7 | * Copyright (c) 1999, National Research Council of Canada |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <rtems/powerpc/powerpc.h> |
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16 | |
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17 | #include <mpc8xx.h> |
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18 | #include <mpc8xx/mmu.h> |
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19 | |
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20 | /* |
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21 | * mmu_init |
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22 | * |
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23 | * This routine sets up the virtual memory maps on an MPC8xx. |
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24 | * The MPC8xx does not support block address translation (BATs) |
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25 | * and does not have segment registers. Thus, we must set up page |
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26 | * translation. However, its MMU supports variable size pages |
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27 | * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. |
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28 | * |
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29 | * The MPC8xx has separate data and instruction 32-entry translation |
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30 | * lookaside buffers (TLB). By mapping all of DRAM as one huge page, |
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31 | * we can preload the TLBs and not have to be concerned with taking |
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32 | * TLB miss exceptions. |
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33 | * |
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34 | * We set up the virtual memory map so that virtual address of a |
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35 | * location is equal to its real address. |
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36 | */ |
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37 | void mmu_init( void ) |
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38 | { |
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39 | register uint32_t reg1, i; |
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40 | |
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41 | /* |
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42 | * Initialize the TLBs |
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43 | * |
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44 | * Instruction address translation and data address translation |
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45 | * must be disabled during initialization (IR=0, DR=0 in MSR). |
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46 | * We can assume the MSR has already been set this way. |
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47 | */ |
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48 | |
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49 | /* |
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50 | * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) |
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51 | * GPM [0] 0b0 = PowerPC mode |
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52 | * PPM [1] 0b0 = Page resolution of protection |
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53 | * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = |
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54 | * NO for IMMU, YES for DMMU! |
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55 | * reserved/WTDEF [3] 0b0 = Default write-through attribute = not |
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56 | * RSV4x [4] 0b0 = 4 entries not reserved |
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57 | * reserved/TWAM [5] 0b0/0b1 = 4-Kbyte page hardware assist |
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58 | * PPCS [6] 0b0 = Ignore user/supervisor state |
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59 | * reserved [7-18] 0x00 |
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60 | * xTLB_INDX [19-23] 31 = 0x1F |
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61 | * reserved [24-31] 0x00 |
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62 | * |
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63 | * Note: It is important that cache-inhibit be set as the default for the |
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64 | * data cache when the DMMU is disabled in order to prevent internal memory |
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65 | * mapped registers from being cached accidentally when address translation |
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66 | * is turned off at the start of exception processing. |
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67 | */ |
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68 | reg1 = M8xx_MI_CTR_ITLB_INDX(31); |
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69 | _mtspr( M8xx_MI_CTR, reg1 ); |
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70 | reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); |
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71 | _mtspr( M8xx_MD_CTR, reg1 ); |
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72 | _isync; |
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73 | |
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74 | /* |
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75 | * Invalidate all TLB entries in both TLBs. |
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76 | * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so |
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77 | * all 32 entries are invalidated. |
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78 | */ |
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79 | __asm__ volatile ("tlbia\n"::); |
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80 | _isync; |
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81 | |
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82 | /* |
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83 | * Set Current Address Space ID Register (M_CASID). |
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84 | * Supervisor: CASID = 0 |
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85 | */ |
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86 | reg1 = 0; |
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87 | _mtspr( M8xx_M_CASID, reg1 ); |
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88 | |
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89 | /* |
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90 | * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) |
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91 | * We ignore the Access Protection Group (APG) mechanism globally |
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92 | * by setting all of the Mx_AP fields to 0b01 : client access |
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93 | * permission is defined by page protection bits. |
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94 | */ |
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95 | reg1 = 0x55555555; |
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96 | _mtspr( M8xx_MI_AP, reg1 ); |
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97 | _mtspr( M8xx_MD_AP, reg1 ); |
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98 | |
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99 | /* |
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100 | * Load both 32-entry TLBs with values from the MMU_TLB_table |
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101 | * which is defined in the BSP. |
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102 | * Note the _TLB_Table must have at most 32 entries. This code |
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103 | * makes no effort to enforce this restriction. |
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104 | */ |
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105 | for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { |
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106 | reg1 = MMU_TLB_table[i].mmu_epn; |
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107 | _mtspr( M8xx_MI_EPN, reg1 ); |
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108 | _mtspr( M8xx_MD_EPN, reg1 ); |
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109 | reg1 = MMU_TLB_table[i].mmu_twc; |
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110 | _mtspr( M8xx_MI_TWC, reg1 ); |
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111 | _mtspr( M8xx_MD_TWC, reg1 ); |
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112 | reg1 = MMU_TLB_table[i].mmu_rpn; /* RPN must be written last! */ |
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113 | _mtspr( M8xx_MI_RPN, reg1 ); |
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114 | _mtspr( M8xx_MD_RPN, reg1 ); |
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115 | } |
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116 | |
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117 | /* |
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118 | * Turn on address translation by setting MSR[IR] and MSR[DR]. |
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119 | */ |
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120 | _CPU_MSR_GET( reg1 ); |
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121 | reg1 |= PPC_MSR_IR | PPC_MSR_DR; |
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122 | _CPU_MSR_SET( reg1 ); |
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123 | } |
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