source: rtems/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @ 371872ac

4.104.114.84.95
Last change on this file since 371872ac was 371872ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/14/05 at 04:39:30

2005-02-14 Ralf Corsepius <ralf.corsepius@…>

  • mpc8xx/mmu/mmu.c, rtems/powerpc/cache.h, rtems/powerpc/powerpc.h: #include <rtems/powerpc/powerpc.h>.
  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * mmu.c
3 *
4 * This file contains routines for initializing
5 * and manipulating the MMU on the MPC8xx.
6 *
7 * Copyright (c) 1999, National Research Council of Canada
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.rtems.com/license/LICENSE.
12 */
13
14#include <rtems.h>
15#include <rtems/powerpc/powerpc.h>
16
17#include <mpc8xx.h>
18#include <mpc8xx/mmu.h>
19
20/*
21 * mmu_init
22 *
23 * This routine sets up the virtual memory maps on an MPC8xx.
24 * The MPC8xx does not support block address translation (BATs)
25 * and does not have segment registers. Thus, we must set up page
26 * translation. However, its MMU supports variable size pages
27 * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
28 *
29 * The MPC8xx has separate data and instruction 32-entry translation
30 * lookaside buffers (TLB). By mapping all of DRAM as one huge page,
31 * we can preload the TLBs and not have to be concerned with taking
32 * TLB miss exceptions.
33 *
34 * We set up the virtual memory map so that virtual address of a
35 * location is equal to its real address.
36 */
37void mmu_init( void )
38{
39  register uint32_t   reg1, i;
40
41  /*
42   * Initialize the TLBs
43   *
44   * Instruction address translation and data address translation
45   * must be disabled during initialization (IR=0, DR=0 in MSR).
46   * We can assume the MSR has already been set this way.
47   */
48
49  /*   
50   * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
51   *    GPM [0]                 0b0 = PowerPC mode
52   *    PPM [1]                 0b0 = Page resolution of protection
53   *    CIDEF [2]               0b0/0b1 = Default cache-inhibit attribute =
54   *                                                    NO for IMMU, YES for DMMU!
55   *    reserved/WTDEF [3]      0b0 = Default write-through attribute = not
56   *    RSV4x [4]               0b0 = 4 entries not reserved
57   *    reserved/TWAM [5]       0b0/0b1 = 4-Kbyte page hardware assist
58   *    PPCS [6]                0b0 = Ignore user/supervisor state
59   *    reserved [7-18]         0x00
60   *    xTLB_INDX [19-23]       31 = 0x1F
61   *    reserved [24-31]        0x00
62   *   
63   * Note: It is important that cache-inhibit be set as the default for the
64   * data cache when the DMMU is disabled in order to prevent internal memory
65   * mapped registers from being cached accidentally when address translation
66   * is turned off at the start of exception processing.
67   */
68  reg1 = M8xx_MI_CTR_ITLB_INDX(31);
69  _mtspr( M8xx_MI_CTR, reg1 );
70  reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
71  _mtspr( M8xx_MD_CTR, reg1 );
72  _isync;
73 
74  /*
75   * Invalidate all TLB entries in both TLBs.
76   * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
77   *       all 32 entries are invalidated.
78   */
79  __asm__ volatile ("tlbia\n"::);
80  _isync;
81 
82  /*
83   * Set Current Address Space ID Register (M_CASID).
84   * Supervisor: CASID = 0
85   */
86  reg1 = 0;
87  _mtspr( M8xx_M_CASID, reg1 );
88
89  /*
90   * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
91   * We ignore the Access Protection Group (APG) mechanism globally
92   * by setting all of the Mx_AP fields to 0b01 : client access
93   * permission is defined by page protection bits.
94   */
95  reg1 = 0x55555555;
96  _mtspr( M8xx_MI_AP, reg1 );
97  _mtspr( M8xx_MD_AP, reg1 );
98
99  /* 
100   * Load both 32-entry TLBs with values from the MMU_TLB_table
101   * which is defined in the BSP.
102   * Note the _TLB_Table must have at most 32 entries. This code
103   * makes no effort to enforce this restriction.
104   */
105  for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
106    reg1 = MMU_TLB_table[i].mmu_epn;
107    _mtspr( M8xx_MI_EPN, reg1 );
108    _mtspr( M8xx_MD_EPN, reg1 );
109    reg1 = MMU_TLB_table[i].mmu_twc;
110    _mtspr( M8xx_MI_TWC, reg1 );
111    _mtspr( M8xx_MD_TWC, reg1 );
112    reg1 = MMU_TLB_table[i].mmu_rpn;    /* RPN must be written last! */
113    _mtspr( M8xx_MI_RPN, reg1 );
114    _mtspr( M8xx_MD_RPN, reg1 );
115  }
116
117  /*
118   * Turn on address translation by setting MSR[IR] and MSR[DR].
119   */
120  _CPU_MSR_GET( reg1 );
121  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
122  _CPU_MSR_SET( reg1 );
123}
Note: See TracBrowser for help on using the repository browser.