1 | /* |
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2 | ************************************************************************** |
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3 | ************************************************************************** |
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4 | ** ** |
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5 | ** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR ** |
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6 | ** ** |
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7 | ** HARDWARE DECLARATIONS ** |
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8 | ** ** |
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9 | ** ** |
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10 | ** Submitted By: ** |
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11 | ** ** |
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12 | ** W. Eric Norum ** |
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13 | ** Saskatchewan Accelerator Laboratory ** |
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14 | ** University of Saskatchewan ** |
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15 | ** 107 North Road ** |
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16 | ** Saskatoon, Saskatchewan, CANADA ** |
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17 | ** S7N 5C6 ** |
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18 | ** ** |
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19 | ** eric@skatter.usask.ca ** |
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20 | ** ** |
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21 | ** Modified for use with the MPC860 (original code was for MC68360) ** |
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22 | ** by ** |
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23 | ** Jay Monkman ** |
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24 | ** Frasca International, Inc. ** |
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25 | ** 906 E. Airport Rd. ** |
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26 | ** Urbana, IL, 61801 ** |
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27 | ** ** |
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28 | ** jmonkman@frasca.com ** |
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29 | ** ** |
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30 | ** Modified further for use with the MPC821 by: ** |
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31 | ** Andrew Bray <andy@chaos.org.uk> ** |
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32 | ** ** |
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33 | ** With some corrections/additions by: ** |
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34 | ** Darlene A. Stewart and ** |
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35 | ** Charles-Antoine Gauthier ** |
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36 | ** Institute for Information Technology ** |
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37 | ** National Research Council of Canada ** |
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38 | ** Ottawa, ON K1A 0R6 ** |
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39 | ** ** |
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40 | ** Darlene.Stewart@iit.nrc.ca ** |
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41 | ** charles.gauthier@iit.nrc.ca ** |
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42 | ** ** |
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43 | ** Corrections/additions: ** |
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44 | ** Copyright (c) 1999, National Research Council of Canada ** |
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45 | ************************************************************************** |
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46 | ************************************************************************** |
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47 | */ |
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48 | |
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49 | #ifndef _MPC8XX_H |
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50 | #define _MPC8XX_H |
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51 | |
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52 | #ifndef ASM |
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53 | |
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54 | #ifdef __cplusplus |
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55 | extern "C" { |
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56 | #endif |
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57 | |
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58 | /* |
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59 | * Macros for accessing Special Purpose Registers (SPRs) |
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60 | */ |
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61 | #define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) |
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62 | #define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) ) |
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63 | |
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64 | #define _isync __asm__ volatile ("isync\n"::) |
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65 | |
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66 | /* |
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67 | * Core Registers (SPRs) |
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68 | */ |
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69 | #define M8xx_DEC 22 /* Decrementer Register */ |
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70 | #define M8xx_DER 149 /* Debug Enable Register */ |
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71 | #define M8xx_ICTRL 158 /* Instruction Support Control Register */ |
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72 | #define M8xx_TBL_WR 284 /* Timebase Lower Write Register */ |
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73 | #define M8xx_TBU_WR 285 /* Timebase Upper Write Register */ |
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74 | #define M8xx_IMMR 638 /* Internal Memory Map Register */ |
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75 | |
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76 | /* |
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77 | * Cache Control Registers (SPRs) |
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78 | */ |
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79 | #define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */ |
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80 | #define M8xx_DC_CST 568 /* Data Cache Control and Status Register */ |
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81 | #define M8xx_IC_ADR 561 /* Instruction Cache Address Register */ |
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82 | #define M8xx_DC_ADR 569 /* Data Cache Address Register */ |
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83 | #define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */ |
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84 | #define M8xx_DC_DAT 570 /* Data Cache Data Port Register */ |
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85 | |
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86 | /* |
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87 | * MMU Registers (SPRs) |
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88 | */ |
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89 | /* Control Registers */ |
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90 | #define M8xx_MI_CTR 784 /* IMMU Control Register */ |
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91 | #define M8xx_MD_CTR 792 /* DMMU Control Register */ |
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92 | /* TLB Source Registers */ |
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93 | #define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */ |
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94 | #define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */ |
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95 | #define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */ |
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96 | #define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */ |
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97 | #define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */ |
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98 | #define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */ |
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99 | /* Tablewalk Assist Registers */ |
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100 | #define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */ |
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101 | /* Protection Registers */ |
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102 | #define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */ |
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103 | #define M8xx_MI_AP 786 /* IMMU Access Protection Register */ |
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104 | #define M8xx_MD_AP 794 /* DMMU Access Protection Register */ |
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105 | /* Scratch Register */ |
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106 | #define M8xx_M_TW 799 /* MMU Tablewalk Special Register */ |
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107 | /* Debug Registers */ |
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108 | #define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */ |
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109 | #define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */ |
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110 | #define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */ |
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111 | #define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */ |
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112 | #define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */ |
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113 | #define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */ |
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114 | |
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115 | #define M8xx_MI_CTR_GPM (1<<31) |
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116 | #define M8xx_MI_CTR_PPM (1<<30) |
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117 | #define M8xx_MI_CTR_CIDEF (1<<29) |
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118 | #define M8xx_MI_CTR_RSV4I (1<<27) |
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119 | #define M8xx_MI_CTR_PPCS (1<<25) |
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120 | #define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */ |
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121 | |
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122 | #define M8xx_MD_CTR_GPM (1<<31) |
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123 | #define M8xx_MD_CTR_PPM (1<<30) |
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124 | #define M8xx_MD_CTR_CIDEF (1<<29) |
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125 | #define M8xx_MD_CTR_WTDEF (1<<28) |
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126 | #define M8xx_MD_CTR_RSV4D (1<<27) |
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127 | #define M8xx_MD_CTR_TWAM (1<<26) |
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128 | #define M8xx_MD_CTR_PPCS (1<<25) |
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129 | #define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */ |
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130 | |
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131 | #define M8xx_MI_EPN_VALID (1<<9) |
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132 | |
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133 | #define M8xx_MD_EPN_VALID (1<<9) |
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134 | |
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135 | #define M8xx_MI_TWC_G (1<<4) |
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136 | #define M8xx_MI_TWC_PSS (0<<2) |
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137 | #define M8xx_MI_TWC_PS512 (1<<2) |
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138 | #define M8xx_MI_TWC_PS8 (3<<2) |
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139 | #define M8xx_MI_TWC_VALID (1) |
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140 | |
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141 | #define M8xx_MD_TWC_G (1<<4) |
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142 | #define M8xx_MD_TWC_PSS (0<<2) |
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143 | #define M8xx_MD_TWC_PS512 (1<<2) |
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144 | #define M8xx_MD_TWC_PS8 (3<<2) |
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145 | #define M8xx_MD_TWC_WT (1<<1) |
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146 | #define M8xx_MD_TWC_VALID (1) |
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147 | |
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148 | #define M8xx_MI_RPN_F (0xf<<4) |
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149 | #define M8xx_MI_RPN_16K (1<<3) |
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150 | #define M8xx_MI_RPN_SHARED (1<<2) |
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151 | #define M8xx_MI_RPN_CI (1<<1) |
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152 | #define M8xx_MI_RPN_VALID (1) |
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153 | |
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154 | #define M8xx_MD_RPN_CHANGE (1<<8) |
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155 | #define M8xx_MD_RPN_F (0xf<<4) |
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156 | #define M8xx_MD_RPN_16K (1<<3) |
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157 | #define M8xx_MD_RPN_SHARED (1<<2) |
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158 | #define M8xx_MD_RPN_CI (1<<1) |
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159 | #define M8xx_MD_RPN_VALID (1) |
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160 | |
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161 | #define M8xx_MI_AP_Kp (1) |
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162 | |
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163 | #define M8xx_MD_AP_Kp (1) |
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164 | |
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165 | #define M8xx_CACHE_CMD_SFWT (0x1<<24) |
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166 | #define M8xx_CACHE_CMD_ENABLE (0x2<<24) |
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167 | #define M8xx_CACHE_CMD_CFWT (0x3<<24) |
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168 | #define M8xx_CACHE_CMD_DISABLE (0x4<<24) |
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169 | #define M8xx_CACHE_CMD_STLES (0x5<<24) |
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170 | #define M8xx_CACHE_CMD_LLCB (0x6<<24) |
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171 | #define M8xx_CACHE_CMD_CLES (0x7<<24) |
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172 | #define M8xx_CACHE_CMD_UNLOCK (0x8<<24) |
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173 | #define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24) |
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174 | #define M8xx_CACHE_CMD_INVALIDATE (0xc<<24) |
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175 | #define M8xx_CACHE_CMD_FLUSH (0xe<<24) |
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176 | |
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177 | /* |
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178 | ************************************************************************* |
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179 | * REGISTER SUBBLOCKS * |
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180 | ************************************************************************* |
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181 | */ |
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182 | |
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183 | /* |
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184 | * Memory controller registers |
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185 | */ |
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186 | typedef struct m8xxMEMCRegisters_ { |
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187 | uint32_t _br; |
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188 | uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ |
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189 | } m8xxMEMCRegisters_t; |
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190 | |
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191 | /* |
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192 | * Serial Communications Controller registers |
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193 | */ |
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194 | typedef struct m8xxSCCRegisters_ { |
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195 | uint32_t gsmr_l; |
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196 | uint32_t gsmr_h; |
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197 | uint16_t psmr; |
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198 | uint16_t _pad0; |
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199 | uint16_t todr; |
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200 | uint16_t dsr; |
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201 | uint16_t scce; |
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202 | uint16_t _pad1; |
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203 | uint16_t sccm; |
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204 | uint8_t _pad2; |
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205 | uint8_t sccs; |
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206 | uint32_t _pad3[2]; |
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207 | } m8xxSCCRegisters_t; |
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208 | |
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209 | /* |
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210 | * Serial Management Controller registers |
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211 | */ |
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212 | typedef struct m8xxSMCRegisters_ { |
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213 | uint16_t _pad0; |
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214 | uint16_t smcmr; |
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215 | uint16_t _pad1; |
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216 | uint8_t smce; |
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217 | uint8_t _pad2; |
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218 | uint16_t _pad3; |
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219 | uint8_t smcm; |
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220 | uint8_t _pad4; |
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221 | uint32_t _pad5; |
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222 | } m8xxSMCRegisters_t; |
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223 | |
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224 | /* |
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225 | * Fast Ethernet Controller registers (Only on MPC8xxT) |
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226 | */ |
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227 | typedef struct m8xxFECRegisters_ { |
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228 | uint32_t addr_low; |
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229 | uint32_t addr_high; |
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230 | uint32_t hash_table_high; |
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231 | uint32_t hash_table_low; |
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232 | uint32_t r_des_start; |
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233 | uint32_t x_des_start; |
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234 | uint32_t r_buf_size; |
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235 | uint32_t _pad0[9]; |
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236 | uint32_t ecntrl; |
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237 | uint32_t ievent; |
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238 | uint32_t imask; |
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239 | uint32_t ivec; |
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240 | uint32_t r_des_active; |
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241 | uint32_t x_des_active; |
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242 | uint32_t _pad1[10]; |
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243 | uint32_t mii_data; |
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244 | uint32_t mii_speed; |
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245 | uint32_t _pad2[17]; |
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246 | uint32_t r_bound; |
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247 | uint32_t r_fstart; |
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248 | uint32_t _pad3[6]; |
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249 | uint32_t x_fstart; |
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250 | uint32_t _pad4[17]; |
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251 | uint32_t fun_code; |
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252 | uint32_t _pad5[3]; |
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253 | uint32_t r_cntrl; |
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254 | uint32_t r_hash; |
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255 | uint32_t _pad6[14]; |
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256 | uint32_t x_cntrl; |
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257 | uint32_t _pad7[30]; |
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258 | |
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259 | } m8xxFECRegisters_t; |
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260 | |
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261 | #define M8xx_FEC_IEVENT_HBERR (1 << 31) |
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262 | #define M8xx_FEC_IEVENT_BABR (1 << 30) |
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263 | #define M8xx_FEC_IEVENT_BABT (1 << 29) |
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264 | #define M8xx_FEC_IEVENT_GRA (1 << 28) |
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265 | #define M8xx_FEC_IEVENT_TFINT (1 << 27) |
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266 | #define M8xx_FEC_IEVENT_TXB (1 << 26) |
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267 | #define M8xx_FEC_IEVENT_RFINT (1 << 25) |
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268 | #define M8xx_FEC_IEVENT_RXB (1 << 24) |
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269 | #define M8xx_FEC_IEVENT_MII (1 << 23) |
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270 | #define M8xx_FEC_IEVENT_EBERR (1 << 22) |
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271 | #define M8xx_FEC_IMASK_HBEEN (1 << 31) |
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272 | #define M8xx_FEC_IMASK_BREEN (1 << 30) |
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273 | #define M8xx_FEC_IMASK_BTEN (1 << 29) |
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274 | #define M8xx_FEC_IMASK_GRAEN (1 << 28) |
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275 | #define M8xx_FEC_IMASK_TFIEN (1 << 27) |
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276 | #define M8xx_FEC_IMASK_TBIEN (1 << 26) |
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277 | #define M8xx_FEC_IMASK_RFIEN (1 << 25) |
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278 | #define M8xx_FEC_IMASK_RBIEN (1 << 24) |
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279 | #define M8xx_FEC_IMASK_MIIEN (1 << 23) |
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280 | #define M8xx_FEC_IMASK_EBERREN (1 << 22) |
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281 | |
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282 | /* |
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283 | ************************************************************************* |
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284 | * Miscellaneous Parameters * |
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285 | ************************************************************************* |
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286 | */ |
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287 | typedef struct m8xxMiscParms_ { |
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288 | uint16_t rev_num; |
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289 | uint16_t _res1; |
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290 | uint32_t _res2; |
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291 | uint32_t _res3; |
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292 | } m8xxMiscParms_t; |
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293 | |
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294 | /* |
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295 | ************************************************************************* |
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296 | * RISC Timers * |
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297 | ************************************************************************* |
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298 | */ |
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299 | typedef struct m8xxTimerParms_ { |
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300 | uint16_t tm_base; |
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301 | uint16_t _tm_ptr; |
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302 | uint16_t _r_tmr; |
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303 | uint16_t _r_tmv; |
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304 | uint32_t tm_cmd; |
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305 | uint32_t tm_cnt; |
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306 | } m8xxTimerParms_t; |
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307 | |
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308 | /* |
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309 | * RISC Controller Configuration Register (RCCR) |
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310 | * All other bits in this register are reserved. |
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311 | */ |
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312 | #define M8xx_RCCR_TIME (1<<15) /* Enable timer */ |
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313 | #define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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314 | #define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ |
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315 | #define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ |
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316 | #define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ |
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317 | #define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */ |
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318 | #define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */ |
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319 | #define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ |
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320 | |
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321 | /* |
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322 | * Command register |
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323 | * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command. |
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324 | */ |
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325 | #define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */ |
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326 | #define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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327 | #define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */ |
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328 | #define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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329 | #define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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330 | |
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331 | /* |
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332 | ************************************************************************* |
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333 | * DMA Controllers * |
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334 | ************************************************************************* |
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335 | */ |
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336 | typedef struct m8xxIDMAparms_ { |
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337 | uint16_t ibase; |
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338 | uint16_t dcmr; |
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339 | uint32_t _sapr; |
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340 | uint32_t _dapr; |
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341 | uint16_t ibptr; |
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342 | uint16_t _write_sp; |
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343 | uint32_t _s_byte_c; |
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344 | uint32_t _d_byte_c; |
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345 | uint32_t _s_state; |
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346 | uint32_t _itemp[4]; |
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347 | uint32_t _sr_mem; |
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348 | uint16_t _read_sp; |
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349 | uint16_t _res0; |
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350 | uint16_t _res1; |
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351 | uint16_t _res2; |
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352 | uint32_t _d_state; |
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353 | } m8xxIDMAparms_t; |
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354 | |
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355 | |
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356 | /* |
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357 | ************************************************************************* |
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358 | * DSP * |
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359 | ************************************************************************* |
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360 | */ |
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361 | typedef struct m8xxDSPparms_ { |
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362 | uint32_t fdbase; |
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363 | uint32_t _fd_ptr; |
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364 | uint32_t _dstate; |
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365 | uint32_t _pad0; |
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366 | uint16_t _dstatus; |
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367 | uint16_t _i; |
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368 | uint16_t _tap; |
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369 | uint16_t _cbase; |
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370 | uint16_t _pad1; |
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371 | uint16_t _xptr; |
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372 | uint16_t _pad2; |
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373 | uint16_t _yptr; |
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374 | uint16_t _m; |
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375 | uint16_t _pad3; |
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376 | uint16_t _n; |
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377 | uint16_t _pad4; |
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378 | uint16_t _k; |
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379 | uint16_t _pad5; |
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380 | } m8xxDSPparms_t; |
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381 | |
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382 | /* |
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383 | ************************************************************************* |
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384 | * Serial Communication Controllers * |
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385 | ************************************************************************* |
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386 | */ |
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387 | typedef struct m8xxSCCparms_ { |
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388 | uint16_t rbase; |
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389 | uint16_t tbase; |
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390 | uint8_t rfcr; |
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391 | uint8_t tfcr; |
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392 | uint16_t mrblr; |
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393 | uint32_t _rstate; |
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394 | uint32_t _pad0; |
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395 | uint16_t _rbptr; |
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396 | uint16_t _pad1; |
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397 | uint32_t _pad2; |
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398 | uint32_t _tstate; |
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399 | uint32_t _pad3; |
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400 | uint16_t _tbptr; |
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401 | uint16_t _pad4; |
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402 | uint32_t _pad5; |
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403 | uint32_t _rcrc; |
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404 | uint32_t _tcrc; |
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405 | union { |
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406 | struct { |
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407 | uint32_t _res0; |
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408 | uint32_t _res1; |
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409 | uint16_t max_idl; |
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410 | uint16_t _idlc; |
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411 | uint16_t brkcr; |
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412 | uint16_t parec; |
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413 | uint16_t frmec; |
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414 | uint16_t nosec; |
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415 | uint16_t brkec; |
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416 | uint16_t brkln; |
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417 | uint16_t uaddr[2]; |
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418 | uint16_t _rtemp; |
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419 | uint16_t toseq; |
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420 | uint16_t character[8]; |
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421 | uint16_t rccm; |
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422 | uint16_t rccr; |
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423 | uint16_t rlbc; |
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424 | } uart; |
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425 | } un; |
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426 | } m8xxSCCparms_t; |
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427 | |
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428 | typedef struct m8xxSCCENparms_ { |
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429 | uint16_t rbase; |
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430 | uint16_t tbase; |
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431 | uint8_t rfcr; |
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432 | uint8_t tfcr; |
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433 | uint16_t mrblr; |
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434 | uint32_t _rstate; |
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435 | uint32_t _pad0; |
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436 | uint16_t _rbptr; |
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437 | uint16_t _pad1; |
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438 | uint32_t _pad2; |
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439 | uint32_t _tstate; |
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440 | uint32_t _pad3; |
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441 | uint16_t _tbptr; |
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442 | uint16_t _pad4; |
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443 | uint32_t _pad5; |
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444 | uint32_t _rcrc; |
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445 | uint32_t _tcrc; |
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446 | union { |
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447 | struct { |
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448 | uint32_t _res0; |
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449 | uint32_t _res1; |
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450 | uint16_t max_idl; |
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451 | uint16_t _idlc; |
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452 | uint16_t brkcr; |
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453 | uint16_t parec; |
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454 | uint16_t frmec; |
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455 | uint16_t nosec; |
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456 | uint16_t brkec; |
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457 | uint16_t brkln; |
---|
458 | uint16_t uaddr[2]; |
---|
459 | uint16_t _rtemp; |
---|
460 | uint16_t toseq; |
---|
461 | uint16_t character[8]; |
---|
462 | uint16_t rccm; |
---|
463 | uint16_t rccr; |
---|
464 | uint16_t rlbc; |
---|
465 | } uart; |
---|
466 | struct { |
---|
467 | uint32_t c_pres; |
---|
468 | uint32_t c_mask; |
---|
469 | uint32_t crcec; |
---|
470 | uint32_t alec; |
---|
471 | uint32_t disfc; |
---|
472 | uint16_t pads; |
---|
473 | uint16_t ret_lim; |
---|
474 | uint16_t _ret_cnt; |
---|
475 | uint16_t mflr; |
---|
476 | uint16_t minflr; |
---|
477 | uint16_t maxd1; |
---|
478 | uint16_t maxd2; |
---|
479 | uint16_t _maxd; |
---|
480 | uint16_t dma_cnt; |
---|
481 | uint16_t _max_b; |
---|
482 | uint16_t gaddr1; |
---|
483 | uint16_t gaddr2; |
---|
484 | uint16_t gaddr3; |
---|
485 | uint16_t gaddr4; |
---|
486 | uint32_t _tbuf0data0; |
---|
487 | uint32_t _tbuf0data1; |
---|
488 | uint32_t _tbuf0rba0; |
---|
489 | uint32_t _tbuf0crc; |
---|
490 | uint16_t _tbuf0bcnt; |
---|
491 | uint16_t paddr_h; |
---|
492 | uint16_t paddr_m; |
---|
493 | uint16_t paddr_l; |
---|
494 | uint16_t p_per; |
---|
495 | uint16_t _rfbd_ptr; |
---|
496 | uint16_t _tfbd_ptr; |
---|
497 | uint16_t _tlbd_ptr; |
---|
498 | uint32_t _tbuf1data0; |
---|
499 | uint32_t _tbuf1data1; |
---|
500 | uint32_t _tbuf1rba0; |
---|
501 | uint32_t _tbuf1crc; |
---|
502 | uint16_t _tbuf1bcnt; |
---|
503 | uint16_t _tx_len; |
---|
504 | uint16_t iaddr1; |
---|
505 | uint16_t iaddr2; |
---|
506 | uint16_t iaddr3; |
---|
507 | uint16_t iaddr4; |
---|
508 | uint16_t _boff_cnt; |
---|
509 | uint16_t taddr_l; |
---|
510 | uint16_t taddr_m; |
---|
511 | uint16_t taddr_h; |
---|
512 | } ethernet; |
---|
513 | } un; |
---|
514 | } m8xxSCCENparms_t; |
---|
515 | |
---|
516 | /* |
---|
517 | * Receive and transmit function code register bits |
---|
518 | * These apply to the function code registers of all devices, not just SCC. |
---|
519 | */ |
---|
520 | #define M8xx_RFCR_BO(x) ((x)<<3) |
---|
521 | #define M8xx_RFCR_MOT (2<<3) |
---|
522 | #define M8xx_RFCR_DMA_SPACE(x) (x) |
---|
523 | #define M8xx_TFCR_BO(x) ((x)<<3) |
---|
524 | #define M8xx_TFCR_MOT (2<<3) |
---|
525 | #define M8xx_TFCR_DMA_SPACE(x) (x) |
---|
526 | |
---|
527 | /* |
---|
528 | * Event and mask registers (SCCE, SCCM) |
---|
529 | */ |
---|
530 | #define M8xx_SCCE_BRKE (1<<6) |
---|
531 | #define M8xx_SCCE_BRK (1<<4) |
---|
532 | #define M8xx_SCCE_BSY (1<<2) |
---|
533 | #define M8xx_SCCE_TX (1<<1) |
---|
534 | #define M8xx_SCCE_RX (1<<0) |
---|
535 | |
---|
536 | /* |
---|
537 | ************************************************************************* |
---|
538 | * Serial Management Controllers * |
---|
539 | ************************************************************************* |
---|
540 | */ |
---|
541 | typedef struct m8xxSMCparms_ { |
---|
542 | uint16_t rbase; |
---|
543 | uint16_t tbase; |
---|
544 | uint8_t rfcr; |
---|
545 | uint8_t tfcr; |
---|
546 | uint16_t mrblr; |
---|
547 | uint32_t _rstate; |
---|
548 | uint32_t _pad0; |
---|
549 | uint16_t _rbptr; |
---|
550 | uint16_t _pad1; |
---|
551 | uint32_t _pad2; |
---|
552 | uint32_t _tstate; |
---|
553 | uint32_t _pad3; |
---|
554 | uint16_t _tbptr; |
---|
555 | uint16_t _pad4; |
---|
556 | uint32_t _pad5; |
---|
557 | union { |
---|
558 | struct { |
---|
559 | uint16_t max_idl; |
---|
560 | uint16_t _idlc; |
---|
561 | uint16_t brkln; |
---|
562 | uint16_t brkec; |
---|
563 | uint16_t brkcr; |
---|
564 | uint16_t _r_mask; |
---|
565 | } uart; |
---|
566 | struct { |
---|
567 | uint16_t _pad0[5]; |
---|
568 | } transparent; |
---|
569 | } un; |
---|
570 | } m8xxSMCparms_t; |
---|
571 | |
---|
572 | /* |
---|
573 | * Mode register |
---|
574 | */ |
---|
575 | #define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
---|
576 | #define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
---|
577 | #define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */ |
---|
578 | #define M8xx_SMCMR_EVEN (1<<8) /* Even parity */ |
---|
579 | #define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
---|
580 | #define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */ |
---|
581 | #define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
---|
582 | #define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
---|
583 | #define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
---|
584 | #define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */ |
---|
585 | #define M8xx_SMCMR_REN (1<<0) /* Enable receiver */ |
---|
586 | |
---|
587 | /* |
---|
588 | * Event and mask registers (SMCE, SMCM) |
---|
589 | */ |
---|
590 | #define M8xx_SMCE_BRKE (1<<6) |
---|
591 | #define M8xx_SMCE_BRK (1<<4) |
---|
592 | #define M8xx_SMCE_BSY (1<<2) |
---|
593 | #define M8xx_SMCE_TX (1<<1) |
---|
594 | #define M8xx_SMCE_RX (1<<0) |
---|
595 | |
---|
596 | /* |
---|
597 | ************************************************************************* |
---|
598 | * Serial Peripheral Interface * |
---|
599 | ************************************************************************* |
---|
600 | */ |
---|
601 | typedef struct m8xxSPIparms_ { |
---|
602 | uint16_t rbase; |
---|
603 | uint16_t tbase; |
---|
604 | uint8_t rfcr; |
---|
605 | uint8_t tfcr; |
---|
606 | uint16_t mrblr; |
---|
607 | uint32_t _rstate; |
---|
608 | uint32_t _pad0; |
---|
609 | uint16_t _rbptr; |
---|
610 | uint16_t _pad1; |
---|
611 | uint32_t _pad2; |
---|
612 | uint32_t _tstate; |
---|
613 | uint32_t _pad3; |
---|
614 | uint16_t _tbptr; |
---|
615 | uint16_t _pad4; |
---|
616 | uint32_t _pad5; |
---|
617 | } m8xxSPIparms_t; |
---|
618 | |
---|
619 | /* |
---|
620 | * Mode register (SPMODE) |
---|
621 | */ |
---|
622 | #define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
---|
623 | #define M8xx_SPMODE_CI (1<<13) /* Clock invert */ |
---|
624 | #define M8xx_SPMODE_CP (1<<12) /* Clock phase */ |
---|
625 | #define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
---|
626 | #define M8xx_SPMODE_REV (1<<10) /* Reverse data */ |
---|
627 | #define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */ |
---|
628 | #define M8xx_SPMODE_EN (1<<8) /* Enable SPI */ |
---|
629 | #define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
---|
630 | #define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */ |
---|
631 | |
---|
632 | /* |
---|
633 | * Mode register (SPCOM) |
---|
634 | */ |
---|
635 | #define M8xx_SPCOM_STR (1<<7) /* Start transmit */ |
---|
636 | |
---|
637 | /* |
---|
638 | * Event and mask registers (SPIE, SPIM) |
---|
639 | */ |
---|
640 | #define M8xx_SPIE_MME (1<<5) /* Multi-master error */ |
---|
641 | #define M8xx_SPIE_TXE (1<<4) /* Tx error */ |
---|
642 | #define M8xx_SPIE_BSY (1<<2) /* Busy condition*/ |
---|
643 | #define M8xx_SPIE_TXB (1<<1) /* Tx buffer */ |
---|
644 | #define M8xx_SPIE_RXB (1<<0) /* Rx buffer */ |
---|
645 | |
---|
646 | /* |
---|
647 | ************************************************************************* |
---|
648 | * SDMA (SCC, SMC, SPI) Buffer Descriptors * |
---|
649 | ************************************************************************* |
---|
650 | */ |
---|
651 | typedef struct m8xxBufferDescriptor_ { |
---|
652 | volatile uint16_t status; |
---|
653 | uint16_t length; |
---|
654 | volatile void *buffer; |
---|
655 | } m8xxBufferDescriptor_t; |
---|
656 | |
---|
657 | /* |
---|
658 | * Bits in receive buffer descriptor status word |
---|
659 | */ |
---|
660 | #define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
661 | #define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
662 | #define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
663 | #define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ |
---|
664 | #define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
---|
665 | #define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
---|
666 | #define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ |
---|
667 | #define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
---|
668 | #define M8xx_BD_MISS (1<<8) /* Ethernet */ |
---|
669 | #define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
---|
670 | #define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
---|
671 | #define M8xx_BD_LONG (1<<5) /* Ethernet */ |
---|
672 | #define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
---|
673 | #define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */ |
---|
674 | #define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
---|
675 | #define M8xx_BD_SHORT (1<<3) /* Ethernet */ |
---|
676 | #define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
---|
677 | #define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */ |
---|
678 | #define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
679 | #define M8xx_BD_COLLISION (1<<0) /* Ethernet */ |
---|
680 | #define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ |
---|
681 | #define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ |
---|
682 | |
---|
683 | /* |
---|
684 | * Bits in transmit buffer descriptor status word |
---|
685 | * Many bits have the same meaning as those in receiver buffer descriptors. |
---|
686 | */ |
---|
687 | #define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
688 | #define M8xx_BD_PAD (1<<14) /* Ethernet */ |
---|
689 | #define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ |
---|
690 | #define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ |
---|
691 | #define M8xx_BD_DEFER (1<<9) /* Ethernet */ |
---|
692 | #define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ |
---|
693 | #define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
---|
694 | #define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
---|
695 | #define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
---|
696 | #define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
---|
697 | #define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
---|
698 | #define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
---|
699 | #define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
---|
700 | #define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */ |
---|
701 | |
---|
702 | /* |
---|
703 | ************************************************************************* |
---|
704 | * IDMA Buffer Descriptors * |
---|
705 | ************************************************************************* |
---|
706 | */ |
---|
707 | typedef struct m8xxIDMABufferDescriptor_ { |
---|
708 | uint16_t status; |
---|
709 | uint8_t dfcr; |
---|
710 | uint8_t sfcr; |
---|
711 | uint32_t length; |
---|
712 | void *source; |
---|
713 | void *destination; |
---|
714 | } m8xxIDMABufferDescriptor_t; |
---|
715 | |
---|
716 | /* |
---|
717 | ************************************************************************* |
---|
718 | * RISC Communication Processor Module Command Register (CR) * |
---|
719 | ************************************************************************* |
---|
720 | */ |
---|
721 | #define M8xx_CR_RST (1<<15) /* Reset communication processor */ |
---|
722 | #define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
---|
723 | #define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
---|
724 | #define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
---|
725 | #define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
---|
726 | #define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
---|
727 | #define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
---|
728 | #define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
---|
729 | #define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
---|
730 | #define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
---|
731 | #define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
---|
732 | #define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */ |
---|
733 | #define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
---|
734 | #define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
---|
735 | #define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
---|
736 | #define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */ |
---|
737 | #define M8xx_CR_OP_START_DSP (12<<8) /* DSP */ |
---|
738 | #define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */ |
---|
739 | |
---|
740 | #define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
---|
741 | #define M8xx_CR_CHAN_I2C (1<<4) |
---|
742 | #define M8xx_CR_CHAN_IDMA1 (1<<4) |
---|
743 | #define M8xx_CR_CHAN_SCC2 (4<<4) |
---|
744 | #define M8xx_CR_CHAN_SPI (5<<4) |
---|
745 | #define M8xx_CR_CHAN_IDMA2 (5<<4) |
---|
746 | #define M8xx_CR_CHAN_TIMER (5<<4) |
---|
747 | #define M8xx_CR_CHAN_SCC3 (8<<4) |
---|
748 | #define M8xx_CR_CHAN_SMC1 (9<<4) |
---|
749 | #define M8xx_CR_CHAN_DSP1 (9<<4) |
---|
750 | #define M8xx_CR_CHAN_SCC4 (12<<4) |
---|
751 | #define M8xx_CR_CHAN_SMC2 (13<<4) |
---|
752 | #define M8xx_CR_CHAN_DSP2 (13<<4) |
---|
753 | #define M8xx_CR_FLG (1<<0) /* Command flag */ |
---|
754 | |
---|
755 | /* |
---|
756 | ************************************************************************* |
---|
757 | * System Protection Control Register (SYPCR) * |
---|
758 | ************************************************************************* |
---|
759 | */ |
---|
760 | #define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ |
---|
761 | #define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
762 | #define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
763 | #define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
764 | #define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
765 | #define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
766 | #define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
767 | |
---|
768 | /* |
---|
769 | ************************************************************************* |
---|
770 | * PCMCIA Control Registers |
---|
771 | ************************************************************************* |
---|
772 | */ |
---|
773 | #define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4)) |
---|
774 | #define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4)) |
---|
775 | #define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4)) |
---|
776 | #define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4)) |
---|
777 | #define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4)) |
---|
778 | #define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4)) |
---|
779 | #define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4)) |
---|
780 | #define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4)) |
---|
781 | #define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4)) |
---|
782 | #define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4)) |
---|
783 | #define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4)) |
---|
784 | #define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4)) |
---|
785 | #define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4)) |
---|
786 | #define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4)) |
---|
787 | #define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4)) |
---|
788 | #define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4)) |
---|
789 | #define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4)) |
---|
790 | #define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4)) |
---|
791 | #define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4)) |
---|
792 | #define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4)) |
---|
793 | #define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4)) |
---|
794 | #define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4)) |
---|
795 | #define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4)) |
---|
796 | #define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4)) |
---|
797 | #define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4)) |
---|
798 | #define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4)) |
---|
799 | #define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4)) |
---|
800 | |
---|
801 | #define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15)) |
---|
802 | #define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19)) |
---|
803 | #define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24)) |
---|
804 | #define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19)) |
---|
805 | #define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19)) |
---|
806 | |
---|
807 | #define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28)) |
---|
808 | #define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28)) |
---|
809 | #define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28)) |
---|
810 | #define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28)) |
---|
811 | #define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28)) |
---|
812 | |
---|
813 | #define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29)) |
---|
814 | #define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29)) |
---|
815 | |
---|
816 | #define M8xx_PCMCIA_POR_WP ((1) << (31-30)) |
---|
817 | #define M8xx_PCMCIA_POR_VALID ((1) << (31-31)) |
---|
818 | |
---|
819 | #define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7)) |
---|
820 | #define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15)) |
---|
821 | #define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17)) |
---|
822 | #define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17)) |
---|
823 | #define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17)) |
---|
824 | #define M8xx_PCMCIA_PGCR_COE ((1) << (31-24)) |
---|
825 | #define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25)) |
---|
826 | |
---|
827 | #define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0)) |
---|
828 | #define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1)) |
---|
829 | #define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2)) |
---|
830 | #define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3)) |
---|
831 | #define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4)) |
---|
832 | #define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5)) |
---|
833 | #define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6)) |
---|
834 | #define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7)) |
---|
835 | #define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16)) |
---|
836 | #define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17)) |
---|
837 | #define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18)) |
---|
838 | #define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19)) |
---|
839 | #define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20)) |
---|
840 | #define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21)) |
---|
841 | #define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22)) |
---|
842 | #define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23)) |
---|
843 | |
---|
844 | |
---|
845 | #define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
846 | #define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
847 | #define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
848 | #define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
849 | #define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
850 | #define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
851 | |
---|
852 | /* |
---|
853 | ************************************************************************* |
---|
854 | * Memory Control Registers * |
---|
855 | ************************************************************************* |
---|
856 | */ |
---|
857 | #define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */ |
---|
858 | #define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */ |
---|
859 | #define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */ |
---|
860 | #define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */ |
---|
861 | #define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */ |
---|
862 | #define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */ |
---|
863 | #define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ |
---|
864 | #define M8xx_MSR_WPER (1<<7) /* Write protection error */ |
---|
865 | #define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ |
---|
866 | #define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */ |
---|
867 | #define M8xx_BR_AT(x) ((x)<<12) /* Address type */ |
---|
868 | #define M8xx_BR_PS8 (1<<10) /* 8 bit port */ |
---|
869 | #define M8xx_BR_PS16 (2<<10) /* 16 bit port */ |
---|
870 | #define M8xx_BR_PS32 (0<<10) /* 32 bit port */ |
---|
871 | #define M8xx_BR_PARE (1<<9) /* Parity checking enable */ |
---|
872 | #define M8xx_BR_WP (1<<8) /* Write protect */ |
---|
873 | #define M8xx_BR_MS_GPCM (0<<6) /* GPCM */ |
---|
874 | #define M8xx_BR_MS_UPMA (2<<6) /* UPM A */ |
---|
875 | #define M8xx_BR_MS_UPMB (3<<6) /* UPM B */ |
---|
876 | #define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
877 | |
---|
878 | #define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */ |
---|
879 | #define M8xx_MEMC_OR_64K 0xffff0000 |
---|
880 | #define M8xx_MEMC_OR_128K 0xfffe0000 |
---|
881 | #define M8xx_MEMC_OR_256K 0xfffc0000 |
---|
882 | #define M8xx_MEMC_OR_512K 0xfff80000 |
---|
883 | #define M8xx_MEMC_OR_1M 0xfff00000 |
---|
884 | #define M8xx_MEMC_OR_2M 0xffe00000 |
---|
885 | #define M8xx_MEMC_OR_4M 0xffc00000 |
---|
886 | #define M8xx_MEMC_OR_8M 0xff800000 |
---|
887 | #define M8xx_MEMC_OR_16M 0xff000000 |
---|
888 | #define M8xx_MEMC_OR_32M 0xfe000000 |
---|
889 | #define M8xx_MEMC_OR_64M 0xfc000000 |
---|
890 | #define M8xx_MEMC_OR_128 0xf8000000 |
---|
891 | #define M8xx_MEMC_OR_256M 0xf0000000 |
---|
892 | #define M8xx_MEMC_OR_512M 0xe0000000 |
---|
893 | #define M8xx_MEMC_OR_1G 0xc0000000 |
---|
894 | #define M8xx_MEMC_OR_2G 0x80000000 |
---|
895 | #define M8xx_MEMC_OR_4G 0x00000000 |
---|
896 | #define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ |
---|
897 | #define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ |
---|
898 | #define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ |
---|
899 | #define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ |
---|
900 | #define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ |
---|
901 | #define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ |
---|
902 | #define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */ |
---|
903 | #define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ |
---|
904 | #define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */ |
---|
905 | #define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ |
---|
906 | #define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ |
---|
907 | |
---|
908 | /* |
---|
909 | ************************************************************************* |
---|
910 | * UPM Registers (MxMR) * |
---|
911 | ************************************************************************* |
---|
912 | */ |
---|
913 | #define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ |
---|
914 | #define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ |
---|
915 | #define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ |
---|
916 | #define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ |
---|
917 | #define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ |
---|
918 | #define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ |
---|
919 | #define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ |
---|
920 | #define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ |
---|
921 | /* |
---|
922 | ************************************************************************* |
---|
923 | * Memory Command Register (MCR) * |
---|
924 | ************************************************************************* |
---|
925 | */ |
---|
926 | #define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */ |
---|
927 | #define M8xx_MEMC_MCR_READ (1<<30) /* READ command */ |
---|
928 | #define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */ |
---|
929 | #define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ |
---|
930 | #define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ |
---|
931 | #define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ |
---|
932 | #define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ |
---|
933 | #define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */ |
---|
934 | |
---|
935 | |
---|
936 | |
---|
937 | /* |
---|
938 | ************************************************************************* |
---|
939 | * SI Mode Register (SIMODE) * |
---|
940 | ************************************************************************* |
---|
941 | */ |
---|
942 | #define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
---|
943 | #define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
---|
944 | #define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
---|
945 | #define M8xx_SI_SMC2_BRG2 (1<<28) |
---|
946 | #define M8xx_SI_SMC2_BRG3 (2<<28) |
---|
947 | #define M8xx_SI_SMC2_BRG4 (3<<28) |
---|
948 | #define M8xx_SI_SMC2_CLK5 (0<<28) |
---|
949 | #define M8xx_SI_SMC2_CLK6 (1<<28) |
---|
950 | #define M8xx_SI_SMC2_CLK7 (2<<28) |
---|
951 | #define M8xx_SI_SMC2_CLK8 (3<<28) |
---|
952 | #define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
---|
953 | #define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
---|
954 | #define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
---|
955 | #define M8xx_SI_SMC1_BRG2 (1<<12) |
---|
956 | #define M8xx_SI_SMC1_BRG3 (2<<12) |
---|
957 | #define M8xx_SI_SMC1_BRG4 (3<<12) |
---|
958 | #define M8xx_SI_SMC1_CLK1 (0<<12) |
---|
959 | #define M8xx_SI_SMC1_CLK2 (1<<12) |
---|
960 | #define M8xx_SI_SMC1_CLK3 (2<<12) |
---|
961 | #define M8xx_SI_SMC1_CLK4 (3<<12) |
---|
962 | |
---|
963 | /* |
---|
964 | ************************************************************************* |
---|
965 | * SDMA Configuration Register (SDCR) * |
---|
966 | ************************************************************************* |
---|
967 | */ |
---|
968 | #define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ |
---|
969 | #define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ |
---|
970 | |
---|
971 | /* |
---|
972 | ************************************************************************* |
---|
973 | * SDMA Status Register (SDSR) * |
---|
974 | ************************************************************************* |
---|
975 | */ |
---|
976 | #define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */ |
---|
977 | #define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ |
---|
978 | #define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ |
---|
979 | |
---|
980 | /* |
---|
981 | ************************************************************************* |
---|
982 | * Baud (sic) Rate Generators * |
---|
983 | ************************************************************************* |
---|
984 | */ |
---|
985 | #define M8xx_BRG_RST (1<<17) /* Reset generator */ |
---|
986 | #define M8xx_BRG_EN (1<<16) /* Enable generator */ |
---|
987 | #define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
---|
988 | #define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
---|
989 | #define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
---|
990 | #define M8xx_BRG_ATB (1<<13) /* Autobaud */ |
---|
991 | #define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */ |
---|
992 | #define M8xx_BRG_57600 (32<<1) |
---|
993 | #define M8xx_BRG_38400 (64<<1) |
---|
994 | #define M8xx_BRG_19200 (129<<1) |
---|
995 | #define M8xx_BRG_9600 (259<<1) |
---|
996 | #define M8xx_BRG_4800 (520<<1) |
---|
997 | #define M8xx_BRG_2400 (1040<<1) |
---|
998 | #define M8xx_BRG_1200 (2082<<1) |
---|
999 | #define M8xx_BRG_600 ((259<<1) | 1) |
---|
1000 | #define M8xx_BRG_300 ((520<<1) | 1) |
---|
1001 | #define M8xx_BRG_150 ((1040<<1) | 1) |
---|
1002 | #define M8xx_BRG_75 ((2080<<1) | 1) |
---|
1003 | |
---|
1004 | #define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ |
---|
1005 | #define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ |
---|
1006 | #define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ |
---|
1007 | #define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ |
---|
1008 | #define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ |
---|
1009 | #define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ |
---|
1010 | #define M8xx_TGCR_STP1 (1<<1) /* Stop timer */ |
---|
1011 | #define M8xx_TGCR_STP2 (1<<5) /* Stop timer */ |
---|
1012 | #define M8xx_TGCR_STP3 (1<<9) /* Stop timer */ |
---|
1013 | #define M8xx_TGCR_STP4 (1<<13) /* Stop timer */ |
---|
1014 | #define M8xx_TGCR_RST1 (1<<0) /* Enable timer */ |
---|
1015 | #define M8xx_TGCR_RST2 (1<<4) /* Enable timer */ |
---|
1016 | #define M8xx_TGCR_RST3 (1<<8) /* Enable timer */ |
---|
1017 | #define M8xx_TGCR_RST4 (1<<12) /* Enable timer */ |
---|
1018 | #define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ |
---|
1019 | #define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ |
---|
1020 | |
---|
1021 | #define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */ |
---|
1022 | #define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */ |
---|
1023 | #define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */ |
---|
1024 | #define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */ |
---|
1025 | #define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ |
---|
1026 | #define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */ |
---|
1027 | #define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */ |
---|
1028 | #define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ |
---|
1029 | #define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ |
---|
1030 | #define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ |
---|
1031 | #define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */ |
---|
1032 | |
---|
1033 | #define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ |
---|
1034 | #define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */ |
---|
1035 | #define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */ |
---|
1036 | #define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ |
---|
1037 | #define M8xx_PISCR_PTE (1<<0) /* PIT enable */ |
---|
1038 | |
---|
1039 | #define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ |
---|
1040 | #define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ |
---|
1041 | #define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ |
---|
1042 | #define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ |
---|
1043 | #define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ |
---|
1044 | #define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ |
---|
1045 | #define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */ |
---|
1046 | |
---|
1047 | #define M8xx_SIMASK_IRM0 (1<<31) |
---|
1048 | #define M8xx_SIMASK_LVM0 (1<<30) |
---|
1049 | #define M8xx_SIMASK_IRM1 (1<<29) |
---|
1050 | #define M8xx_SIMASK_LVM1 (1<<28) |
---|
1051 | #define M8xx_SIMASK_IRM2 (1<<27) |
---|
1052 | #define M8xx_SIMASK_LVM2 (1<<26) |
---|
1053 | #define M8xx_SIMASK_IRM3 (1<<25) |
---|
1054 | #define M8xx_SIMASK_LVM3 (1<<24) |
---|
1055 | #define M8xx_SIMASK_IRM4 (1<<23) |
---|
1056 | #define M8xx_SIMASK_LVM4 (1<<22) |
---|
1057 | #define M8xx_SIMASK_IRM5 (1<<21) |
---|
1058 | #define M8xx_SIMASK_LVM5 (1<<20) |
---|
1059 | #define M8xx_SIMASK_IRM6 (1<<19) |
---|
1060 | #define M8xx_SIMASK_LVM6 (1<<18) |
---|
1061 | #define M8xx_SIMASK_IRM7 (1<<17) |
---|
1062 | #define M8xx_SIMASK_LVM7 (1<<16) |
---|
1063 | |
---|
1064 | #define M8xx_SIUMCR_EARB (1<<31) |
---|
1065 | #define M8xx_SIUMCR_EARP0 (0<<28) |
---|
1066 | #define M8xx_SIUMCR_EARP1 (1<<28) |
---|
1067 | #define M8xx_SIUMCR_EARP2 (2<<28) |
---|
1068 | #define M8xx_SIUMCR_EARP3 (3<<28) |
---|
1069 | #define M8xx_SIUMCR_EARP4 (4<<28) |
---|
1070 | #define M8xx_SIUMCR_EARP5 (5<<28) |
---|
1071 | #define M8xx_SIUMCR_EARP6 (6<<28) |
---|
1072 | #define M8xx_SIUMCR_EARP7 (7<<28) |
---|
1073 | #define M8xx_SIUMCR_DSHW (1<<23) |
---|
1074 | #define M8xx_SIUMCR_DBGC0 (0<<21) |
---|
1075 | #define M8xx_SIUMCR_DBGC1 (1<<21) |
---|
1076 | #define M8xx_SIUMCR_DBGC2 (2<<21) |
---|
1077 | #define M8xx_SIUMCR_DBGC3 (3<<21) |
---|
1078 | #define M8xx_SIUMCR_DBPC0 (0<<19) |
---|
1079 | #define M8xx_SIUMCR_DBPC1 (1<<19) |
---|
1080 | #define M8xx_SIUMCR_DBPC2 (2<<19) |
---|
1081 | #define M8xx_SIUMCR_DBPC3 (3<<19) |
---|
1082 | #define M8xx_SIUMCR_FRC (1<<17) |
---|
1083 | #define M8xx_SIUMCR_DLK (1<<16) |
---|
1084 | #define M8xx_SIUMCR_PNCS (1<<15) |
---|
1085 | #define M8xx_SIUMCR_OPAR (1<<14) |
---|
1086 | #define M8xx_SIUMCR_DPC (1<<13) |
---|
1087 | #define M8xx_SIUMCR_MPRE (1<<12) |
---|
1088 | #define M8xx_SIUMCR_MLRC0 (0<<10) |
---|
1089 | #define M8xx_SIUMCR_MLRC1 (1<<10) |
---|
1090 | #define M8xx_SIUMCR_MLRC2 (2<<10) |
---|
1091 | #define M8xx_SIUMCR_MLRC3 (3<<10) |
---|
1092 | #define M8xx_SIUMCR_AEME (1<<9) |
---|
1093 | #define M8xx_SIUMCR_SEME (1<<8) |
---|
1094 | #define M8xx_SIUMCR_BSC (1<<7) |
---|
1095 | #define M8xx_SIUMCR_GB5E (1<<6) |
---|
1096 | #define M8xx_SIUMCR_B2DD (1<<5) |
---|
1097 | #define M8xx_SIUMCR_B3DD (1<<4) |
---|
1098 | |
---|
1099 | /* |
---|
1100 | * Value to write to a key register to unlock the corresponding SIU register |
---|
1101 | */ |
---|
1102 | #define M8xx_UNLOCK_KEY 0x55CCAA33 |
---|
1103 | |
---|
1104 | /* |
---|
1105 | ************************************************************************* |
---|
1106 | * MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * |
---|
1107 | ************************************************************************* |
---|
1108 | */ |
---|
1109 | typedef struct m8xx_ { |
---|
1110 | |
---|
1111 | /* |
---|
1112 | * SIU Block |
---|
1113 | */ |
---|
1114 | uint32_t siumcr; |
---|
1115 | uint32_t sypcr; |
---|
1116 | #if defined(mpc860) |
---|
1117 | uint32_t swt; |
---|
1118 | #elif defined(mpc821) |
---|
1119 | uint32_t _pad70; |
---|
1120 | #endif |
---|
1121 | uint16_t _pad0; |
---|
1122 | uint16_t swsr; |
---|
1123 | uint32_t sipend; |
---|
1124 | uint32_t simask; |
---|
1125 | uint32_t siel; |
---|
1126 | uint32_t sivec; |
---|
1127 | uint32_t tesr; |
---|
1128 | uint32_t _pad1[3]; |
---|
1129 | uint32_t sdcr; |
---|
1130 | uint8_t _pad2[0x80-0x34]; |
---|
1131 | |
---|
1132 | /* |
---|
1133 | * PCMCIA Block |
---|
1134 | */ |
---|
1135 | uint32_t pbr0; |
---|
1136 | uint32_t por0; |
---|
1137 | uint32_t pbr1; |
---|
1138 | uint32_t por1; |
---|
1139 | uint32_t pbr2; |
---|
1140 | uint32_t por2; |
---|
1141 | uint32_t pbr3; |
---|
1142 | uint32_t por3; |
---|
1143 | uint32_t pbr4; |
---|
1144 | uint32_t por4; |
---|
1145 | uint32_t pbr5; |
---|
1146 | uint32_t por5; |
---|
1147 | uint32_t pbr6; |
---|
1148 | uint32_t por6; |
---|
1149 | uint32_t pbr7; |
---|
1150 | uint32_t por7; |
---|
1151 | uint8_t _pad3[0xe0-0xc0]; |
---|
1152 | uint32_t pgcra; |
---|
1153 | uint32_t pgcrb; |
---|
1154 | uint32_t pscr; |
---|
1155 | uint32_t _pad4; |
---|
1156 | uint32_t pipr; |
---|
1157 | uint32_t _pad5; |
---|
1158 | uint32_t per; |
---|
1159 | uint32_t _pad6; |
---|
1160 | |
---|
1161 | /* |
---|
1162 | * MEMC Block |
---|
1163 | */ |
---|
1164 | m8xxMEMCRegisters_t memc[8]; |
---|
1165 | uint8_t _pad7[0x164-0x140]; |
---|
1166 | uint32_t mar; |
---|
1167 | uint32_t mcr; |
---|
1168 | uint32_t _pad8; |
---|
1169 | uint32_t mamr; |
---|
1170 | uint32_t mbmr; |
---|
1171 | uint16_t mstat; |
---|
1172 | uint16_t mptpr; |
---|
1173 | uint32_t mdr; |
---|
1174 | uint8_t _pad9[0x200-0x180]; |
---|
1175 | |
---|
1176 | /* |
---|
1177 | * System integration timers |
---|
1178 | */ |
---|
1179 | uint16_t tbscr; |
---|
1180 | uint16_t _pad10; |
---|
1181 | uint32_t tbreff0; |
---|
1182 | uint32_t tbreff1; |
---|
1183 | uint8_t _pad11[0x220-0x20c]; |
---|
1184 | uint16_t rtcsc; |
---|
1185 | uint16_t _pad12; |
---|
1186 | uint32_t rtc; |
---|
1187 | uint32_t rtsec; |
---|
1188 | uint32_t rtcal; |
---|
1189 | uint32_t _pad13[4]; |
---|
1190 | uint16_t piscr; |
---|
1191 | uint16_t _pad14; |
---|
1192 | uint16_t pitc; |
---|
1193 | uint16_t _pad_14_1; |
---|
1194 | uint16_t pitr; |
---|
1195 | uint16_t _pad_14_2; |
---|
1196 | uint8_t _pad15[0x280-0x24c]; |
---|
1197 | |
---|
1198 | |
---|
1199 | /* |
---|
1200 | * Clocks and Reset |
---|
1201 | */ |
---|
1202 | uint32_t sccr; |
---|
1203 | uint32_t plprcr; |
---|
1204 | uint32_t rsr; |
---|
1205 | uint8_t _pad16[0x300-0x28c]; |
---|
1206 | |
---|
1207 | |
---|
1208 | /* |
---|
1209 | * System integration timers keys |
---|
1210 | */ |
---|
1211 | uint32_t tbscrk; |
---|
1212 | uint32_t tbreff0k; |
---|
1213 | uint32_t tbreff1k; |
---|
1214 | uint32_t tbk; |
---|
1215 | uint32_t _pad17[4]; |
---|
1216 | uint32_t rtcsk; |
---|
1217 | uint32_t rtck; |
---|
1218 | uint32_t rtseck; |
---|
1219 | uint32_t rtcalk; |
---|
1220 | uint32_t _pad18[4]; |
---|
1221 | uint32_t piscrk; |
---|
1222 | uint32_t pitck; |
---|
1223 | uint8_t _pad19[0x380-0x348]; |
---|
1224 | |
---|
1225 | /* |
---|
1226 | * Clocks and Reset Keys |
---|
1227 | */ |
---|
1228 | uint32_t sccrk; |
---|
1229 | uint32_t plprck; |
---|
1230 | uint32_t rsrk; |
---|
1231 | uint8_t _pad20[0x400-0x38c]; |
---|
1232 | uint8_t _pad21[0x800-0x400]; |
---|
1233 | uint8_t _pad22[0x860-0x800]; |
---|
1234 | |
---|
1235 | |
---|
1236 | /* |
---|
1237 | * I2C |
---|
1238 | */ |
---|
1239 | uint8_t i2mod; |
---|
1240 | uint8_t _pad23[3]; |
---|
1241 | uint8_t i2add; |
---|
1242 | uint8_t _pad24[3]; |
---|
1243 | uint8_t i2brg; |
---|
1244 | uint8_t _pad25[3]; |
---|
1245 | uint8_t i2com; |
---|
1246 | uint8_t _pad26[3]; |
---|
1247 | uint8_t i2cer; |
---|
1248 | uint8_t _pad27[3]; |
---|
1249 | uint8_t i2cmr; |
---|
1250 | uint8_t _pad28[0x900-0x875]; |
---|
1251 | |
---|
1252 | /* |
---|
1253 | * DMA Block |
---|
1254 | */ |
---|
1255 | uint32_t _pad29; |
---|
1256 | uint32_t sdar; |
---|
1257 | uint8_t sdsr; |
---|
1258 | uint8_t _pad30[3]; |
---|
1259 | uint8_t sdmr; |
---|
1260 | uint8_t _pad31[3]; |
---|
1261 | uint8_t idsr1; |
---|
1262 | uint8_t _pad32[3]; |
---|
1263 | uint8_t idmr1; |
---|
1264 | uint8_t _pad33[3]; |
---|
1265 | uint8_t idsr2; |
---|
1266 | uint8_t _pad34[3]; |
---|
1267 | uint8_t idmr2; |
---|
1268 | uint8_t _pad35[0x930-0x91d]; |
---|
1269 | |
---|
1270 | /* |
---|
1271 | * CPM Interrupt Control Block |
---|
1272 | */ |
---|
1273 | uint16_t civr; |
---|
1274 | uint8_t _pad36[14]; |
---|
1275 | uint32_t cicr; |
---|
1276 | uint32_t cipr; |
---|
1277 | uint32_t cimr; |
---|
1278 | uint32_t cisr; |
---|
1279 | |
---|
1280 | /* |
---|
1281 | * I/O Port Block |
---|
1282 | */ |
---|
1283 | uint16_t padir; |
---|
1284 | uint16_t papar; |
---|
1285 | uint16_t paodr; |
---|
1286 | uint16_t padat; |
---|
1287 | uint8_t _pad37[8]; |
---|
1288 | uint16_t pcdir; |
---|
1289 | uint16_t pcpar; |
---|
1290 | uint16_t pcso; |
---|
1291 | uint16_t pcdat; |
---|
1292 | uint16_t pcint; |
---|
1293 | uint8_t _pad39[6]; |
---|
1294 | uint16_t pddir; |
---|
1295 | uint16_t pdpar; |
---|
1296 | uint16_t _pad40; |
---|
1297 | uint16_t pddat; |
---|
1298 | uint8_t _pad41[8]; |
---|
1299 | |
---|
1300 | /* |
---|
1301 | * CPM Timers Block |
---|
1302 | */ |
---|
1303 | uint16_t tgcr; |
---|
1304 | uint8_t _pad42[14]; |
---|
1305 | uint16_t tmr1; |
---|
1306 | uint16_t tmr2; |
---|
1307 | uint16_t trr1; |
---|
1308 | uint16_t trr2; |
---|
1309 | uint16_t tcr1; |
---|
1310 | uint16_t tcr2; |
---|
1311 | uint16_t tcn1; |
---|
1312 | uint16_t tcn2; |
---|
1313 | uint16_t tmr3; |
---|
1314 | uint16_t tmr4; |
---|
1315 | uint16_t trr3; |
---|
1316 | uint16_t trr4; |
---|
1317 | uint16_t tcr3; |
---|
1318 | uint16_t tcr4; |
---|
1319 | uint16_t tcn3; |
---|
1320 | uint16_t tcn4; |
---|
1321 | uint16_t ter1; |
---|
1322 | uint16_t ter2; |
---|
1323 | uint16_t ter3; |
---|
1324 | uint16_t ter4; |
---|
1325 | uint8_t _pad43[8]; |
---|
1326 | |
---|
1327 | /* |
---|
1328 | * CPM Block |
---|
1329 | */ |
---|
1330 | uint16_t cpcr; |
---|
1331 | uint16_t _pad44; |
---|
1332 | uint16_t rccr; |
---|
1333 | uint8_t _pad45; |
---|
1334 | uint8_t rmds; |
---|
1335 | uint32_t rmdr; |
---|
1336 | uint16_t rctr1; |
---|
1337 | uint16_t rctr2; |
---|
1338 | uint16_t rctr3; |
---|
1339 | uint16_t rctr4; |
---|
1340 | uint16_t _pad46; |
---|
1341 | uint16_t rter; |
---|
1342 | uint16_t _pad47; |
---|
1343 | uint16_t rtmr; |
---|
1344 | uint8_t _pad48[0x9f0-0x9dc]; |
---|
1345 | |
---|
1346 | /* |
---|
1347 | * BRG Block |
---|
1348 | */ |
---|
1349 | uint32_t brgc1; |
---|
1350 | uint32_t brgc2; |
---|
1351 | uint32_t brgc3; |
---|
1352 | uint32_t brgc4; |
---|
1353 | |
---|
1354 | /* |
---|
1355 | * SCC Block |
---|
1356 | */ |
---|
1357 | m8xxSCCRegisters_t scc1; |
---|
1358 | m8xxSCCRegisters_t scc2; |
---|
1359 | #if defined(mpc860) |
---|
1360 | m8xxSCCRegisters_t scc3; |
---|
1361 | m8xxSCCRegisters_t scc4; |
---|
1362 | #elif defined(mpc821) |
---|
1363 | uint8_t _pad72[0xa80-0xa40]; |
---|
1364 | #endif |
---|
1365 | |
---|
1366 | /* |
---|
1367 | * SMC Block |
---|
1368 | */ |
---|
1369 | m8xxSMCRegisters_t smc1; |
---|
1370 | m8xxSMCRegisters_t smc2; |
---|
1371 | |
---|
1372 | /* |
---|
1373 | * SPI Block |
---|
1374 | */ |
---|
1375 | uint16_t spmode; |
---|
1376 | uint16_t _pad49[2]; |
---|
1377 | uint8_t spie; |
---|
1378 | uint8_t _pad50; |
---|
1379 | uint16_t _pad51; |
---|
1380 | uint8_t spim; |
---|
1381 | uint8_t _pad52[2]; |
---|
1382 | uint8_t spcom; |
---|
1383 | uint16_t _pad53[2]; |
---|
1384 | |
---|
1385 | /* |
---|
1386 | * PIP Block |
---|
1387 | */ |
---|
1388 | uint16_t pipc; |
---|
1389 | uint16_t _pad54; |
---|
1390 | uint16_t ptpr; |
---|
1391 | uint32_t pbdir; |
---|
1392 | uint32_t pbpar; |
---|
1393 | uint16_t _pad55; |
---|
1394 | uint16_t pbodr; |
---|
1395 | uint32_t pbdat; |
---|
1396 | uint32_t _pad56[6]; |
---|
1397 | |
---|
1398 | /* |
---|
1399 | * SI Block |
---|
1400 | */ |
---|
1401 | uint32_t simode; |
---|
1402 | uint8_t sigmr; |
---|
1403 | uint8_t _pad57; |
---|
1404 | uint8_t sistr; |
---|
1405 | uint8_t sicmr; |
---|
1406 | uint32_t _pad58; |
---|
1407 | uint32_t sicr; |
---|
1408 | uint16_t sirp[2]; |
---|
1409 | uint32_t _pad59[3]; |
---|
1410 | uint8_t _pad60[0xc00-0xb00]; |
---|
1411 | uint8_t siram[512]; |
---|
1412 | #if defined(mpc860) |
---|
1413 | /* |
---|
1414 | * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC) |
---|
1415 | */ |
---|
1416 | m8xxFECRegisters_t fec; |
---|
1417 | #elif defined(mpc821) |
---|
1418 | uint8_t lcdram[512]; |
---|
1419 | #endif |
---|
1420 | uint8_t _pad62[0x2000-0x1000]; |
---|
1421 | |
---|
1422 | /* |
---|
1423 | * Dual-port RAM |
---|
1424 | */ |
---|
1425 | uint8_t dpram0[0x200]; /* BD/DATA/UCODE */ |
---|
1426 | uint8_t dpram1[0x200]; /* BD/DATA/UCODE */ |
---|
1427 | uint8_t dpram2[0x400]; /* BD/DATA/UCODE */ |
---|
1428 | uint8_t dpram3[0x600]; /* BD/DATA*/ |
---|
1429 | uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ |
---|
1430 | uint8_t _pad63[0x3c00-0x3000]; |
---|
1431 | |
---|
1432 | /* When using SCC1 for ethernet, we lose the use of I2C since |
---|
1433 | * their parameters would overlap. Motorola has a microcode |
---|
1434 | * patch to move parameters around so that both can be used |
---|
1435 | * together. It is available on their web site somewhere |
---|
1436 | * under http://www.mot.com/mpc8xx. If ethernet is used on |
---|
1437 | * one (or more) of the other SCCs, then other CPM features |
---|
1438 | * will be unavailable: |
---|
1439 | * SCC2 -> lose SPI |
---|
1440 | * SCC3 -> lose SMC1 |
---|
1441 | * SCC4 -> lose SMC2 |
---|
1442 | * However, Ethernet only works on SCC1 on the 8xx. |
---|
1443 | */ |
---|
1444 | m8xxSCCENparms_t scc1p; |
---|
1445 | uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)]; |
---|
1446 | m8xxMiscParms_t miscp; |
---|
1447 | uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; |
---|
1448 | m8xxIDMAparms_t idma1p; |
---|
1449 | uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; |
---|
1450 | |
---|
1451 | m8xxSCCparms_t scc2p; |
---|
1452 | uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; |
---|
1453 | m8xxSPIparms_t spip; |
---|
1454 | uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)]; |
---|
1455 | m8xxTimerParms_t tmp; |
---|
1456 | uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; |
---|
1457 | m8xxIDMAparms_t idma2p; |
---|
1458 | uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; |
---|
1459 | |
---|
1460 | m8xxSCCparms_t scc3p; /* Not available on MPC821 */ |
---|
1461 | uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; |
---|
1462 | m8xxSMCparms_t smc1p; |
---|
1463 | uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; |
---|
1464 | m8xxDSPparms_t dsp1p; |
---|
1465 | uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; |
---|
1466 | |
---|
1467 | m8xxSCCparms_t scc4p; /* Not available on MPC821 */ |
---|
1468 | uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; |
---|
1469 | m8xxSMCparms_t smc2p; |
---|
1470 | uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)]; |
---|
1471 | m8xxDSPparms_t dsp2p; |
---|
1472 | uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)]; |
---|
1473 | } m8xx_t; |
---|
1474 | |
---|
1475 | extern volatile m8xx_t m8xx; |
---|
1476 | |
---|
1477 | #ifdef __cplusplus |
---|
1478 | } |
---|
1479 | #endif |
---|
1480 | |
---|
1481 | #endif /* ASM */ |
---|
1482 | |
---|
1483 | #endif /* _MPC8XX_H */ |
---|