1 | /* |
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2 | ************************************************************************** |
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3 | ************************************************************************** |
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4 | ** ** |
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5 | ** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR ** |
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6 | ** ** |
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7 | ** HARDWARE DECLARATIONS ** |
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8 | ** ** |
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9 | ** ** |
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10 | ** Submitted By: ** |
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11 | ** ** |
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12 | ** W. Eric Norum ** |
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13 | ** Saskatchewan Accelerator Laboratory ** |
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14 | ** University of Saskatchewan ** |
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15 | ** 107 North Road ** |
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16 | ** Saskatoon, Saskatchewan, CANADA ** |
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17 | ** S7N 5C6 ** |
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18 | ** ** |
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19 | ** eric@skatter.usask.ca ** |
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20 | ** ** |
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21 | ** Modified for use with the MPC860 (original code was for MC68360) ** |
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22 | ** by ** |
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23 | ** Jay Monkman ** |
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24 | ** Frasca International, Inc. ** |
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25 | ** 906 E. Airport Rd. ** |
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26 | ** Urbana, IL, 61801 ** |
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27 | ** ** |
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28 | ** jmonkman@frasca.com ** |
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29 | ** ** |
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30 | ** Modified further for use with the MPC821 by: ** |
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31 | ** Andrew Bray <andy@chaos.org.uk> ** |
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32 | ** ** |
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33 | ** With some corrections/additions by: ** |
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34 | ** Darlene A. Stewart and ** |
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35 | ** Charles-Antoine Gauthier ** |
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36 | ** Institute for Information Technology ** |
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37 | ** National Research Council of Canada ** |
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38 | ** Ottawa, ON K1A 0R6 ** |
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39 | ** ** |
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40 | ** Darlene.Stewart@iit.nrc.ca ** |
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41 | ** charles.gauthier@iit.nrc.ca ** |
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42 | ** ** |
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43 | ** Corrections/additions: ** |
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44 | ** Copyright (c) 1999, National Research Council of Canada ** |
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45 | ************************************************************************** |
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46 | ************************************************************************** |
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47 | */ |
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48 | |
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49 | #ifndef __MPC8xx_h |
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50 | #define __MPC8xx_h |
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51 | |
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52 | #ifndef ASM |
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53 | |
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54 | #ifdef __cplusplus |
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55 | extern "C" { |
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56 | #endif |
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57 | |
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58 | /* |
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59 | * Macros for accessing Special Purpose Registers (SPRs) |
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60 | */ |
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61 | #define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) |
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62 | #define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) ) |
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63 | |
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64 | #define _isync __asm__ volatile ("isync\n"::) |
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65 | |
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66 | /* |
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67 | * Core Registers (SPRs) |
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68 | */ |
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69 | #define M8xx_DEC 22 /* Decrementer Register */ |
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70 | #define M8xx_DER 149 /* Debug Enable Register */ |
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71 | #define M8xx_ICTRL 158 /* Instruction Support Control Register */ |
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72 | #define M8xx_TBL_WR 284 /* Timebase Lower Write Register */ |
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73 | #define M8xx_TBU_WR 285 /* Timebase Upper Write Register */ |
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74 | #define M8xx_IMMR 638 /* Internal Memory Map Register */ |
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75 | |
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76 | /* |
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77 | * Cache Control Registers (SPRs) |
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78 | */ |
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79 | #define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */ |
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80 | #define M8xx_DC_CST 568 /* Data Cache Control and Status Register */ |
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81 | #define M8xx_IC_ADR 561 /* Instruction Cache Address Register */ |
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82 | #define M8xx_DC_ADR 569 /* Data Cache Address Register */ |
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83 | #define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */ |
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84 | #define M8xx_DC_DAT 570 /* Data Cache Data Port Register */ |
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85 | |
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86 | /* |
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87 | * MMU Registers (SPRs) |
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88 | */ |
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89 | /* Control Registers */ |
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90 | #define M8xx_MI_CTR 784 /* IMMU Control Register */ |
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91 | #define M8xx_MD_CTR 792 /* DMMU Control Register */ |
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92 | /* TLB Source Registers */ |
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93 | #define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */ |
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94 | #define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */ |
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95 | #define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */ |
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96 | #define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */ |
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97 | #define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */ |
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98 | #define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */ |
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99 | /* Tablewalk Assist Registers */ |
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100 | #define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */ |
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101 | /* Protection Registers */ |
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102 | #define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */ |
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103 | #define M8xx_MI_AP 786 /* IMMU Access Protection Register */ |
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104 | #define M8xx_MD_AP 794 /* DMMU Access Protection Register */ |
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105 | /* Scratch Register */ |
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106 | #define M8xx_M_TW 799 /* MMU Tablewalk Special Register */ |
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107 | /* Debug Registers */ |
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108 | #define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */ |
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109 | #define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */ |
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110 | #define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */ |
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111 | #define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */ |
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112 | #define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */ |
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113 | #define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */ |
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114 | |
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115 | #define M8xx_MI_CTR_GPM (1<<31) |
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116 | #define M8xx_MI_CTR_PPM (1<<30) |
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117 | #define M8xx_MI_CTR_CIDEF (1<<29) |
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118 | #define M8xx_MI_CTR_RSV4I (1<<27) |
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119 | #define M8xx_MI_CTR_PPCS (1<<25) |
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120 | #define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */ |
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121 | |
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122 | #define M8xx_MD_CTR_GPM (1<<31) |
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123 | #define M8xx_MD_CTR_PPM (1<<30) |
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124 | #define M8xx_MD_CTR_CIDEF (1<<29) |
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125 | #define M8xx_MD_CTR_WTDEF (1<<28) |
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126 | #define M8xx_MD_CTR_RSV4D (1<<27) |
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127 | #define M8xx_MD_CTR_TWAM (1<<26) |
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128 | #define M8xx_MD_CTR_PPCS (1<<25) |
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129 | #define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */ |
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130 | |
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131 | #define M8xx_MI_EPN_VALID (1<<9) |
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132 | |
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133 | #define M8xx_MD_EPN_VALID (1<<9) |
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134 | |
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135 | #define M8xx_MI_TWC_G (1<<4) |
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136 | #define M8xx_MI_TWC_PSS (0<<2) |
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137 | #define M8xx_MI_TWC_PS512 (1<<2) |
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138 | #define M8xx_MI_TWC_PS8 (3<<2) |
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139 | #define M8xx_MI_TWC_VALID (1) |
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140 | |
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141 | #define M8xx_MD_TWC_G (1<<4) |
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142 | #define M8xx_MD_TWC_PSS (0<<2) |
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143 | #define M8xx_MD_TWC_PS512 (1<<2) |
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144 | #define M8xx_MD_TWC_PS8 (3<<2) |
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145 | #define M8xx_MD_TWC_WT (1<<1) |
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146 | #define M8xx_MD_TWC_VALID (1) |
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147 | |
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148 | #define M8xx_MI_RPN_F (0xf<<4) |
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149 | #define M8xx_MI_RPN_16K (1<<3) |
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150 | #define M8xx_MI_RPN_SHARED (1<<2) |
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151 | #define M8xx_MI_RPN_CI (1<<1) |
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152 | #define M8xx_MI_RPN_VALID (1) |
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153 | |
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154 | #define M8xx_MD_RPN_CHANGE (1<<8) |
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155 | #define M8xx_MD_RPN_F (0xf<<4) |
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156 | #define M8xx_MD_RPN_16K (1<<3) |
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157 | #define M8xx_MD_RPN_SHARED (1<<2) |
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158 | #define M8xx_MD_RPN_CI (1<<1) |
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159 | #define M8xx_MD_RPN_VALID (1) |
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160 | |
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161 | #define M8xx_MI_AP_Kp (1) |
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162 | |
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163 | #define M8xx_MD_AP_Kp (1) |
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164 | |
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165 | #define M8xx_CACHE_CMD_SFWT (0x1<<24) |
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166 | #define M8xx_CACHE_CMD_ENABLE (0x2<<24) |
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167 | #define M8xx_CACHE_CMD_CFWT (0x3<<24) |
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168 | #define M8xx_CACHE_CMD_DISABLE (0x4<<24) |
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169 | #define M8xx_CACHE_CMD_STLES (0x5<<24) |
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170 | #define M8xx_CACHE_CMD_LLCB (0x6<<24) |
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171 | #define M8xx_CACHE_CMD_CLES (0x7<<24) |
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172 | #define M8xx_CACHE_CMD_UNLOCK (0x8<<24) |
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173 | #define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24) |
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174 | #define M8xx_CACHE_CMD_INVALIDATE (0xc<<24) |
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175 | #define M8xx_CACHE_CMD_FLUSH (0xe<<24) |
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176 | |
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177 | /* |
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178 | ************************************************************************* |
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179 | * REGISTER SUBBLOCKS * |
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180 | ************************************************************************* |
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181 | */ |
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182 | |
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183 | /* |
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184 | * Memory controller registers |
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185 | */ |
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186 | typedef struct m8xxMEMCRegisters_ { |
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187 | rtems_unsigned32 _br; |
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188 | rtems_unsigned32 _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ |
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189 | } m8xxMEMCRegisters_t; |
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190 | |
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191 | /* |
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192 | * Serial Communications Controller registers |
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193 | */ |
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194 | typedef struct m8xxSCCRegisters_ { |
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195 | rtems_unsigned32 gsmr_l; |
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196 | rtems_unsigned32 gsmr_h; |
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197 | rtems_unsigned16 psmr; |
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198 | rtems_unsigned16 _pad0; |
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199 | rtems_unsigned16 todr; |
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200 | rtems_unsigned16 dsr; |
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201 | rtems_unsigned16 scce; |
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202 | rtems_unsigned16 _pad1; |
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203 | rtems_unsigned16 sccm; |
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204 | rtems_unsigned8 _pad2; |
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205 | rtems_unsigned8 sccs; |
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206 | rtems_unsigned32 _pad3[2]; |
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207 | } m8xxSCCRegisters_t; |
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208 | |
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209 | /* |
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210 | * Serial Management Controller registers |
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211 | */ |
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212 | typedef struct m8xxSMCRegisters_ { |
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213 | rtems_unsigned16 _pad0; |
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214 | rtems_unsigned16 smcmr; |
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215 | rtems_unsigned16 _pad1; |
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216 | rtems_unsigned8 smce; |
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217 | rtems_unsigned8 _pad2; |
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218 | rtems_unsigned16 _pad3; |
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219 | rtems_unsigned8 smcm; |
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220 | rtems_unsigned8 _pad4; |
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221 | rtems_unsigned32 _pad5; |
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222 | } m8xxSMCRegisters_t; |
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223 | |
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224 | /* |
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225 | * Fast Ethernet Controller registers (Only on MPC8xxT) |
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226 | */ |
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227 | typedef struct m8xxFECRegisters_ { |
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228 | rtems_unsigned32 addr_low; |
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229 | rtems_unsigned32 addr_high; |
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230 | rtems_unsigned32 hash_table_high; |
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231 | rtems_unsigned32 hash_table_low; |
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232 | rtems_unsigned32 r_des_start; |
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233 | rtems_unsigned32 x_des_start; |
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234 | rtems_unsigned32 r_buf_size; |
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235 | rtems_unsigned32 _pad0[9]; |
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236 | rtems_unsigned32 ecntrl; |
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237 | rtems_unsigned32 ievent; |
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238 | rtems_unsigned32 imask; |
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239 | rtems_unsigned32 ivec; |
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240 | rtems_unsigned32 r_des_active; |
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241 | rtems_unsigned32 x_des_active; |
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242 | rtems_unsigned32 _pad1[10]; |
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243 | rtems_unsigned32 mii_data; |
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244 | rtems_unsigned32 mii_speed; |
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245 | rtems_unsigned32 _pad2[17]; |
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246 | rtems_unsigned32 r_bound; |
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247 | rtems_unsigned32 r_fstart; |
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248 | rtems_unsigned32 _pad3[6]; |
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249 | rtems_unsigned32 x_fstart; |
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250 | rtems_unsigned32 _pad4[17]; |
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251 | rtems_unsigned32 fun_code; |
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252 | rtems_unsigned32 _pad5[3]; |
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253 | rtems_unsigned32 r_cntrl; |
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254 | rtems_unsigned32 r_hash; |
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255 | rtems_unsigned32 _pad6[14]; |
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256 | rtems_unsigned32 x_cntrl; |
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257 | rtems_unsigned32 _pad7[30]; |
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258 | |
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259 | } m8xxFECRegisters_t; |
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260 | |
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261 | #define M8xx_FEC_IEVENT_HBERR (1 << 31) |
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262 | #define M8xx_FEC_IEVENT_BABR (1 << 30) |
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263 | #define M8xx_FEC_IEVENT_BABT (1 << 29) |
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264 | #define M8xx_FEC_IEVENT_GRA (1 << 28) |
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265 | #define M8xx_FEC_IEVENT_TFINT (1 << 27) |
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266 | #define M8xx_FEC_IEVENT_TXB (1 << 26) |
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267 | #define M8xx_FEC_IEVENT_RFINT (1 << 25) |
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268 | #define M8xx_FEC_IEVENT_RXB (1 << 24) |
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269 | #define M8xx_FEC_IEVENT_MII (1 << 23) |
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270 | #define M8xx_FEC_IEVENT_EBERR (1 << 22) |
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271 | #define M8xx_FEC_IMASK_HBEEN (1 << 31) |
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272 | #define M8xx_FEC_IMASK_BREEN (1 << 30) |
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273 | #define M8xx_FEC_IMASK_BTEN (1 << 29) |
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274 | #define M8xx_FEC_IMASK_GRAEN (1 << 28) |
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275 | #define M8xx_FEC_IMASK_TFIEN (1 << 27) |
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276 | #define M8xx_FEC_IMASK_TBIEN (1 << 26) |
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277 | #define M8xx_FEC_IMASK_RFIEN (1 << 25) |
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278 | #define M8xx_FEC_IMASK_RBIEN (1 << 24) |
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279 | #define M8xx_FEC_IMASK_MIIEN (1 << 23) |
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280 | #define M8xx_FEC_IMASK_EBERREN (1 << 22) |
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281 | |
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282 | /* |
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283 | ************************************************************************* |
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284 | * Miscellaneous Parameters * |
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285 | ************************************************************************* |
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286 | */ |
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287 | typedef struct m8xxMiscParms_ { |
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288 | rtems_unsigned16 rev_num; |
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289 | rtems_unsigned16 _res1; |
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290 | rtems_unsigned32 _res2; |
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291 | rtems_unsigned32 _res3; |
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292 | } m8xxMiscParms_t; |
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293 | |
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294 | /* |
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295 | ************************************************************************* |
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296 | * RISC Timers * |
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297 | ************************************************************************* |
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298 | */ |
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299 | typedef struct m8xxTimerParms_ { |
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300 | rtems_unsigned16 tm_base; |
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301 | rtems_unsigned16 _tm_ptr; |
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302 | rtems_unsigned16 _r_tmr; |
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303 | rtems_unsigned16 _r_tmv; |
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304 | rtems_unsigned32 tm_cmd; |
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305 | rtems_unsigned32 tm_cnt; |
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306 | } m8xxTimerParms_t; |
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307 | |
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308 | /* |
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309 | * RISC Controller Configuration Register (RCCR) |
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310 | * All other bits in this register are reserved. |
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311 | */ |
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312 | #define M8xx_RCCR_TIME (1<<15) /* Enable timer */ |
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313 | #define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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314 | #define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ |
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315 | #define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ |
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316 | #define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ |
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317 | #define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */ |
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318 | #define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */ |
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319 | #define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ |
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320 | |
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321 | /* |
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322 | * Command register |
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323 | * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command. |
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324 | */ |
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325 | #define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */ |
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326 | #define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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327 | #define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */ |
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328 | #define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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329 | #define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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330 | |
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331 | /* |
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332 | ************************************************************************* |
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333 | * DMA Controllers * |
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334 | ************************************************************************* |
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335 | */ |
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336 | typedef struct m8xxIDMAparms_ { |
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337 | rtems_unsigned16 ibase; |
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338 | rtems_unsigned16 dcmr; |
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339 | rtems_unsigned32 _sapr; |
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340 | rtems_unsigned32 _dapr; |
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341 | rtems_unsigned16 ibptr; |
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342 | rtems_unsigned16 _write_sp; |
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343 | rtems_unsigned32 _s_byte_c; |
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344 | rtems_unsigned32 _d_byte_c; |
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345 | rtems_unsigned32 _s_state; |
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346 | rtems_unsigned32 _itemp[4]; |
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347 | rtems_unsigned32 _sr_mem; |
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348 | rtems_unsigned16 _read_sp; |
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349 | rtems_unsigned16 _res0; |
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350 | rtems_unsigned16 _res1; |
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351 | rtems_unsigned16 _res2; |
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352 | rtems_unsigned32 _d_state; |
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353 | } m8xxIDMAparms_t; |
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354 | |
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355 | |
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356 | /* |
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357 | ************************************************************************* |
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358 | * DSP * |
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359 | ************************************************************************* |
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360 | */ |
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361 | typedef struct m8xxDSPparms_ { |
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362 | rtems_unsigned32 fdbase; |
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363 | rtems_unsigned32 _fd_ptr; |
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364 | rtems_unsigned32 _dstate; |
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365 | rtems_unsigned32 _pad0; |
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366 | rtems_unsigned16 _dstatus; |
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367 | rtems_unsigned16 _i; |
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368 | rtems_unsigned16 _tap; |
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369 | rtems_unsigned16 _cbase; |
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370 | rtems_unsigned16 _pad1; |
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371 | rtems_unsigned16 _xptr; |
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372 | rtems_unsigned16 _pad2; |
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373 | rtems_unsigned16 _yptr; |
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374 | rtems_unsigned16 _m; |
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375 | rtems_unsigned16 _pad3; |
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376 | rtems_unsigned16 _n; |
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377 | rtems_unsigned16 _pad4; |
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378 | rtems_unsigned16 _k; |
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379 | rtems_unsigned16 _pad5; |
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380 | } m8xxDSPparms_t; |
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381 | |
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382 | /* |
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383 | ************************************************************************* |
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384 | * Serial Communication Controllers * |
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385 | ************************************************************************* |
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386 | */ |
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387 | typedef struct m8xxSCCparms_ { |
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388 | rtems_unsigned16 rbase; |
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389 | rtems_unsigned16 tbase; |
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390 | rtems_unsigned8 rfcr; |
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391 | rtems_unsigned8 tfcr; |
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392 | rtems_unsigned16 mrblr; |
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393 | rtems_unsigned32 _rstate; |
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394 | rtems_unsigned32 _pad0; |
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395 | rtems_unsigned16 _rbptr; |
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396 | rtems_unsigned16 _pad1; |
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397 | rtems_unsigned32 _pad2; |
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398 | rtems_unsigned32 _tstate; |
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399 | rtems_unsigned32 _pad3; |
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400 | rtems_unsigned16 _tbptr; |
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401 | rtems_unsigned16 _pad4; |
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402 | rtems_unsigned32 _pad5; |
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403 | rtems_unsigned32 _rcrc; |
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404 | rtems_unsigned32 _tcrc; |
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405 | union { |
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406 | struct { |
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407 | rtems_unsigned32 _res0; |
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408 | rtems_unsigned32 _res1; |
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409 | rtems_unsigned16 max_idl; |
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410 | rtems_unsigned16 _idlc; |
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411 | rtems_unsigned16 brkcr; |
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412 | rtems_unsigned16 parec; |
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413 | rtems_unsigned16 frmec; |
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414 | rtems_unsigned16 nosec; |
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415 | rtems_unsigned16 brkec; |
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416 | rtems_unsigned16 brkln; |
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417 | rtems_unsigned16 uaddr[2]; |
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418 | rtems_unsigned16 _rtemp; |
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419 | rtems_unsigned16 toseq; |
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420 | rtems_unsigned16 character[8]; |
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421 | rtems_unsigned16 rccm; |
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422 | rtems_unsigned16 rccr; |
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423 | rtems_unsigned16 rlbc; |
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424 | } uart; |
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425 | } un; |
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426 | } m8xxSCCparms_t; |
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427 | |
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428 | typedef struct m8xxSCCENparms_ { |
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429 | rtems_unsigned16 rbase; |
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430 | rtems_unsigned16 tbase; |
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431 | rtems_unsigned8 rfcr; |
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432 | rtems_unsigned8 tfcr; |
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433 | rtems_unsigned16 mrblr; |
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434 | rtems_unsigned32 _rstate; |
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435 | rtems_unsigned32 _pad0; |
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436 | rtems_unsigned16 _rbptr; |
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437 | rtems_unsigned16 _pad1; |
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438 | rtems_unsigned32 _pad2; |
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439 | rtems_unsigned32 _tstate; |
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440 | rtems_unsigned32 _pad3; |
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441 | rtems_unsigned16 _tbptr; |
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442 | rtems_unsigned16 _pad4; |
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443 | rtems_unsigned32 _pad5; |
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444 | rtems_unsigned32 _rcrc; |
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445 | rtems_unsigned32 _tcrc; |
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446 | union { |
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447 | struct { |
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448 | rtems_unsigned32 _res0; |
---|
449 | rtems_unsigned32 _res1; |
---|
450 | rtems_unsigned16 max_idl; |
---|
451 | rtems_unsigned16 _idlc; |
---|
452 | rtems_unsigned16 brkcr; |
---|
453 | rtems_unsigned16 parec; |
---|
454 | rtems_unsigned16 frmec; |
---|
455 | rtems_unsigned16 nosec; |
---|
456 | rtems_unsigned16 brkec; |
---|
457 | rtems_unsigned16 brkln; |
---|
458 | rtems_unsigned16 uaddr[2]; |
---|
459 | rtems_unsigned16 _rtemp; |
---|
460 | rtems_unsigned16 toseq; |
---|
461 | rtems_unsigned16 character[8]; |
---|
462 | rtems_unsigned16 rccm; |
---|
463 | rtems_unsigned16 rccr; |
---|
464 | rtems_unsigned16 rlbc; |
---|
465 | } uart; |
---|
466 | struct { |
---|
467 | rtems_unsigned32 c_pres; |
---|
468 | rtems_unsigned32 c_mask; |
---|
469 | rtems_unsigned32 crcec; |
---|
470 | rtems_unsigned32 alec; |
---|
471 | rtems_unsigned32 disfc; |
---|
472 | rtems_unsigned16 pads; |
---|
473 | rtems_unsigned16 ret_lim; |
---|
474 | rtems_unsigned16 _ret_cnt; |
---|
475 | rtems_unsigned16 mflr; |
---|
476 | rtems_unsigned16 minflr; |
---|
477 | rtems_unsigned16 maxd1; |
---|
478 | rtems_unsigned16 maxd2; |
---|
479 | rtems_unsigned16 _maxd; |
---|
480 | rtems_unsigned16 dma_cnt; |
---|
481 | rtems_unsigned16 _max_b; |
---|
482 | rtems_unsigned16 gaddr1; |
---|
483 | rtems_unsigned16 gaddr2; |
---|
484 | rtems_unsigned16 gaddr3; |
---|
485 | rtems_unsigned16 gaddr4; |
---|
486 | rtems_unsigned32 _tbuf0data0; |
---|
487 | rtems_unsigned32 _tbuf0data1; |
---|
488 | rtems_unsigned32 _tbuf0rba0; |
---|
489 | rtems_unsigned32 _tbuf0crc; |
---|
490 | rtems_unsigned16 _tbuf0bcnt; |
---|
491 | rtems_unsigned16 paddr_h; |
---|
492 | rtems_unsigned16 paddr_m; |
---|
493 | rtems_unsigned16 paddr_l; |
---|
494 | rtems_unsigned16 p_per; |
---|
495 | rtems_unsigned16 _rfbd_ptr; |
---|
496 | rtems_unsigned16 _tfbd_ptr; |
---|
497 | rtems_unsigned16 _tlbd_ptr; |
---|
498 | rtems_unsigned32 _tbuf1data0; |
---|
499 | rtems_unsigned32 _tbuf1data1; |
---|
500 | rtems_unsigned32 _tbuf1rba0; |
---|
501 | rtems_unsigned32 _tbuf1crc; |
---|
502 | rtems_unsigned16 _tbuf1bcnt; |
---|
503 | rtems_unsigned16 _tx_len; |
---|
504 | rtems_unsigned16 iaddr1; |
---|
505 | rtems_unsigned16 iaddr2; |
---|
506 | rtems_unsigned16 iaddr3; |
---|
507 | rtems_unsigned16 iaddr4; |
---|
508 | rtems_unsigned16 _boff_cnt; |
---|
509 | rtems_unsigned16 taddr_l; |
---|
510 | rtems_unsigned16 taddr_m; |
---|
511 | rtems_unsigned16 taddr_h; |
---|
512 | } ethernet; |
---|
513 | } un; |
---|
514 | } m8xxSCCENparms_t; |
---|
515 | |
---|
516 | /* |
---|
517 | * Receive and transmit function code register bits |
---|
518 | * These apply to the function code registers of all devices, not just SCC. |
---|
519 | */ |
---|
520 | #define M8xx_RFCR_BO(x) ((x)<<3) |
---|
521 | #define M8xx_RFCR_MOT (2<<3) |
---|
522 | #define M8xx_RFCR_DMA_SPACE(x) (x) |
---|
523 | #define M8xx_TFCR_BO(x) ((x)<<3) |
---|
524 | #define M8xx_TFCR_MOT (2<<3) |
---|
525 | #define M8xx_TFCR_DMA_SPACE(x) (x) |
---|
526 | |
---|
527 | /* |
---|
528 | * Event and mask registers (SCCE, SCCM) |
---|
529 | */ |
---|
530 | #define M8xx_SCCE_BRKE (1<<6) |
---|
531 | #define M8xx_SCCE_BRK (1<<4) |
---|
532 | #define M8xx_SCCE_BSY (1<<2) |
---|
533 | #define M8xx_SCCE_TX (1<<1) |
---|
534 | #define M8xx_SCCE_RX (1<<0) |
---|
535 | |
---|
536 | /* |
---|
537 | ************************************************************************* |
---|
538 | * Serial Management Controllers * |
---|
539 | ************************************************************************* |
---|
540 | */ |
---|
541 | typedef struct m8xxSMCparms_ { |
---|
542 | rtems_unsigned16 rbase; |
---|
543 | rtems_unsigned16 tbase; |
---|
544 | rtems_unsigned8 rfcr; |
---|
545 | rtems_unsigned8 tfcr; |
---|
546 | rtems_unsigned16 mrblr; |
---|
547 | rtems_unsigned32 _rstate; |
---|
548 | rtems_unsigned32 _pad0; |
---|
549 | rtems_unsigned16 _rbptr; |
---|
550 | rtems_unsigned16 _pad1; |
---|
551 | rtems_unsigned32 _pad2; |
---|
552 | rtems_unsigned32 _tstate; |
---|
553 | rtems_unsigned32 _pad3; |
---|
554 | rtems_unsigned16 _tbptr; |
---|
555 | rtems_unsigned16 _pad4; |
---|
556 | rtems_unsigned32 _pad5; |
---|
557 | union { |
---|
558 | struct { |
---|
559 | rtems_unsigned16 max_idl; |
---|
560 | rtems_unsigned16 _idlc; |
---|
561 | rtems_unsigned16 brkln; |
---|
562 | rtems_unsigned16 brkec; |
---|
563 | rtems_unsigned16 brkcr; |
---|
564 | rtems_unsigned16 _r_mask; |
---|
565 | } uart; |
---|
566 | struct { |
---|
567 | rtems_unsigned16 _pad0[5]; |
---|
568 | } transparent; |
---|
569 | } un; |
---|
570 | } m8xxSMCparms_t; |
---|
571 | |
---|
572 | /* |
---|
573 | * Mode register |
---|
574 | */ |
---|
575 | #define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
---|
576 | #define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
---|
577 | #define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */ |
---|
578 | #define M8xx_SMCMR_EVEN (1<<8) /* Even parity */ |
---|
579 | #define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
---|
580 | #define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */ |
---|
581 | #define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
---|
582 | #define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
---|
583 | #define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
---|
584 | #define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */ |
---|
585 | #define M8xx_SMCMR_REN (1<<0) /* Enable receiver */ |
---|
586 | |
---|
587 | /* |
---|
588 | * Event and mask registers (SMCE, SMCM) |
---|
589 | */ |
---|
590 | #define M8xx_SMCE_BRKE (1<<6) |
---|
591 | #define M8xx_SMCE_BRK (1<<4) |
---|
592 | #define M8xx_SMCE_BSY (1<<2) |
---|
593 | #define M8xx_SMCE_TX (1<<1) |
---|
594 | #define M8xx_SMCE_RX (1<<0) |
---|
595 | |
---|
596 | /* |
---|
597 | ************************************************************************* |
---|
598 | * Serial Peripheral Interface * |
---|
599 | ************************************************************************* |
---|
600 | */ |
---|
601 | typedef struct m8xxSPIparms_ { |
---|
602 | rtems_unsigned16 rbase; |
---|
603 | rtems_unsigned16 tbase; |
---|
604 | rtems_unsigned8 rfcr; |
---|
605 | rtems_unsigned8 tfcr; |
---|
606 | rtems_unsigned16 mrblr; |
---|
607 | rtems_unsigned32 _rstate; |
---|
608 | rtems_unsigned32 _pad0; |
---|
609 | rtems_unsigned16 _rbptr; |
---|
610 | rtems_unsigned16 _pad1; |
---|
611 | rtems_unsigned32 _pad2; |
---|
612 | rtems_unsigned32 _tstate; |
---|
613 | rtems_unsigned32 _pad3; |
---|
614 | rtems_unsigned16 _tbptr; |
---|
615 | rtems_unsigned16 _pad4; |
---|
616 | rtems_unsigned32 _pad5; |
---|
617 | } m8xxSPIparms_t; |
---|
618 | |
---|
619 | /* |
---|
620 | * Mode register (SPMODE) |
---|
621 | */ |
---|
622 | #define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
---|
623 | #define M8xx_SPMODE_CI (1<<13) /* Clock invert */ |
---|
624 | #define M8xx_SPMODE_CP (1<<12) /* Clock phase */ |
---|
625 | #define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
---|
626 | #define M8xx_SPMODE_REV (1<<10) /* Reverse data */ |
---|
627 | #define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */ |
---|
628 | #define M8xx_SPMODE_EN (1<<8) /* Enable SPI */ |
---|
629 | #define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
---|
630 | #define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */ |
---|
631 | |
---|
632 | /* |
---|
633 | * Mode register (SPCOM) |
---|
634 | */ |
---|
635 | #define M8xx_SPCOM_STR (1<<7) /* Start transmit */ |
---|
636 | |
---|
637 | /* |
---|
638 | * Event and mask registers (SPIE, SPIM) |
---|
639 | */ |
---|
640 | #define M8xx_SPIE_MME (1<<5) /* Multi-master error */ |
---|
641 | #define M8xx_SPIE_TXE (1<<4) /* Tx error */ |
---|
642 | #define M8xx_SPIE_BSY (1<<2) /* Busy condition*/ |
---|
643 | #define M8xx_SPIE_TXB (1<<1) /* Tx buffer */ |
---|
644 | #define M8xx_SPIE_RXB (1<<0) /* Rx buffer */ |
---|
645 | |
---|
646 | /* |
---|
647 | ************************************************************************* |
---|
648 | * SDMA (SCC, SMC, SPI) Buffer Descriptors * |
---|
649 | ************************************************************************* |
---|
650 | */ |
---|
651 | typedef struct m8xxBufferDescriptor_ { |
---|
652 | rtems_unsigned16 status; |
---|
653 | rtems_unsigned16 length; |
---|
654 | volatile void *buffer; |
---|
655 | } m8xxBufferDescriptor_t; |
---|
656 | |
---|
657 | /* |
---|
658 | * Bits in receive buffer descriptor status word |
---|
659 | */ |
---|
660 | #define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
661 | #define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
662 | #define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
663 | #define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ |
---|
664 | #define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
---|
665 | #define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
---|
666 | #define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ |
---|
667 | #define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
---|
668 | #define M8xx_BD_MISS (1<<8) /* Ethernet */ |
---|
669 | #define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
---|
670 | #define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
---|
671 | #define M8xx_BD_LONG (1<<5) /* Ethernet */ |
---|
672 | #define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
---|
673 | #define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */ |
---|
674 | #define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
---|
675 | #define M8xx_BD_SHORT (1<<3) /* Ethernet */ |
---|
676 | #define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
---|
677 | #define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */ |
---|
678 | #define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
679 | #define M8xx_BD_COLLISION (1<<0) /* Ethernet */ |
---|
680 | #define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ |
---|
681 | #define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ |
---|
682 | |
---|
683 | /* |
---|
684 | * Bits in transmit buffer descriptor status word |
---|
685 | * Many bits have the same meaning as those in receiver buffer descriptors. |
---|
686 | */ |
---|
687 | #define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
688 | #define M8xx_BD_PAD (1<<14) /* Ethernet */ |
---|
689 | #define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ |
---|
690 | #define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ |
---|
691 | #define M8xx_BD_DEFER (1<<9) /* Ethernet */ |
---|
692 | #define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ |
---|
693 | #define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
---|
694 | #define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
---|
695 | #define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
---|
696 | #define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
---|
697 | #define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
---|
698 | #define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
---|
699 | #define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
---|
700 | #define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */ |
---|
701 | |
---|
702 | /* |
---|
703 | ************************************************************************* |
---|
704 | * IDMA Buffer Descriptors * |
---|
705 | ************************************************************************* |
---|
706 | */ |
---|
707 | typedef struct m8xxIDMABufferDescriptor_ { |
---|
708 | rtems_unsigned16 status; |
---|
709 | rtems_unsigned8 dfcr; |
---|
710 | rtems_unsigned8 sfcr; |
---|
711 | rtems_unsigned32 length; |
---|
712 | void *source; |
---|
713 | void *destination; |
---|
714 | } m8xxIDMABufferDescriptor_t; |
---|
715 | |
---|
716 | /* |
---|
717 | ************************************************************************* |
---|
718 | * RISC Communication Processor Module Command Register (CR) * |
---|
719 | ************************************************************************* |
---|
720 | */ |
---|
721 | #define M8xx_CR_RST (1<<15) /* Reset communication processor */ |
---|
722 | #define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
---|
723 | #define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
---|
724 | #define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
---|
725 | #define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
---|
726 | #define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
---|
727 | #define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
---|
728 | #define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
---|
729 | #define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
---|
730 | #define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
---|
731 | #define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
---|
732 | #define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */ |
---|
733 | #define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
---|
734 | #define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
---|
735 | #define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
---|
736 | #define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */ |
---|
737 | #define M8xx_CR_OP_START_DSP (12<<8) /* DSP */ |
---|
738 | #define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */ |
---|
739 | |
---|
740 | #define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
---|
741 | #define M8xx_CR_CHAN_I2C (1<<4) |
---|
742 | #define M8xx_CR_CHAN_IDMA1 (1<<4) |
---|
743 | #define M8xx_CR_CHAN_SCC2 (4<<4) |
---|
744 | #define M8xx_CR_CHAN_SPI (5<<4) |
---|
745 | #define M8xx_CR_CHAN_IDMA2 (5<<4) |
---|
746 | #define M8xx_CR_CHAN_TIMER (5<<4) |
---|
747 | #define M8xx_CR_CHAN_SCC3 (8<<4) |
---|
748 | #define M8xx_CR_CHAN_SMC1 (9<<4) |
---|
749 | #define M8xx_CR_CHAN_DSP1 (9<<4) |
---|
750 | #define M8xx_CR_CHAN_SCC4 (12<<4) |
---|
751 | #define M8xx_CR_CHAN_SMC2 (13<<4) |
---|
752 | #define M8xx_CR_CHAN_DSP2 (13<<4) |
---|
753 | #define M8xx_CR_FLG (1<<0) /* Command flag */ |
---|
754 | |
---|
755 | /* |
---|
756 | ************************************************************************* |
---|
757 | * System Protection Control Register (SYPCR) * |
---|
758 | ************************************************************************* |
---|
759 | */ |
---|
760 | #define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ |
---|
761 | #define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
762 | #define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
763 | #define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
764 | #define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
765 | #define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
766 | #define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
767 | |
---|
768 | /* |
---|
769 | ************************************************************************* |
---|
770 | * Memory Control Registers * |
---|
771 | ************************************************************************* |
---|
772 | */ |
---|
773 | #define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */ |
---|
774 | #define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */ |
---|
775 | #define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */ |
---|
776 | #define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */ |
---|
777 | #define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */ |
---|
778 | #define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */ |
---|
779 | #define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ |
---|
780 | #define M8xx_MSR_WPER (1<<7) /* Write protection error */ |
---|
781 | #define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ |
---|
782 | #define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */ |
---|
783 | #define M8xx_BR_AT(x) ((x)<<12) /* Address type */ |
---|
784 | #define M8xx_BR_PS8 (1<<10) /* 8 bit port */ |
---|
785 | #define M8xx_BR_PS16 (2<<10) /* 16 bit port */ |
---|
786 | #define M8xx_BR_PS32 (0<<10) /* 32 bit port */ |
---|
787 | #define M8xx_BR_PARE (1<<9) /* Parity checking enable */ |
---|
788 | #define M8xx_BR_WP (1<<8) /* Write protect */ |
---|
789 | #define M8xx_BR_MS_GPCM (0<<6) /* GPCM */ |
---|
790 | #define M8xx_BR_MS_UPMA (2<<6) /* UPM A */ |
---|
791 | #define M8xx_BR_MS_UPMB (3<<6) /* UPM B */ |
---|
792 | #define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
793 | |
---|
794 | #define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */ |
---|
795 | #define M8xx_MEMC_OR_64K 0xffff0000 |
---|
796 | #define M8xx_MEMC_OR_128K 0xfffe0000 |
---|
797 | #define M8xx_MEMC_OR_256K 0xfffc0000 |
---|
798 | #define M8xx_MEMC_OR_512K 0xfff80000 |
---|
799 | #define M8xx_MEMC_OR_1M 0xfff00000 |
---|
800 | #define M8xx_MEMC_OR_2M 0xffe00000 |
---|
801 | #define M8xx_MEMC_OR_4M 0xffc00000 |
---|
802 | #define M8xx_MEMC_OR_8M 0xff800000 |
---|
803 | #define M8xx_MEMC_OR_16M 0xff000000 |
---|
804 | #define M8xx_MEMC_OR_32M 0xfe000000 |
---|
805 | #define M8xx_MEMC_OR_64M 0xfc000000 |
---|
806 | #define M8xx_MEMC_OR_128 0xf8000000 |
---|
807 | #define M8xx_MEMC_OR_256M 0xf0000000 |
---|
808 | #define M8xx_MEMC_OR_512M 0xe0000000 |
---|
809 | #define M8xx_MEMC_OR_1G 0xc0000000 |
---|
810 | #define M8xx_MEMC_OR_2G 0x80000000 |
---|
811 | #define M8xx_MEMC_OR_4G 0x00000000 |
---|
812 | #define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ |
---|
813 | #define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ |
---|
814 | #define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ |
---|
815 | #define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ |
---|
816 | #define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ |
---|
817 | #define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ |
---|
818 | #define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */ |
---|
819 | #define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ |
---|
820 | #define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */ |
---|
821 | #define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ |
---|
822 | #define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ |
---|
823 | |
---|
824 | /* |
---|
825 | ************************************************************************* |
---|
826 | * UPM Registers (MxMR) * |
---|
827 | ************************************************************************* |
---|
828 | */ |
---|
829 | #define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ |
---|
830 | #define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ |
---|
831 | #define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ |
---|
832 | #define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ |
---|
833 | #define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ |
---|
834 | #define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ |
---|
835 | #define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ |
---|
836 | #define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ |
---|
837 | /* |
---|
838 | ************************************************************************* |
---|
839 | * Memory Command Register (MCR) * |
---|
840 | ************************************************************************* |
---|
841 | */ |
---|
842 | #define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */ |
---|
843 | #define M8xx_MEMC_MCR_READ (1<<30) /* READ command */ |
---|
844 | #define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */ |
---|
845 | #define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ |
---|
846 | #define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ |
---|
847 | #define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ |
---|
848 | #define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ |
---|
849 | #define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */ |
---|
850 | |
---|
851 | |
---|
852 | |
---|
853 | /* |
---|
854 | ************************************************************************* |
---|
855 | * SI Mode Register (SIMODE) * |
---|
856 | ************************************************************************* |
---|
857 | */ |
---|
858 | #define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
---|
859 | #define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
---|
860 | #define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
---|
861 | #define M8xx_SI_SMC2_BRG2 (1<<28) |
---|
862 | #define M8xx_SI_SMC2_BRG3 (2<<28) |
---|
863 | #define M8xx_SI_SMC2_BRG4 (3<<28) |
---|
864 | #define M8xx_SI_SMC2_CLK5 (0<<28) |
---|
865 | #define M8xx_SI_SMC2_CLK6 (1<<28) |
---|
866 | #define M8xx_SI_SMC2_CLK7 (2<<28) |
---|
867 | #define M8xx_SI_SMC2_CLK8 (3<<28) |
---|
868 | #define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
---|
869 | #define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
---|
870 | #define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
---|
871 | #define M8xx_SI_SMC1_BRG2 (1<<12) |
---|
872 | #define M8xx_SI_SMC1_BRG3 (2<<12) |
---|
873 | #define M8xx_SI_SMC1_BRG4 (3<<12) |
---|
874 | #define M8xx_SI_SMC1_CLK1 (0<<12) |
---|
875 | #define M8xx_SI_SMC1_CLK2 (1<<12) |
---|
876 | #define M8xx_SI_SMC1_CLK3 (2<<12) |
---|
877 | #define M8xx_SI_SMC1_CLK4 (3<<12) |
---|
878 | |
---|
879 | /* |
---|
880 | ************************************************************************* |
---|
881 | * SDMA Configuration Register (SDCR) * |
---|
882 | ************************************************************************* |
---|
883 | */ |
---|
884 | #define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ |
---|
885 | #define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ |
---|
886 | |
---|
887 | /* |
---|
888 | ************************************************************************* |
---|
889 | * SDMA Status Register (SDSR) * |
---|
890 | ************************************************************************* |
---|
891 | */ |
---|
892 | #define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */ |
---|
893 | #define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ |
---|
894 | #define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ |
---|
895 | |
---|
896 | /* |
---|
897 | ************************************************************************* |
---|
898 | * Baud (sic) Rate Generators * |
---|
899 | ************************************************************************* |
---|
900 | */ |
---|
901 | #define M8xx_BRG_RST (1<<17) /* Reset generator */ |
---|
902 | #define M8xx_BRG_EN (1<<16) /* Enable generator */ |
---|
903 | #define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
---|
904 | #define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
---|
905 | #define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
---|
906 | #define M8xx_BRG_ATB (1<<13) /* Autobaud */ |
---|
907 | #define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */ |
---|
908 | #define M8xx_BRG_57600 (32<<1) |
---|
909 | #define M8xx_BRG_38400 (64<<1) |
---|
910 | #define M8xx_BRG_19200 (129<<1) |
---|
911 | #define M8xx_BRG_9600 (259<<1) |
---|
912 | #define M8xx_BRG_4800 (520<<1) |
---|
913 | #define M8xx_BRG_2400 (1040<<1) |
---|
914 | #define M8xx_BRG_1200 (2082<<1) |
---|
915 | #define M8xx_BRG_600 ((259<<1) | 1) |
---|
916 | #define M8xx_BRG_300 ((520<<1) | 1) |
---|
917 | #define M8xx_BRG_150 ((1040<<1) | 1) |
---|
918 | #define M8xx_BRG_75 ((2080<<1) | 1) |
---|
919 | |
---|
920 | #define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ |
---|
921 | #define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ |
---|
922 | #define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ |
---|
923 | #define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ |
---|
924 | #define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ |
---|
925 | #define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ |
---|
926 | #define M8xx_TGCR_STP1 (1<<1) /* Stop timer */ |
---|
927 | #define M8xx_TGCR_STP2 (1<<5) /* Stop timer */ |
---|
928 | #define M8xx_TGCR_STP3 (1<<9) /* Stop timer */ |
---|
929 | #define M8xx_TGCR_STP4 (1<<13) /* Stop timer */ |
---|
930 | #define M8xx_TGCR_RST1 (1<<0) /* Enable timer */ |
---|
931 | #define M8xx_TGCR_RST2 (1<<4) /* Enable timer */ |
---|
932 | #define M8xx_TGCR_RST3 (1<<8) /* Enable timer */ |
---|
933 | #define M8xx_TGCR_RST4 (1<<12) /* Enable timer */ |
---|
934 | #define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ |
---|
935 | #define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ |
---|
936 | |
---|
937 | #define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */ |
---|
938 | #define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */ |
---|
939 | #define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */ |
---|
940 | #define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */ |
---|
941 | #define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ |
---|
942 | #define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */ |
---|
943 | #define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */ |
---|
944 | #define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ |
---|
945 | #define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ |
---|
946 | #define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ |
---|
947 | #define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */ |
---|
948 | |
---|
949 | #define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ |
---|
950 | #define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */ |
---|
951 | #define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */ |
---|
952 | #define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ |
---|
953 | #define M8xx_PISCR_PTE (1<<0) /* PIT enable */ |
---|
954 | |
---|
955 | #define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ |
---|
956 | #define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ |
---|
957 | #define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ |
---|
958 | #define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ |
---|
959 | #define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ |
---|
960 | #define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ |
---|
961 | #define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */ |
---|
962 | |
---|
963 | #define M8xx_SIMASK_IRM0 (1<<31) |
---|
964 | #define M8xx_SIMASK_LVM0 (1<<30) |
---|
965 | #define M8xx_SIMASK_IRM1 (1<<29) |
---|
966 | #define M8xx_SIMASK_LVM1 (1<<28) |
---|
967 | #define M8xx_SIMASK_IRM2 (1<<27) |
---|
968 | #define M8xx_SIMASK_LVM2 (1<<26) |
---|
969 | #define M8xx_SIMASK_IRM3 (1<<25) |
---|
970 | #define M8xx_SIMASK_LVM3 (1<<24) |
---|
971 | #define M8xx_SIMASK_IRM4 (1<<23) |
---|
972 | #define M8xx_SIMASK_LVM4 (1<<22) |
---|
973 | #define M8xx_SIMASK_IRM5 (1<<21) |
---|
974 | #define M8xx_SIMASK_LVM5 (1<<20) |
---|
975 | #define M8xx_SIMASK_IRM6 (1<<19) |
---|
976 | #define M8xx_SIMASK_LVM6 (1<<18) |
---|
977 | #define M8xx_SIMASK_IRM7 (1<<17) |
---|
978 | #define M8xx_SIMASK_LVM7 (1<<16) |
---|
979 | |
---|
980 | #define M8xx_SIUMCR_EARB (1<<31) |
---|
981 | #define M8xx_SIUMCR_EARP0 (0<<28) |
---|
982 | #define M8xx_SIUMCR_EARP1 (1<<28) |
---|
983 | #define M8xx_SIUMCR_EARP2 (2<<28) |
---|
984 | #define M8xx_SIUMCR_EARP3 (3<<28) |
---|
985 | #define M8xx_SIUMCR_EARP4 (4<<28) |
---|
986 | #define M8xx_SIUMCR_EARP5 (5<<28) |
---|
987 | #define M8xx_SIUMCR_EARP6 (6<<28) |
---|
988 | #define M8xx_SIUMCR_EARP7 (7<<28) |
---|
989 | #define M8xx_SIUMCR_DSHW (1<<23) |
---|
990 | #define M8xx_SIUMCR_DBGC0 (0<<21) |
---|
991 | #define M8xx_SIUMCR_DBGC1 (1<<21) |
---|
992 | #define M8xx_SIUMCR_DBGC2 (2<<21) |
---|
993 | #define M8xx_SIUMCR_DBGC3 (3<<21) |
---|
994 | #define M8xx_SIUMCR_DBPC0 (0<<19) |
---|
995 | #define M8xx_SIUMCR_DBPC1 (1<<19) |
---|
996 | #define M8xx_SIUMCR_DBPC2 (2<<19) |
---|
997 | #define M8xx_SIUMCR_DBPC3 (3<<19) |
---|
998 | #define M8xx_SIUMCR_FRC (1<<17) |
---|
999 | #define M8xx_SIUMCR_DLK (1<<16) |
---|
1000 | #define M8xx_SIUMCR_PNCS (1<<15) |
---|
1001 | #define M8xx_SIUMCR_OPAR (1<<14) |
---|
1002 | #define M8xx_SIUMCR_DPC (1<<13) |
---|
1003 | #define M8xx_SIUMCR_MPRE (1<<12) |
---|
1004 | #define M8xx_SIUMCR_MLRC0 (0<<10) |
---|
1005 | #define M8xx_SIUMCR_MLRC1 (1<<10) |
---|
1006 | #define M8xx_SIUMCR_MLRC2 (2<<10) |
---|
1007 | #define M8xx_SIUMCR_MLRC3 (3<<10) |
---|
1008 | #define M8xx_SIUMCR_AEME (1<<9) |
---|
1009 | #define M8xx_SIUMCR_SEME (1<<8) |
---|
1010 | #define M8xx_SIUMCR_BSC (1<<7) |
---|
1011 | #define M8xx_SIUMCR_GB5E (1<<6) |
---|
1012 | #define M8xx_SIUMCR_B2DD (1<<5) |
---|
1013 | #define M8xx_SIUMCR_B3DD (1<<4) |
---|
1014 | |
---|
1015 | /* |
---|
1016 | * Value to write to a key register to unlock the corresponding SIU register |
---|
1017 | */ |
---|
1018 | #define M8xx_UNLOCK_KEY 0x55CCAA33 |
---|
1019 | |
---|
1020 | /* |
---|
1021 | ************************************************************************* |
---|
1022 | * MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * |
---|
1023 | ************************************************************************* |
---|
1024 | */ |
---|
1025 | typedef struct m8xx_ { |
---|
1026 | |
---|
1027 | /* |
---|
1028 | * SIU Block |
---|
1029 | */ |
---|
1030 | rtems_unsigned32 siumcr; |
---|
1031 | rtems_unsigned32 sypcr; |
---|
1032 | #if defined(mpc860) |
---|
1033 | rtems_unsigned32 swt; |
---|
1034 | #elif defined(mpc821) |
---|
1035 | rtems_unsigned32 _pad70; |
---|
1036 | #endif |
---|
1037 | rtems_unsigned16 _pad0; |
---|
1038 | rtems_unsigned16 swsr; |
---|
1039 | rtems_unsigned32 sipend; |
---|
1040 | rtems_unsigned32 simask; |
---|
1041 | rtems_unsigned32 siel; |
---|
1042 | rtems_unsigned32 sivec; |
---|
1043 | rtems_unsigned32 tesr; |
---|
1044 | rtems_unsigned32 _pad1[3]; |
---|
1045 | rtems_unsigned32 sdcr; |
---|
1046 | rtems_unsigned8 _pad2[0x80-0x34]; |
---|
1047 | |
---|
1048 | /* |
---|
1049 | * PCMCIA Block |
---|
1050 | */ |
---|
1051 | rtems_unsigned32 pbr0; |
---|
1052 | rtems_unsigned32 por0; |
---|
1053 | rtems_unsigned32 pbr1; |
---|
1054 | rtems_unsigned32 por1; |
---|
1055 | rtems_unsigned32 pbr2; |
---|
1056 | rtems_unsigned32 por2; |
---|
1057 | rtems_unsigned32 pbr3; |
---|
1058 | rtems_unsigned32 por3; |
---|
1059 | rtems_unsigned32 pbr4; |
---|
1060 | rtems_unsigned32 por4; |
---|
1061 | rtems_unsigned32 pbr5; |
---|
1062 | rtems_unsigned32 por5; |
---|
1063 | rtems_unsigned32 pbr6; |
---|
1064 | rtems_unsigned32 por6; |
---|
1065 | rtems_unsigned32 pbr7; |
---|
1066 | rtems_unsigned32 por7; |
---|
1067 | rtems_unsigned8 _pad3[0xe0-0xc0]; |
---|
1068 | rtems_unsigned32 pgcra; |
---|
1069 | rtems_unsigned32 pgcrb; |
---|
1070 | rtems_unsigned32 pscr; |
---|
1071 | rtems_unsigned32 _pad4; |
---|
1072 | rtems_unsigned32 pipr; |
---|
1073 | rtems_unsigned32 _pad5; |
---|
1074 | rtems_unsigned32 per; |
---|
1075 | rtems_unsigned32 _pad6; |
---|
1076 | |
---|
1077 | /* |
---|
1078 | * MEMC Block |
---|
1079 | */ |
---|
1080 | m8xxMEMCRegisters_t memc[8]; |
---|
1081 | rtems_unsigned8 _pad7[0x164-0x140]; |
---|
1082 | rtems_unsigned32 mar; |
---|
1083 | rtems_unsigned32 mcr; |
---|
1084 | rtems_unsigned32 _pad8; |
---|
1085 | rtems_unsigned32 mamr; |
---|
1086 | rtems_unsigned32 mbmr; |
---|
1087 | rtems_unsigned16 mstat; |
---|
1088 | rtems_unsigned16 mptpr; |
---|
1089 | rtems_unsigned32 mdr; |
---|
1090 | rtems_unsigned8 _pad9[0x200-0x180]; |
---|
1091 | |
---|
1092 | /* |
---|
1093 | * System integration timers |
---|
1094 | */ |
---|
1095 | rtems_unsigned16 tbscr; |
---|
1096 | rtems_unsigned16 _pad10; |
---|
1097 | rtems_unsigned32 tbreff0; |
---|
1098 | rtems_unsigned32 tbreff1; |
---|
1099 | rtems_unsigned8 _pad11[0x220-0x20c]; |
---|
1100 | rtems_unsigned16 rtcsc; |
---|
1101 | rtems_unsigned16 _pad12; |
---|
1102 | rtems_unsigned32 rtc; |
---|
1103 | rtems_unsigned32 rtsec; |
---|
1104 | rtems_unsigned32 rtcal; |
---|
1105 | rtems_unsigned32 _pad13[4]; |
---|
1106 | rtems_unsigned16 piscr; |
---|
1107 | rtems_unsigned16 _pad14; |
---|
1108 | rtems_unsigned16 pitc; |
---|
1109 | rtems_unsigned16 _pad_14_1; |
---|
1110 | rtems_unsigned16 pitr; |
---|
1111 | rtems_unsigned16 _pad_14_2; |
---|
1112 | rtems_unsigned8 _pad15[0x280-0x24c]; |
---|
1113 | |
---|
1114 | |
---|
1115 | /* |
---|
1116 | * Clocks and Reset |
---|
1117 | */ |
---|
1118 | rtems_unsigned32 sccr; |
---|
1119 | rtems_unsigned32 plprcr; |
---|
1120 | rtems_unsigned32 rsr; |
---|
1121 | rtems_unsigned8 _pad16[0x300-0x28c]; |
---|
1122 | |
---|
1123 | |
---|
1124 | /* |
---|
1125 | * System integration timers keys |
---|
1126 | */ |
---|
1127 | rtems_unsigned32 tbscrk; |
---|
1128 | rtems_unsigned32 tbreff0k; |
---|
1129 | rtems_unsigned32 tbreff1k; |
---|
1130 | rtems_unsigned32 tbk; |
---|
1131 | rtems_unsigned32 _pad17[4]; |
---|
1132 | rtems_unsigned32 rtcsk; |
---|
1133 | rtems_unsigned32 rtck; |
---|
1134 | rtems_unsigned32 rtseck; |
---|
1135 | rtems_unsigned32 rtcalk; |
---|
1136 | rtems_unsigned32 _pad18[4]; |
---|
1137 | rtems_unsigned32 piscrk; |
---|
1138 | rtems_unsigned32 pitck; |
---|
1139 | rtems_unsigned8 _pad19[0x380-0x348]; |
---|
1140 | |
---|
1141 | /* |
---|
1142 | * Clocks and Reset Keys |
---|
1143 | */ |
---|
1144 | rtems_unsigned32 sccrk; |
---|
1145 | rtems_unsigned32 plprck; |
---|
1146 | rtems_unsigned32 rsrk; |
---|
1147 | rtems_unsigned8 _pad20[0x400-0x38c]; |
---|
1148 | rtems_unsigned8 _pad21[0x800-0x400]; |
---|
1149 | rtems_unsigned8 _pad22[0x860-0x800]; |
---|
1150 | |
---|
1151 | |
---|
1152 | /* |
---|
1153 | * I2C |
---|
1154 | */ |
---|
1155 | rtems_unsigned8 i2mod; |
---|
1156 | rtems_unsigned8 _pad23[3]; |
---|
1157 | rtems_unsigned8 i2add; |
---|
1158 | rtems_unsigned8 _pad24[3]; |
---|
1159 | rtems_unsigned8 i2brg; |
---|
1160 | rtems_unsigned8 _pad25[3]; |
---|
1161 | rtems_unsigned8 i2com; |
---|
1162 | rtems_unsigned8 _pad26[3]; |
---|
1163 | rtems_unsigned8 i2cer; |
---|
1164 | rtems_unsigned8 _pad27[3]; |
---|
1165 | rtems_unsigned8 i2cmr; |
---|
1166 | rtems_unsigned8 _pad28[0x900-0x875]; |
---|
1167 | |
---|
1168 | /* |
---|
1169 | * DMA Block |
---|
1170 | */ |
---|
1171 | rtems_unsigned32 _pad29; |
---|
1172 | rtems_unsigned32 sdar; |
---|
1173 | rtems_unsigned8 sdsr; |
---|
1174 | rtems_unsigned8 _pad30[3]; |
---|
1175 | rtems_unsigned8 sdmr; |
---|
1176 | rtems_unsigned8 _pad31[3]; |
---|
1177 | rtems_unsigned8 idsr1; |
---|
1178 | rtems_unsigned8 _pad32[3]; |
---|
1179 | rtems_unsigned8 idmr1; |
---|
1180 | rtems_unsigned8 _pad33[3]; |
---|
1181 | rtems_unsigned8 idsr2; |
---|
1182 | rtems_unsigned8 _pad34[3]; |
---|
1183 | rtems_unsigned8 idmr2; |
---|
1184 | rtems_unsigned8 _pad35[0x930-0x91d]; |
---|
1185 | |
---|
1186 | /* |
---|
1187 | * CPM Interrupt Control Block |
---|
1188 | */ |
---|
1189 | rtems_unsigned16 civr; |
---|
1190 | rtems_unsigned8 _pad36[14]; |
---|
1191 | rtems_unsigned32 cicr; |
---|
1192 | rtems_unsigned32 cipr; |
---|
1193 | rtems_unsigned32 cimr; |
---|
1194 | rtems_unsigned32 cisr; |
---|
1195 | |
---|
1196 | /* |
---|
1197 | * I/O Port Block |
---|
1198 | */ |
---|
1199 | rtems_unsigned16 padir; |
---|
1200 | rtems_unsigned16 papar; |
---|
1201 | rtems_unsigned16 paodr; |
---|
1202 | rtems_unsigned16 padat; |
---|
1203 | rtems_unsigned8 _pad37[8]; |
---|
1204 | rtems_unsigned16 pcdir; |
---|
1205 | rtems_unsigned16 pcpar; |
---|
1206 | rtems_unsigned16 pcso; |
---|
1207 | rtems_unsigned16 pcdat; |
---|
1208 | rtems_unsigned16 pcint; |
---|
1209 | rtems_unsigned8 _pad39[6]; |
---|
1210 | rtems_unsigned16 pddir; |
---|
1211 | rtems_unsigned16 pdpar; |
---|
1212 | rtems_unsigned16 _pad40; |
---|
1213 | rtems_unsigned16 pddat; |
---|
1214 | rtems_unsigned8 _pad41[8]; |
---|
1215 | |
---|
1216 | /* |
---|
1217 | * CPM Timers Block |
---|
1218 | */ |
---|
1219 | rtems_unsigned16 tgcr; |
---|
1220 | rtems_unsigned8 _pad42[14]; |
---|
1221 | rtems_unsigned16 tmr1; |
---|
1222 | rtems_unsigned16 tmr2; |
---|
1223 | rtems_unsigned16 trr1; |
---|
1224 | rtems_unsigned16 trr2; |
---|
1225 | rtems_unsigned16 tcr1; |
---|
1226 | rtems_unsigned16 tcr2; |
---|
1227 | rtems_unsigned16 tcn1; |
---|
1228 | rtems_unsigned16 tcn2; |
---|
1229 | rtems_unsigned16 tmr3; |
---|
1230 | rtems_unsigned16 tmr4; |
---|
1231 | rtems_unsigned16 trr3; |
---|
1232 | rtems_unsigned16 trr4; |
---|
1233 | rtems_unsigned16 tcr3; |
---|
1234 | rtems_unsigned16 tcr4; |
---|
1235 | rtems_unsigned16 tcn3; |
---|
1236 | rtems_unsigned16 tcn4; |
---|
1237 | rtems_unsigned16 ter1; |
---|
1238 | rtems_unsigned16 ter2; |
---|
1239 | rtems_unsigned16 ter3; |
---|
1240 | rtems_unsigned16 ter4; |
---|
1241 | rtems_unsigned8 _pad43[8]; |
---|
1242 | |
---|
1243 | /* |
---|
1244 | * CPM Block |
---|
1245 | */ |
---|
1246 | rtems_unsigned16 cpcr; |
---|
1247 | rtems_unsigned16 _pad44; |
---|
1248 | rtems_unsigned16 rccr; |
---|
1249 | rtems_unsigned8 _pad45; |
---|
1250 | rtems_unsigned8 rmds; |
---|
1251 | rtems_unsigned32 rmdr; |
---|
1252 | rtems_unsigned16 rctr1; |
---|
1253 | rtems_unsigned16 rctr2; |
---|
1254 | rtems_unsigned16 rctr3; |
---|
1255 | rtems_unsigned16 rctr4; |
---|
1256 | rtems_unsigned16 _pad46; |
---|
1257 | rtems_unsigned16 rter; |
---|
1258 | rtems_unsigned16 _pad47; |
---|
1259 | rtems_unsigned16 rtmr; |
---|
1260 | rtems_unsigned8 _pad48[0x9f0-0x9dc]; |
---|
1261 | |
---|
1262 | /* |
---|
1263 | * BRG Block |
---|
1264 | */ |
---|
1265 | rtems_unsigned32 brgc1; |
---|
1266 | rtems_unsigned32 brgc2; |
---|
1267 | rtems_unsigned32 brgc3; |
---|
1268 | rtems_unsigned32 brgc4; |
---|
1269 | |
---|
1270 | /* |
---|
1271 | * SCC Block |
---|
1272 | */ |
---|
1273 | m8xxSCCRegisters_t scc1; |
---|
1274 | m8xxSCCRegisters_t scc2; |
---|
1275 | #if defined(mpc860) |
---|
1276 | m8xxSCCRegisters_t scc3; |
---|
1277 | m8xxSCCRegisters_t scc4; |
---|
1278 | #elif defined(mpc821) |
---|
1279 | rtems_unsigned8 _pad72[0xa80-0xa40]; |
---|
1280 | #endif |
---|
1281 | |
---|
1282 | /* |
---|
1283 | * SMC Block |
---|
1284 | */ |
---|
1285 | m8xxSMCRegisters_t smc1; |
---|
1286 | m8xxSMCRegisters_t smc2; |
---|
1287 | |
---|
1288 | /* |
---|
1289 | * SPI Block |
---|
1290 | */ |
---|
1291 | rtems_unsigned16 spmode; |
---|
1292 | rtems_unsigned16 _pad49[2]; |
---|
1293 | rtems_unsigned8 spie; |
---|
1294 | rtems_unsigned8 _pad50; |
---|
1295 | rtems_unsigned16 _pad51; |
---|
1296 | rtems_unsigned8 spim; |
---|
1297 | rtems_unsigned8 _pad52[2]; |
---|
1298 | rtems_unsigned8 spcom; |
---|
1299 | rtems_unsigned16 _pad53[2]; |
---|
1300 | |
---|
1301 | /* |
---|
1302 | * PIP Block |
---|
1303 | */ |
---|
1304 | rtems_unsigned16 pipc; |
---|
1305 | rtems_unsigned16 _pad54; |
---|
1306 | rtems_unsigned16 ptpr; |
---|
1307 | rtems_unsigned32 pbdir; |
---|
1308 | rtems_unsigned32 pbpar; |
---|
1309 | rtems_unsigned16 _pad55; |
---|
1310 | rtems_unsigned16 pbodr; |
---|
1311 | rtems_unsigned32 pbdat; |
---|
1312 | rtems_unsigned32 _pad56[6]; |
---|
1313 | |
---|
1314 | /* |
---|
1315 | * SI Block |
---|
1316 | */ |
---|
1317 | rtems_unsigned32 simode; |
---|
1318 | rtems_unsigned8 sigmr; |
---|
1319 | rtems_unsigned8 _pad57; |
---|
1320 | rtems_unsigned8 sistr; |
---|
1321 | rtems_unsigned8 sicmr; |
---|
1322 | rtems_unsigned32 _pad58; |
---|
1323 | rtems_unsigned32 sicr; |
---|
1324 | rtems_unsigned16 sirp[2]; |
---|
1325 | rtems_unsigned32 _pad59[3]; |
---|
1326 | rtems_unsigned8 _pad60[0xc00-0xb00]; |
---|
1327 | rtems_unsigned8 siram[512]; |
---|
1328 | #if defined(mpc860) |
---|
1329 | /* |
---|
1330 | * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC) |
---|
1331 | */ |
---|
1332 | m8xxFECRegisters_t fec; |
---|
1333 | #elif defined(mpc821) |
---|
1334 | rtems_unsigned8 lcdram[512]; |
---|
1335 | #endif |
---|
1336 | rtems_unsigned8 _pad62[0x2000-0x1000]; |
---|
1337 | |
---|
1338 | /* |
---|
1339 | * Dual-port RAM |
---|
1340 | */ |
---|
1341 | rtems_unsigned8 dpram0[0x200]; /* BD/DATA/UCODE */ |
---|
1342 | rtems_unsigned8 dpram1[0x200]; /* BD/DATA/UCODE */ |
---|
1343 | rtems_unsigned8 dpram2[0x400]; /* BD/DATA/UCODE */ |
---|
1344 | rtems_unsigned8 dpram3[0x600]; /* BD/DATA*/ |
---|
1345 | rtems_unsigned8 dpram4[0x200]; /* BD/DATA/UCODE */ |
---|
1346 | rtems_unsigned8 _pad63[0x3c00-0x3000]; |
---|
1347 | |
---|
1348 | /* When using SCC1 for ethernet, we lose the use of I2C since |
---|
1349 | * their parameters would overlap. Motorola has a microcode |
---|
1350 | * patch to move parameters around so that both can be used |
---|
1351 | * together. It is available on their web site somewhere |
---|
1352 | * under http://www.mot.com/mpc8xx. If ethernet is used on |
---|
1353 | * one (or more) of the other SCCs, then other CPM features |
---|
1354 | * will be unavailable: |
---|
1355 | * SCC2 -> lose SPI |
---|
1356 | * SCC3 -> lose SMC1 |
---|
1357 | * SCC4 -> lose SMC2 |
---|
1358 | * However, Ethernet only works on SCC1 on the 8xx. |
---|
1359 | */ |
---|
1360 | m8xxSCCENparms_t scc1p; |
---|
1361 | rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)]; |
---|
1362 | m8xxMiscParms_t miscp; |
---|
1363 | rtems_unsigned8 _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; |
---|
1364 | m8xxIDMAparms_t idma1p; |
---|
1365 | rtems_unsigned8 _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; |
---|
1366 | |
---|
1367 | m8xxSCCparms_t scc2p; |
---|
1368 | rtems_unsigned8 _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; |
---|
1369 | m8xxSPIparms_t spip; |
---|
1370 | rtems_unsigned8 _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)]; |
---|
1371 | m8xxTimerParms_t tmp; |
---|
1372 | rtems_unsigned8 _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; |
---|
1373 | m8xxIDMAparms_t idma2p; |
---|
1374 | rtems_unsigned8 _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; |
---|
1375 | |
---|
1376 | m8xxSCCparms_t scc3p; /* Not available on MPC821 */ |
---|
1377 | rtems_unsigned8 _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; |
---|
1378 | m8xxSMCparms_t smc1p; |
---|
1379 | rtems_unsigned8 _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; |
---|
1380 | m8xxDSPparms_t dsp1p; |
---|
1381 | rtems_unsigned8 _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; |
---|
1382 | |
---|
1383 | m8xxSCCparms_t scc4p; /* Not available on MPC821 */ |
---|
1384 | rtems_unsigned8 _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; |
---|
1385 | m8xxSMCparms_t smc2p; |
---|
1386 | rtems_unsigned8 _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)]; |
---|
1387 | m8xxDSPparms_t dsp2p; |
---|
1388 | rtems_unsigned8 _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)]; |
---|
1389 | } m8xx_t; |
---|
1390 | |
---|
1391 | extern volatile m8xx_t m8xx; |
---|
1392 | |
---|
1393 | #ifdef __cplusplus |
---|
1394 | } |
---|
1395 | #endif |
---|
1396 | |
---|
1397 | #endif /* ASM */ |
---|
1398 | |
---|
1399 | #endif /* __MPC8xx_h */ |
---|