4.104.114.84.95
Last change
on this file since 73b5bd5d was
11c2382,
checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/01/04 at 10:07:38
|
2004-04-01 Ralf Corsepius <ralf_corsepius@…>
- mpc505/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc6xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc6xx/mmu/mmuAsm.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc8260/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc8xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
- ppc403/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc5xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
- mpc8260/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
- mpc8xx/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
- ppc403/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
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-
Property mode set to
100644
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File size:
1.2 KB
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Line | |
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1 | /* |
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2 | * asm_utils.s |
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3 | * |
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4 | * $Id$ |
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5 | * |
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6 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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7 | * |
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8 | * This file contains the low-level support for moving exception |
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9 | * exception code to appropriate location. |
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10 | * |
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11 | */ |
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12 | |
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13 | #include <rtems/asm.h> |
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14 | #include <rtems/score/cpu.h> |
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15 | #include <libcpu/io.h> |
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16 | |
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17 | .globl codemove |
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18 | codemove: |
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19 | .type codemove,@function |
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20 | /* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */ |
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21 | cmplw cr1,r3,r4 |
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22 | addi r0,r5,3 |
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23 | srwi. r0,r0,2 |
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24 | beq cr1,4f /* In place copy is not necessary */ |
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25 | beq 7f /* Protect against 0 count */ |
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26 | mtctr r0 |
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27 | bge cr1,2f |
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28 | |
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29 | la r8,-4(r4) |
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30 | la r7,-4(r3) |
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31 | 1: lwzu r0,4(r8) |
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32 | stwu r0,4(r7) |
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33 | bdnz 1b |
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34 | b 4f |
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35 | |
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36 | 2: slwi r0,r0,2 |
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37 | add r8,r4,r0 |
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38 | add r7,r3,r0 |
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39 | 3: lwzu r0,-4(r8) |
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40 | stwu r0,-4(r7) |
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41 | bdnz 3b |
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42 | |
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43 | /* Now flush the cache: note that we must start from a cache aligned |
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44 | * address. Otherwise we might miss one cache line. |
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45 | */ |
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46 | 4: cmpwi r6,0 |
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47 | add r5,r3,r5 |
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48 | beq 7f /* Always flush prefetch queue in any case */ |
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49 | subi r0,r6,1 |
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50 | andc r3,r3,r0 |
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51 | mr r4,r3 |
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52 | 5: cmplw r4,r5 |
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53 | dcbst 0,r4 |
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54 | add r4,r4,r6 |
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55 | blt 5b |
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56 | sync /* Wait for all dcbst to complete on bus */ |
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57 | mr r4,r3 |
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58 | 6: cmplw r4,r5 |
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59 | icbi 0,r4 |
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60 | add r4,r4,r6 |
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61 | blt 6b |
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62 | 7: sync /* Wait for all icbi to complete on bus */ |
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63 | isync |
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64 | blr |
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