1 | /* |
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2 | * General Serial I/O functions. |
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3 | * |
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4 | * This file contains the functions for performing serial I/O. |
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5 | * The actual system calls (console_*) should be in the BSP part |
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6 | * of the source tree. That way different BSPs can use whichever |
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7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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8 | * this file, and it caused problems with one BSP using SCC2 |
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9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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10 | * |
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11 | * On-chip resources used: |
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12 | * resource minor note |
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13 | * SMC1 0 |
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14 | * SMC2 1 |
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15 | * SCC1 2 N/A. Hardwired as ethernet port |
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16 | * SCC2 3 |
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17 | * SCC3 4 |
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18 | * SCC4 5 |
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19 | * BRG1 |
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20 | * BRG2 |
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21 | * BRG3 |
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22 | * BRG4 |
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23 | * Author: Jay Monkman (jmonkman@frasca.com) |
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24 | * Copyright (C) 1998 by Frasca International, Inc. |
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25 | * |
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26 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: |
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27 | * W. Eric Norum |
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28 | * Saskatchewan Accelerator Laboratory |
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29 | * University of Saskatchewan |
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30 | * Saskatoon, Saskatchewan, CANADA |
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31 | * eric@skatter.usask.ca |
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32 | * |
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33 | * COPYRIGHT (c) 1989-1998. |
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34 | * On-Line Applications Research Corporation (OAR). |
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35 | * |
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36 | * Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca> |
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37 | * and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> |
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38 | * Copyright (c) 1999, National Research Council of Canada |
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39 | * |
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40 | * The license and distribution terms for this file may be |
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41 | * found in the file LICENSE in this distribution or at |
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42 | * |
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43 | * http://www.rtems.com/license/LICENSE. |
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44 | * |
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45 | * $Id$ |
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46 | */ |
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47 | |
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48 | #include <rtems.h> |
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49 | #include <rtems/libio.h> |
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50 | #include <mpc8xx.h> |
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51 | #include <mpc8xx/console.h> |
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52 | #include <mpc8xx/cpm.h> |
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53 | #include <stdlib.h> |
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54 | #include <unistd.h> |
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55 | #include <termios.h> |
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56 | #include <bsp/irq.h> |
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57 | #include <rtems/bspIo.h> /* for printk */ |
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58 | |
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59 | int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine); |
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60 | extern rtems_cpu_table Cpu_table; |
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61 | |
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62 | /* BSP supplied routine */ |
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63 | extern int mbx8xx_console_get_configuration(); |
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64 | |
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65 | /* |
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66 | * Interrupt-driven input buffer |
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67 | */ |
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68 | #define RXBUFSIZE 16 |
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69 | |
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70 | /* |
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71 | * I/O buffers and pointers to buffer descriptors. |
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72 | * Currently, single buffered input is done. This will work only |
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73 | * if the Rx interrupts are serviced quickly. |
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74 | * |
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75 | * TODO: Add a least double buffering for safety. |
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76 | */ |
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77 | static volatile char rxBuf[NUM_PORTS][RXBUFSIZE]; |
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78 | static volatile char txBuf[NUM_PORTS]; |
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79 | |
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80 | /* SCC/SMC buffer descriptors */ |
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81 | static volatile m8xxBufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS]; |
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82 | |
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83 | /* Used to track the usage of the baud rate generators */ |
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84 | static unsigned long brg_spd[4]; |
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85 | static char brg_used[4]; |
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86 | |
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87 | /* Used to track termios private data for callbacks */ |
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88 | struct rtems_termios_tty *ttyp[NUM_PORTS]; |
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89 | |
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90 | /* |
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91 | * Device-specific routines |
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92 | */ |
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93 | static int m8xx_get_brg_cd(int); |
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94 | static unsigned char m8xx_get_brg_clk(int); |
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95 | void m8xx_console_reserve_resources(rtems_configuration_table *); |
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96 | static int m8xx_smc_set_attributes(int, const struct termios*); |
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97 | static int m8xx_scc_set_attributes(int, const struct termios*); |
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98 | static void m8xx_smc1_interrupt_handler(void); |
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99 | static void m8xx_smc2_interrupt_handler(void); |
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100 | static void m8xx_scc2_interrupt_handler(void); |
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101 | #if defined(mpc860) |
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102 | static void m8xx_scc3_interrupt_handler(void); |
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103 | static void m8xx_scc4_interrupt_handler(void); |
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104 | #endif |
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105 | |
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106 | /* |
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107 | * Compute baud-rate-generator configuration register value |
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108 | */ |
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109 | static int |
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110 | m8xx_get_brg_cd (int baud) |
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111 | { |
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112 | int divisor; |
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113 | int div16 = 0; |
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114 | |
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115 | divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud; |
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116 | if (divisor > 4096) { |
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117 | div16 = 1; |
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118 | divisor = (divisor + 8) / 16; |
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119 | } |
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120 | return M8xx_BRG_EN | M8xx_BRG_EXTC_BRGCLK | |
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121 | ((divisor - 1) << 1) | div16; |
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122 | } |
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123 | |
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124 | |
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125 | /* |
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126 | * This function will fail if more that 4 baud rates have been selected |
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127 | * at any time since the OS started. It needs to be fixed. FIXME |
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128 | */ |
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129 | static unsigned |
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130 | char m8xx_get_brg_clk(int baud) |
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131 | { |
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132 | int i; |
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133 | |
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134 | /* first try to find a BRG that is already at the right speed */ |
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135 | for ( i = 0; i < 4; i++ ) { |
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136 | if ( brg_spd[i] == baud ) { |
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137 | break; |
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138 | } |
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139 | } |
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140 | |
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141 | if ( i == 4 ) { /* I guess we didn't find one */ |
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142 | for ( i = 0; i < 4; i++ ) { |
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143 | if ( brg_used[i] == 0 ) { |
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144 | break; |
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145 | } |
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146 | } |
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147 | } |
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148 | if (i != 4) { |
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149 | brg_used[i]++; |
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150 | brg_spd[i]=baud; |
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151 | switch (i) { |
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152 | case 0: |
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153 | m8xx.brgc1 = M8xx_BRG_RST; |
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154 | m8xx.brgc1 = m8xx_get_brg_cd(baud); |
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155 | break; |
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156 | case 1: |
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157 | m8xx.brgc2 = M8xx_BRG_RST; |
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158 | m8xx.brgc2 = m8xx_get_brg_cd(baud); |
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159 | break; |
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160 | case 2: |
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161 | m8xx.brgc3 = M8xx_BRG_RST; |
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162 | m8xx.brgc3 = m8xx_get_brg_cd(baud); |
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163 | break; |
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164 | case 3: |
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165 | m8xx.brgc4 = M8xx_BRG_RST; |
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166 | m8xx.brgc4 = m8xx_get_brg_cd(baud); |
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167 | break; |
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168 | } |
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169 | return i; |
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170 | } |
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171 | |
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172 | else |
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173 | return 0xff; |
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174 | } |
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175 | |
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176 | |
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177 | /* |
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178 | * Hardware-dependent portion of tcsetattr(). |
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179 | */ |
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180 | static int |
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181 | m8xx_smc_set_attributes (int minor, const struct termios *t) |
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182 | { |
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183 | int baud, brg=0, csize=0, ssize, psize; |
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184 | uint16_t clen=0, cstopb, parenb, parodd, cread; |
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185 | |
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186 | /* Baud rate */ |
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187 | switch (t->c_cflag & CBAUD) { |
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188 | default: baud = -1; break; |
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189 | case B50: baud = 50; break; |
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190 | case B75: baud = 75; break; |
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191 | case B110: baud = 110; break; |
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192 | case B134: baud = 134; break; |
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193 | case B150: baud = 150; break; |
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194 | case B200: baud = 200; break; |
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195 | case B300: baud = 300; break; |
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196 | case B600: baud = 600; break; |
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197 | case B1200: baud = 1200; break; |
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198 | case B1800: baud = 1800; break; |
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199 | case B2400: baud = 2400; break; |
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200 | case B4800: baud = 4800; break; |
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201 | case B9600: baud = 9600; break; |
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202 | case B19200: baud = 19200; break; |
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203 | case B38400: baud = 38400; break; |
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204 | case B57600: baud = 57600; break; |
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205 | case B115200: baud = 115200; break; |
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206 | case B230400: baud = 230400; break; |
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207 | case B460800: baud = 460800; break; |
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208 | } |
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209 | if (baud > 0) |
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210 | brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ |
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211 | /* at least 2 ports will be the same */ |
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212 | |
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213 | /* Number of data bits */ |
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214 | switch ( t->c_cflag & CSIZE ) { |
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215 | case CS5: csize = 5; break; |
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216 | case CS6: csize = 6; break; |
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217 | case CS7: csize = 7; break; |
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218 | case CS8: csize = 8; break; |
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219 | } |
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220 | |
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221 | /* Stop bits */ |
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222 | if ( t->c_cflag & CSTOPB ) { |
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223 | cstopb = 0x0400; /* Two stop bits */ |
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224 | ssize = 2; |
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225 | } else { |
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226 | cstopb = 0x0000; /* One stop bit */ |
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227 | ssize = 1; |
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228 | } |
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229 | |
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230 | /* Parity */ |
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231 | if ( t->c_cflag & PARENB ) { |
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232 | parenb = 0x0200; /* Parity enabled on Tx and Rx */ |
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233 | psize = 1; |
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234 | } else { |
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235 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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236 | psize = 0; |
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237 | } |
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238 | |
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239 | if ( t->c_cflag & PARODD ) |
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240 | parodd = 0x0000; /* Odd parity */ |
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241 | else |
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242 | parodd = 0x0100; |
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243 | |
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244 | /* |
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245 | * Character Length = start + data + parity + stop - 1 |
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246 | */ |
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247 | switch ( 1 + csize + psize + ssize - 1 ) { |
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248 | case 6: clen = 0x3000; break; |
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249 | case 7: clen = 0x3800; break; |
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250 | case 8: clen = 0x4000; break; |
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251 | case 9: clen = 0x4800; break; |
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252 | case 10: clen = 0x5000; break; |
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253 | case 11: clen = 0x5800; break; |
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254 | } |
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255 | |
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256 | if ( t->c_cflag & CREAD ) |
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257 | cread = 0x0023; /* UART normal operation, enable Rx and Tx */ |
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258 | else |
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259 | cread = 0x0021; /* UART normal operation, enable Tx */ |
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260 | |
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261 | /* Write the SIMODE/SMCMR registers */ |
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262 | switch (minor) { |
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263 | case SMC1_MINOR: |
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264 | m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) ); |
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265 | m8xx.smc1.smcmr = clen | cstopb | parenb | parodd | cread; |
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266 | break; |
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267 | case SMC2_MINOR: |
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268 | m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) ); |
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269 | m8xx.smc2.smcmr = clen | cstopb | parenb | parodd | cread; |
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270 | break; |
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271 | } |
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272 | return 0; |
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273 | } |
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274 | |
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275 | |
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276 | static int |
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277 | m8xx_scc_set_attributes (int minor, const struct termios *t) |
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278 | { |
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279 | int baud, brg=0; |
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280 | uint16_t csize=0, cstopb, parenb, parodd; |
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281 | |
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282 | /* Baud rate */ |
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283 | switch (t->c_cflag & CBAUD) { |
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284 | default: baud = -1; break; |
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285 | case B50: baud = 50; break; |
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286 | case B75: baud = 75; break; |
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287 | case B110: baud = 110; break; |
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288 | case B134: baud = 134; break; |
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289 | case B150: baud = 150; break; |
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290 | case B200: baud = 200; break; |
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291 | case B300: baud = 300; break; |
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292 | case B600: baud = 600; break; |
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293 | case B1200: baud = 1200; break; |
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294 | case B1800: baud = 1800; break; |
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295 | case B2400: baud = 2400; break; |
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296 | case B4800: baud = 4800; break; |
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297 | case B9600: baud = 9600; break; |
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298 | case B19200: baud = 19200; break; |
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299 | case B38400: baud = 38400; break; |
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300 | case B57600: baud = 57600; break; |
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301 | case B115200: baud = 115200; break; |
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302 | case B230400: baud = 230400; break; |
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303 | case B460800: baud = 460800; break; |
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304 | } |
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305 | if (baud > 0) |
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306 | brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ |
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307 | /* at least 2 ports will be the same */ |
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308 | /* Write the SICR register below */ |
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309 | |
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310 | /* Number of data bits */ |
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311 | switch ( t->c_cflag & CSIZE ) { |
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312 | case CS5: csize = 0x0000; break; |
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313 | case CS6: csize = 0x1000; break; |
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314 | case CS7: csize = 0x2000; break; |
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315 | case CS8: csize = 0x3000; break; |
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316 | } |
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317 | |
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318 | /* Stop bits */ |
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319 | if ( t->c_cflag & CSTOPB ) |
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320 | cstopb = 0x4000; /* Two stop bits */ |
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321 | else |
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322 | cstopb = 0x0000; /* One stop bit */ |
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323 | |
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324 | /* Parity */ |
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325 | if ( t->c_cflag & PARENB ) |
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326 | parenb = 0x0010; /* Parity enabled on Tx and Rx */ |
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327 | else |
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328 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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329 | |
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330 | if ( t->c_cflag & PARODD ) |
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331 | parodd = 0x0000; /* Odd parity */ |
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332 | else |
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333 | parodd = 0x000a; |
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334 | |
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335 | /* Write the SICR/PSMR Registers */ |
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336 | switch (minor) { |
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337 | case SCC2_MINOR: |
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338 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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339 | m8xx.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc2.psmr & 0x8fe0) ); |
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340 | break; |
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341 | #if defined(mpc860) |
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342 | case SCC3_MINOR: |
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343 | m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) ); |
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344 | m8xx.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc3.psmr & 0x8fe0) ); |
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345 | break; |
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346 | case SCC4_MINOR: |
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347 | m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) ); |
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348 | m8xx.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc4.psmr & 0x8fe0) ); |
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349 | break; |
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350 | #endif |
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351 | } |
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352 | |
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353 | return 0; |
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354 | } |
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355 | |
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356 | |
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357 | int |
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358 | m8xx_uart_setAttributes( |
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359 | int minor, |
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360 | const struct termios *t |
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361 | ) |
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362 | { |
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363 | /* |
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364 | * Check that port number is valid |
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365 | */ |
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366 | if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) |
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367 | return 0; |
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368 | |
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369 | switch (minor) { |
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370 | case SMC1_MINOR: |
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371 | case SMC2_MINOR: |
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372 | return m8xx_smc_set_attributes( minor, t ); |
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373 | |
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374 | case SCC2_MINOR: |
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375 | case SCC3_MINOR: |
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376 | case SCC4_MINOR: |
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377 | return m8xx_scc_set_attributes( minor, t ); |
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378 | } |
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379 | return 0; |
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380 | } |
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381 | |
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382 | |
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383 | /* |
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384 | * Interrupt handlers |
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385 | */ |
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386 | static void m8xx_scc2_interrupt_handler () |
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387 | { |
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388 | int nb_overflow; |
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389 | |
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390 | /* |
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391 | * Buffer received? |
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392 | */ |
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393 | if ((m8xx.scc2.sccm & M8xx_SCCE_RX) && (m8xx.scc2.scce & M8xx_SCCE_RX)) { |
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394 | m8xx.scc2.scce = M8xx_SCCE_RX; /* Clear the event */ |
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395 | |
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396 | |
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397 | /* Check that the buffer is ours */ |
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398 | if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
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399 | rtems_cache_invalidate_multiple_data_lines( |
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400 | (const void *) RxBd[SCC2_MINOR]->buffer, |
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401 | RxBd[SCC2_MINOR]->length ); |
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402 | nb_overflow = rtems_termios_enqueue_raw_characters( |
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403 | (void *)ttyp[SCC2_MINOR], |
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404 | (char *)RxBd[SCC2_MINOR]->buffer, |
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405 | (int)RxBd[SCC2_MINOR]->length ); |
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406 | RxBd[SCC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
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407 | M8xx_BD_INTERRUPT; |
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408 | } |
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409 | } |
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410 | |
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411 | /* |
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412 | * Buffer transmitted? |
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413 | */ |
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414 | if (m8xx.scc2.scce & M8xx_SCCE_TX) { |
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415 | m8xx.scc2.scce = M8xx_SCCE_TX; /* Clear the event */ |
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416 | |
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417 | /* Check that the buffer is ours */ |
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418 | if ((TxBd[SCC2_MINOR]->status & M8xx_BD_READY) == 0) |
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419 | rtems_termios_dequeue_characters ( |
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420 | (void *)ttyp[SCC2_MINOR], |
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421 | (int)TxBd[SCC2_MINOR]->length); |
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422 | } |
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423 | } |
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424 | |
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425 | |
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426 | #ifdef mpc860 |
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427 | static void |
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428 | m8xx_scc3_interrupt_handler (void) |
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429 | { |
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430 | int nb_overflow; |
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431 | |
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432 | /* |
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433 | * Buffer received? |
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434 | */ |
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435 | if ((m8xx.scc3.sccm & M8xx_SCCE_RX) && (m8xx.scc3.scce & M8xx_SCCE_RX)) { |
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436 | m8xx.scc3.scce = M8xx_SCCE_RX; /* Clear the event */ |
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437 | |
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438 | |
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439 | /* Check that the buffer is ours */ |
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440 | if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
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441 | rtems_cache_invalidate_multiple_data_lines( |
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442 | (const void *) RxBd[SCC3_MINOR]->buffer, |
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443 | RxBd[SCC3_MINOR]->length ); |
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444 | nb_overflow = rtems_termios_enqueue_raw_characters( |
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445 | (void *)ttyp[SCC3_MINOR], |
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446 | (char *)RxBd[SCC3_MINOR]->buffer, |
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447 | (int)RxBd[SCC3_MINOR]->length ); |
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448 | RxBd[SCC3_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
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449 | M8xx_BD_INTERRUPT; |
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450 | } |
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451 | } |
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452 | |
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453 | /* |
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454 | * Buffer transmitted? |
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455 | */ |
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456 | if (m8xx.scc3.scce & M8xx_SCCE_TX) { |
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457 | m8xx.scc3.scce = M8xx_SCCE_TX; /* Clear the event */ |
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458 | |
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459 | /* Check that the buffer is ours */ |
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460 | if ((TxBd[SCC3_MINOR]->status & M8xx_BD_READY) == 0) |
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461 | rtems_termios_dequeue_characters ( |
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462 | (void *)ttyp[SCC3_MINOR], |
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463 | (int)TxBd[SCC3_MINOR]->length); |
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464 | } |
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465 | } |
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466 | |
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467 | |
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468 | static void |
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469 | m8xx_scc4_interrupt_handler (void) |
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470 | { |
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471 | int nb_overflow; |
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472 | |
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473 | /* |
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474 | * Buffer received? |
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475 | */ |
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476 | if ((m8xx.scc4.sccm & M8xx_SCCE_RX) && (m8xx.scc4.scce & M8xx_SCCE_RX)) { |
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477 | m8xx.scc4.scce = M8xx_SCCE_RX; /* Clear the event */ |
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478 | |
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479 | |
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480 | /* Check that the buffer is ours */ |
---|
481 | if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
482 | rtems_cache_invalidate_multiple_data_lines( |
---|
483 | (const void *) RxBd[SCC4_MINOR]->buffer, |
---|
484 | RxBd[SCC4_MINOR]->length ); |
---|
485 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
486 | (void *)ttyp[SCC4_MINOR], |
---|
487 | (char *)RxBd[SCC4_MINOR]->buffer, |
---|
488 | (int)RxBd[SCC4_MINOR]->length ); |
---|
489 | RxBd[SCC4_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
490 | M8xx_BD_INTERRUPT; |
---|
491 | } |
---|
492 | } |
---|
493 | |
---|
494 | /* |
---|
495 | * Buffer transmitted? |
---|
496 | */ |
---|
497 | if (m8xx.scc4.scce & M8xx_SCCE_TX) { |
---|
498 | m8xx.scc4.scce = M8xx_SCCE_TX; /* Clear the event */ |
---|
499 | |
---|
500 | /* Check that the buffer is ours */ |
---|
501 | if ((TxBd[SCC4_MINOR]->status & M8xx_BD_READY) == 0) |
---|
502 | rtems_termios_dequeue_characters ( |
---|
503 | (void *)ttyp[SCC4_MINOR], |
---|
504 | (int)TxBd[SCC4_MINOR]->length); |
---|
505 | } |
---|
506 | } |
---|
507 | #endif |
---|
508 | |
---|
509 | static void |
---|
510 | m8xx_smc1_interrupt_handler (void) |
---|
511 | { |
---|
512 | int nb_overflow; |
---|
513 | |
---|
514 | /* |
---|
515 | * Buffer received? |
---|
516 | */ |
---|
517 | if (m8xx.smc1.smce & M8xx_SMCE_RX) { |
---|
518 | m8xx.smc1.smce = M8xx_SMCE_RX; /* Clear the event */ |
---|
519 | |
---|
520 | |
---|
521 | /* Check that the buffer is ours */ |
---|
522 | if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
523 | rtems_cache_invalidate_multiple_data_lines( |
---|
524 | (const void *) RxBd[SMC1_MINOR]->buffer, |
---|
525 | RxBd[SMC1_MINOR]->length ); |
---|
526 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
527 | (void *)ttyp[SMC1_MINOR], |
---|
528 | (char *)RxBd[SMC1_MINOR]->buffer, |
---|
529 | (int)RxBd[SMC1_MINOR]->length ); |
---|
530 | RxBd[SMC1_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
531 | M8xx_BD_INTERRUPT; |
---|
532 | } |
---|
533 | } |
---|
534 | |
---|
535 | /* |
---|
536 | * Buffer transmitted? |
---|
537 | */ |
---|
538 | if (m8xx.smc1.smce & M8xx_SMCE_TX) { |
---|
539 | m8xx.smc1.smce = M8xx_SMCE_TX; /* Clear the event */ |
---|
540 | |
---|
541 | /* Check that the buffer is ours */ |
---|
542 | if ((TxBd[SMC1_MINOR]->status & M8xx_BD_READY) == 0) |
---|
543 | rtems_termios_dequeue_characters ( |
---|
544 | (void *)ttyp[SMC1_MINOR], |
---|
545 | (int)TxBd[SMC1_MINOR]->length); |
---|
546 | } |
---|
547 | } |
---|
548 | |
---|
549 | |
---|
550 | static void |
---|
551 | m8xx_smc2_interrupt_handler (void) |
---|
552 | { |
---|
553 | int nb_overflow; |
---|
554 | |
---|
555 | /* |
---|
556 | * Buffer received? |
---|
557 | */ |
---|
558 | if (m8xx.smc2.smce & M8xx_SMCE_RX) { |
---|
559 | m8xx.smc2.smce = M8xx_SMCE_RX; /* Clear the event */ |
---|
560 | |
---|
561 | |
---|
562 | /* Check that the buffer is ours */ |
---|
563 | if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
564 | rtems_cache_invalidate_multiple_data_lines( |
---|
565 | (const void *) RxBd[SMC2_MINOR]->buffer, |
---|
566 | RxBd[SMC2_MINOR]->length ); |
---|
567 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
568 | (void *)ttyp[SMC2_MINOR], |
---|
569 | (char *)RxBd[SMC2_MINOR]->buffer, |
---|
570 | (int)RxBd[SMC2_MINOR]->length ); |
---|
571 | RxBd[SMC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
572 | M8xx_BD_INTERRUPT; |
---|
573 | } |
---|
574 | } |
---|
575 | |
---|
576 | /* |
---|
577 | * Buffer transmitted? |
---|
578 | */ |
---|
579 | if (m8xx.smc2.smce & M8xx_SMCE_TX) { |
---|
580 | m8xx.smc2.smce = M8xx_SMCE_TX; /* Clear the event */ |
---|
581 | |
---|
582 | /* Check that the buffer is ours */ |
---|
583 | if ((TxBd[SMC2_MINOR]->status & M8xx_BD_READY) == 0) |
---|
584 | rtems_termios_dequeue_characters ( |
---|
585 | (void *)ttyp[SMC2_MINOR], |
---|
586 | (int)TxBd[SMC2_MINOR]->length); |
---|
587 | } |
---|
588 | } |
---|
589 | |
---|
590 | void m8xx_scc_enable(const rtems_irq_connect_data* ptr) |
---|
591 | { |
---|
592 | volatile m8xxSCCRegisters_t *sccregs = 0; |
---|
593 | switch (ptr->name) { |
---|
594 | #if defined(mpc860) |
---|
595 | case BSP_CPM_IRQ_SCC4 : |
---|
596 | sccregs = &m8xx.scc4; |
---|
597 | break; |
---|
598 | case BSP_CPM_IRQ_SCC3 : |
---|
599 | sccregs = &m8xx.scc3; |
---|
600 | break; |
---|
601 | #endif |
---|
602 | case BSP_CPM_IRQ_SCC2 : |
---|
603 | sccregs = &m8xx.scc2; |
---|
604 | break; |
---|
605 | case BSP_CPM_IRQ_SCC1 : |
---|
606 | sccregs = &m8xx.scc1; |
---|
607 | break; |
---|
608 | default: |
---|
609 | break; |
---|
610 | } |
---|
611 | sccregs->sccm = 3; |
---|
612 | } |
---|
613 | |
---|
614 | void m8xx_scc_disable(const rtems_irq_connect_data* ptr) |
---|
615 | { |
---|
616 | volatile m8xxSCCRegisters_t *sccregs = 0; |
---|
617 | switch (ptr->name) { |
---|
618 | #if defined(mpc860) |
---|
619 | case BSP_CPM_IRQ_SCC4 : |
---|
620 | sccregs = &m8xx.scc4; |
---|
621 | break; |
---|
622 | case BSP_CPM_IRQ_SCC3 : |
---|
623 | sccregs = &m8xx.scc3; |
---|
624 | break; |
---|
625 | #endif |
---|
626 | case BSP_CPM_IRQ_SCC2 : |
---|
627 | sccregs = &m8xx.scc2; |
---|
628 | break; |
---|
629 | case BSP_CPM_IRQ_SCC1 : |
---|
630 | sccregs = &m8xx.scc1; |
---|
631 | break; |
---|
632 | default: |
---|
633 | break; |
---|
634 | } |
---|
635 | sccregs->sccm &= (~3); |
---|
636 | } |
---|
637 | |
---|
638 | int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) |
---|
639 | { |
---|
640 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
641 | } |
---|
642 | |
---|
643 | static rtems_irq_connect_data consoleIrqData; |
---|
644 | |
---|
645 | void |
---|
646 | m8xx_uart_scc_initialize (int minor) |
---|
647 | { |
---|
648 | unsigned char brg; |
---|
649 | volatile m8xxSCCparms_t *sccparms = 0; |
---|
650 | volatile m8xxSCCRegisters_t *sccregs = 0; |
---|
651 | |
---|
652 | /* |
---|
653 | * Check that minor number is valid |
---|
654 | */ |
---|
655 | if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) |
---|
656 | return; |
---|
657 | |
---|
658 | /* Get the sicr clock source bit values for 9600 bps */ |
---|
659 | brg = m8xx_get_brg_clk(9600); |
---|
660 | |
---|
661 | /* |
---|
662 | * Allocate buffer descriptors |
---|
663 | */ |
---|
664 | RxBd[minor] = m8xx_bd_allocate(1); |
---|
665 | TxBd[minor] = m8xx_bd_allocate(1); |
---|
666 | |
---|
667 | /* |
---|
668 | * Get the address of the parameter RAM for the specified port, |
---|
669 | * configure I/O port A,C & D and put SMC in NMSI mode, connect |
---|
670 | * the SCC to the appropriate BRG. |
---|
671 | * |
---|
672 | * SCC2 TxD is shared with port A bit 12 |
---|
673 | * SCC2 RxD is shared with port A bit 13 |
---|
674 | * SCC1 TxD is shared with port A bit 14 |
---|
675 | * SCC1 RxD is shared with port A bit 15 |
---|
676 | * SCC4 DCD is shared with port C bit 4 |
---|
677 | * SCC4 CTS is shared with port C bit 5 |
---|
678 | * SCC3 DCD is shared with port C bit 6 |
---|
679 | * SCC3 CTS is shared with port C bit 7 |
---|
680 | * SCC2 DCD is shared with port C bit 8 |
---|
681 | * SCC2 CTS is shared with port C bit 9 |
---|
682 | * SCC1 DCD is shared with port C bit 10 |
---|
683 | * SCC1 CTS is shared with port C bit 11 |
---|
684 | * SCC2 RTS is shared with port C bit 14 |
---|
685 | * SCC1 RTS is shared with port C bit 15 |
---|
686 | * SCC4 RTS is shared with port D bit 6 |
---|
687 | * SCC3 RTS is shared with port D bit 7 |
---|
688 | * SCC4 TxD is shared with port D bit 8 |
---|
689 | * SCC4 RxD is shared with port D bit 9 |
---|
690 | * SCC3 TxD is shared with port D bit 10 |
---|
691 | * SCC3 RxD is shared with port D bit 11 |
---|
692 | */ |
---|
693 | switch (minor) { |
---|
694 | case SCC2_MINOR: |
---|
695 | sccparms = &m8xx.scc2p; |
---|
696 | sccregs = &m8xx.scc2; |
---|
697 | |
---|
698 | m8xx.papar |= 0x000C; /* PA12 & PA13 are dedicated peripheral pins */ |
---|
699 | m8xx.padir &= ~0x000C; /* PA13 & PA12 must not drive the UART lines */ |
---|
700 | m8xx.paodr &= ~0x000C; /* PA12 & PA13 are not open drain */ |
---|
701 | m8xx.pcpar |= 0x0002; /* PC14 is SCC2 RTS */ |
---|
702 | m8xx.pcpar &= ~0x00C0; /* PC8 & PC9 are SCC2 DCD and CTS */ |
---|
703 | m8xx.pcdir &= ~0x00C2; /* PC8, PC9 & PC14 must not drive the UART lines */ |
---|
704 | m8xx.pcso |= 0x00C0; /* Enable DCD and CTS inputs */ |
---|
705 | |
---|
706 | m8xx.sicr &= 0xFFFF00FF; /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */ |
---|
707 | m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */ |
---|
708 | break; |
---|
709 | |
---|
710 | #ifdef mpc860 |
---|
711 | case SCC3_MINOR: |
---|
712 | sccparms = &m8xx.scc3p; |
---|
713 | sccregs = &m8xx.scc3; |
---|
714 | |
---|
715 | m8xx.pcpar &= ~0x0300; /* PC6 & PC7 are SCC3 DCD and CTS */ |
---|
716 | m8xx.pcdir &= ~0x0300; /* PC6 & PC7 must not drive the UART lines */ |
---|
717 | m8xx.pcso |= 0x0300; /* Enable DCD and CTS inputs */ |
---|
718 | m8xx.pdpar |= 0x0130; /* PD7, PD10 & PD11 are dedicated peripheral pins */ |
---|
719 | |
---|
720 | m8xx.sicr &= 0xFF00FFFF; /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */ |
---|
721 | m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */ |
---|
722 | break; |
---|
723 | |
---|
724 | case SCC4_MINOR: |
---|
725 | sccparms = &m8xx.scc4p; |
---|
726 | sccregs = &m8xx.scc4; |
---|
727 | |
---|
728 | m8xx.pcpar &= ~0x0C00; /* PC4 & PC5 are SCC4 DCD and CTS */ |
---|
729 | m8xx.pcdir &= ~0x0C00; /* PC4 & PC5 must not drive the UART lines */ |
---|
730 | m8xx.pcso |= 0x0C00; /* Enable DCD and CTS inputs */ |
---|
731 | m8xx.pdpar |= 0x02C0; /* PD6, PD8 & PD9 are dedicated peripheral pins */ |
---|
732 | |
---|
733 | m8xx.sicr &= 0x00FFFFFF; /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */ |
---|
734 | m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */ |
---|
735 | break; |
---|
736 | #endif |
---|
737 | } |
---|
738 | |
---|
739 | /* |
---|
740 | * Set up SDMA |
---|
741 | */ |
---|
742 | m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */ |
---|
743 | |
---|
744 | /* |
---|
745 | * Set up the SCC parameter RAM. |
---|
746 | */ |
---|
747 | sccparms->rbase = (char *)RxBd[minor] - (char *)&m8xx; |
---|
748 | sccparms->tbase = (char *)TxBd[minor] - (char *)&m8xx; |
---|
749 | |
---|
750 | sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); |
---|
751 | sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); |
---|
752 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
753 | sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
754 | else |
---|
755 | sccparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
756 | sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
757 | sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
758 | |
---|
759 | sccparms->un.uart.parec = 0; /* Clear parity error counter */ |
---|
760 | sccparms->un.uart.frmec = 0; /* Clear framing error counter */ |
---|
761 | sccparms->un.uart.nosec = 0; /* Clear noise counter */ |
---|
762 | sccparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
763 | |
---|
764 | sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */ |
---|
765 | sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */ |
---|
766 | sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */ |
---|
767 | |
---|
768 | sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */ |
---|
769 | sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */ |
---|
770 | sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */ |
---|
771 | sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */ |
---|
772 | sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */ |
---|
773 | sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */ |
---|
774 | sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */ |
---|
775 | sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */ |
---|
776 | |
---|
777 | |
---|
778 | sccparms->un.uart.rccm = 0xc0ff; /* No masking */ |
---|
779 | |
---|
780 | /* |
---|
781 | * Set up the Receive Buffer Descriptor |
---|
782 | */ |
---|
783 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
784 | RxBd[minor]->length = 0; |
---|
785 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
786 | |
---|
787 | /* |
---|
788 | * Setup the Transmit Buffer Descriptor |
---|
789 | */ |
---|
790 | TxBd[minor]->status = M8xx_BD_WRAP; |
---|
791 | |
---|
792 | /* |
---|
793 | * Set up SCCx general and protocol-specific mode registers |
---|
794 | */ |
---|
795 | sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */ |
---|
796 | sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/ |
---|
797 | sccregs->scce = ~0; /* Clear any pending event */ |
---|
798 | sccregs->sccm = 0; /* Mask all interrupt/event sources */ |
---|
799 | sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit, |
---|
800 | 8 data bits, no parity */ |
---|
801 | sccregs->dsr = 0x7E7E; /* No fractional stop bits */ |
---|
802 | sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */ |
---|
803 | |
---|
804 | /* |
---|
805 | * Initialize the Rx and Tx with the new parameters. |
---|
806 | */ |
---|
807 | switch (minor) { |
---|
808 | case SCC2_MINOR: |
---|
809 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC2); |
---|
810 | break; |
---|
811 | |
---|
812 | #ifdef mpc860 |
---|
813 | case SCC3_MINOR: |
---|
814 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC3); |
---|
815 | break; |
---|
816 | case SCC4_MINOR: |
---|
817 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC4); |
---|
818 | break; |
---|
819 | #endif |
---|
820 | } |
---|
821 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
822 | consoleIrqData.on = m8xx_scc_enable; |
---|
823 | consoleIrqData.off = m8xx_scc_disable; |
---|
824 | consoleIrqData.isOn = m8xx_scc_isOn; |
---|
825 | |
---|
826 | switch (minor) { |
---|
827 | case SCC2_MINOR: |
---|
828 | consoleIrqData.name = BSP_CPM_IRQ_SCC2; |
---|
829 | consoleIrqData.hdl = m8xx_scc2_interrupt_handler; |
---|
830 | break; |
---|
831 | |
---|
832 | #ifdef mpc860 |
---|
833 | case SCC3_MINOR: |
---|
834 | consoleIrqData.name = BSP_CPM_IRQ_SCC3; |
---|
835 | consoleIrqData.hdl = m8xx_scc3_interrupt_handler; |
---|
836 | break; |
---|
837 | |
---|
838 | case SCC4_MINOR: |
---|
839 | consoleIrqData.name = BSP_CPM_IRQ_SCC4; |
---|
840 | consoleIrqData.hdl = m8xx_scc4_interrupt_handler; |
---|
841 | break; |
---|
842 | #endif /* mpc860 */ |
---|
843 | } |
---|
844 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
845 | printk("Unable to connect SCC Irq handler\n"); |
---|
846 | rtems_fatal_error_occurred(1); |
---|
847 | } |
---|
848 | } |
---|
849 | } |
---|
850 | |
---|
851 | void m8xx_smc_enable(const rtems_irq_connect_data* ptr) |
---|
852 | { |
---|
853 | volatile m8xxSMCRegisters_t *smcregs = 0; |
---|
854 | switch (ptr->name) { |
---|
855 | case BSP_CPM_IRQ_SMC1 : |
---|
856 | smcregs = &m8xx.smc1; |
---|
857 | break; |
---|
858 | case BSP_CPM_IRQ_SMC2_OR_PIP : |
---|
859 | smcregs = &m8xx.smc2; |
---|
860 | break; |
---|
861 | default: |
---|
862 | break; |
---|
863 | } |
---|
864 | smcregs->smcm = 3; |
---|
865 | } |
---|
866 | |
---|
867 | void m8xx_smc_disable(const rtems_irq_connect_data* ptr) |
---|
868 | { |
---|
869 | volatile m8xxSMCRegisters_t *smcregs = 0; |
---|
870 | switch (ptr->name) { |
---|
871 | case BSP_CPM_IRQ_SMC1 : |
---|
872 | smcregs = &m8xx.smc1; |
---|
873 | break; |
---|
874 | case BSP_CPM_IRQ_SMC2_OR_PIP : |
---|
875 | smcregs = &m8xx.smc2; |
---|
876 | break; |
---|
877 | default: |
---|
878 | break; |
---|
879 | } |
---|
880 | smcregs->smcm &= (~3); |
---|
881 | } |
---|
882 | |
---|
883 | int m8xx_smc_isOn(const rtems_irq_connect_data* ptr) |
---|
884 | { |
---|
885 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
886 | } |
---|
887 | |
---|
888 | void |
---|
889 | m8xx_uart_smc_initialize (int minor) |
---|
890 | { |
---|
891 | unsigned char brg; |
---|
892 | volatile m8xxSMCparms_t *smcparms = 0; |
---|
893 | volatile m8xxSMCRegisters_t *smcregs = 0; |
---|
894 | |
---|
895 | /* |
---|
896 | * Check that minor number is valid |
---|
897 | */ |
---|
898 | if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) |
---|
899 | return; |
---|
900 | |
---|
901 | m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */ |
---|
902 | /* Get the simode clock source bit values for 9600 bps */ |
---|
903 | brg = m8xx_get_brg_clk(9600); |
---|
904 | |
---|
905 | /* |
---|
906 | * Allocate buffer descriptors |
---|
907 | */ |
---|
908 | RxBd[minor] = m8xx_bd_allocate (1); |
---|
909 | TxBd[minor] = m8xx_bd_allocate (1); |
---|
910 | |
---|
911 | /* |
---|
912 | * Get the address of the parameter RAM for the specified port, |
---|
913 | * configure I/O port B and put SMC in NMSI mode, connect the |
---|
914 | * SMC to the appropriate BRG. |
---|
915 | * |
---|
916 | * SMC2 RxD is shared with port B bit 20 |
---|
917 | * SMC2 TxD is shared with port B bit 21 |
---|
918 | * SMC1 RxD is shared with port B bit 24 |
---|
919 | * SMC1 TxD is shared with port B bit 25 |
---|
920 | */ |
---|
921 | switch (minor) { |
---|
922 | case SMC1_MINOR: |
---|
923 | smcparms = &m8xx.smc1p; |
---|
924 | smcregs = &m8xx.smc1; |
---|
925 | |
---|
926 | m8xx.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ |
---|
927 | m8xx.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ |
---|
928 | m8xx.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ |
---|
929 | |
---|
930 | m8xx.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */ |
---|
931 | m8xx.simode |= brg << 12; /* SMC1CS = brg */ |
---|
932 | break; |
---|
933 | |
---|
934 | case SMC2_MINOR: |
---|
935 | smcparms = &m8xx.smc2p; |
---|
936 | smcregs = &m8xx.smc2; |
---|
937 | |
---|
938 | m8xx.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ |
---|
939 | m8xx.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ |
---|
940 | m8xx.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ |
---|
941 | |
---|
942 | m8xx.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ |
---|
943 | m8xx.simode |= brg << 28; /* SMC2CS = brg */ |
---|
944 | break; |
---|
945 | } |
---|
946 | |
---|
947 | /* |
---|
948 | * Set up SMC1 parameter RAM common to all protocols |
---|
949 | */ |
---|
950 | smcparms->rbase = (char *)RxBd[minor] - (char *)&m8xx; |
---|
951 | smcparms->tbase = (char *)TxBd[minor] - (char *)&m8xx; |
---|
952 | smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); |
---|
953 | smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); |
---|
954 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
955 | smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
956 | else |
---|
957 | smcparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
958 | |
---|
959 | /* |
---|
960 | * Set up SMC1 parameter RAM UART-specific parameters |
---|
961 | */ |
---|
962 | smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
963 | smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
964 | smcparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
965 | |
---|
966 | /* |
---|
967 | * Set up the Receive Buffer Descriptor |
---|
968 | */ |
---|
969 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
970 | RxBd[minor]->length = 0; |
---|
971 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
972 | |
---|
973 | /* |
---|
974 | * Setup the Transmit Buffer Descriptor |
---|
975 | */ |
---|
976 | TxBd[minor]->status = M8xx_BD_WRAP; |
---|
977 | |
---|
978 | /* |
---|
979 | * Set up SMCx general and protocol-specific mode registers |
---|
980 | */ |
---|
981 | smcregs->smce = ~0; /* Clear any pending events */ |
---|
982 | smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */ |
---|
983 | smcregs->smcmr = M8xx_SMCMR_CLEN(9) | M8xx_SMCMR_SM_UART; |
---|
984 | |
---|
985 | /* |
---|
986 | * Send "Init parameters" command |
---|
987 | */ |
---|
988 | switch (minor) { |
---|
989 | case SMC1_MINOR: |
---|
990 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC1); |
---|
991 | break; |
---|
992 | |
---|
993 | case SMC2_MINOR: |
---|
994 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2); |
---|
995 | break; |
---|
996 | } |
---|
997 | |
---|
998 | /* |
---|
999 | * Enable receiver and transmitter |
---|
1000 | */ |
---|
1001 | smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN; |
---|
1002 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
1003 | consoleIrqData.on = m8xx_smc_enable; |
---|
1004 | consoleIrqData.off = m8xx_smc_disable; |
---|
1005 | consoleIrqData.isOn = m8xx_smc_isOn; |
---|
1006 | switch (minor) { |
---|
1007 | case SMC1_MINOR: |
---|
1008 | consoleIrqData.name = BSP_CPM_IRQ_SMC1; |
---|
1009 | consoleIrqData.hdl = m8xx_smc1_interrupt_handler; |
---|
1010 | break; |
---|
1011 | |
---|
1012 | case SMC2_MINOR: |
---|
1013 | consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP; |
---|
1014 | consoleIrqData.hdl = m8xx_smc2_interrupt_handler; |
---|
1015 | break; |
---|
1016 | } |
---|
1017 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
1018 | printk("Unable to connect SMC Irq handler\n"); |
---|
1019 | rtems_fatal_error_occurred(1); |
---|
1020 | } |
---|
1021 | } |
---|
1022 | } |
---|
1023 | |
---|
1024 | void |
---|
1025 | m8xx_uart_initialize(void) |
---|
1026 | { |
---|
1027 | int i; |
---|
1028 | |
---|
1029 | for (i=0; i < 4; i++) { |
---|
1030 | brg_spd[i] = 0; |
---|
1031 | brg_used[i] = 0; |
---|
1032 | } |
---|
1033 | } |
---|
1034 | |
---|
1035 | |
---|
1036 | |
---|
1037 | int |
---|
1038 | m8xx_uart_pollRead( |
---|
1039 | int minor |
---|
1040 | ) |
---|
1041 | { |
---|
1042 | unsigned char c; |
---|
1043 | |
---|
1044 | if (RxBd[minor]->status & M8xx_BD_EMPTY) { |
---|
1045 | return -1; |
---|
1046 | } |
---|
1047 | rtems_cache_invalidate_multiple_data_lines( |
---|
1048 | (const void *) RxBd[minor]->buffer, |
---|
1049 | RxBd[minor]->length |
---|
1050 | ); |
---|
1051 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
1052 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP; |
---|
1053 | return c; |
---|
1054 | } |
---|
1055 | |
---|
1056 | |
---|
1057 | /* |
---|
1058 | * TODO: Get a free buffer and set it up. |
---|
1059 | */ |
---|
1060 | int |
---|
1061 | m8xx_uart_write( |
---|
1062 | int minor, |
---|
1063 | const char *buf, |
---|
1064 | int len |
---|
1065 | ) |
---|
1066 | { |
---|
1067 | rtems_cache_flush_multiple_data_lines( buf, len ); |
---|
1068 | TxBd[minor]->buffer = (char *) buf; |
---|
1069 | TxBd[minor]->length = len; |
---|
1070 | TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
1071 | return 0; |
---|
1072 | } |
---|
1073 | |
---|
1074 | |
---|
1075 | int |
---|
1076 | m8xx_uart_pollWrite( |
---|
1077 | int minor, |
---|
1078 | const char *buf, |
---|
1079 | int len |
---|
1080 | ) |
---|
1081 | { |
---|
1082 | while (len--) { |
---|
1083 | while (TxBd[minor]->status & M8xx_BD_READY) |
---|
1084 | continue; |
---|
1085 | txBuf[minor] = *buf++; |
---|
1086 | rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 ); |
---|
1087 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
1088 | TxBd[minor]->length = 1; |
---|
1089 | TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP; |
---|
1090 | } |
---|
1091 | return 0; |
---|
1092 | } |
---|
1093 | |
---|
1094 | void |
---|
1095 | m8xx_uart_reserve_resources( |
---|
1096 | rtems_configuration_table *configuration |
---|
1097 | ) |
---|
1098 | { |
---|
1099 | rtems_termios_reserve_resources (configuration, NUM_PORTS); |
---|
1100 | } |
---|