source: rtems/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c @ 37731c2

4.104.114.84.95
Last change on this file since 37731c2 was 37731c2, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 6, 2001 at 3:54:20 PM

2001-03-30 Eric Valette <valette@…>

  • mpc8xx/exceptions/.cvsignore, mpc8xx/exceptions/Makefile.am, mpc8xx/exceptions/asm_utils.S, mpc8xx/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.h: New files.
  • configure.in, mpc6xx/mmu/bat.h, mpc8xx/Makefile.am, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/include/mpc8xx.h, mpc8xx/mmu/mmu.c, new_exception_processing/cpu.h, shared/include/byteorder.h, wrapup/Makefile.am: This is conversion of the mpc8xx CPU to the "new exception processing model."
  • Property mode set to 100644
File size: 30.3 KB
Line 
1/*
2 *  General Serial I/O functions.
3 *
4 *  This file contains the functions for performing serial I/O.
5 *  The actual system calls (console_*) should be in the BSP part
6 *  of the source tree. That way different BSPs can use whichever
7 *  SMCs and SCCs they want. Originally, all the stuff was in
8 *  this file, and it caused problems with one BSP using SCC2
9 *  as /dev/console, others using SMC1 for /dev/console, etc.
10 *
11 *  On-chip resources used:
12 *   resource   minor                note
13 *    SMC1       0
14 *    SMC2       1
15 *    SCC1       2                   N/A. Hardwired as ethernet port
16 *    SCC2       3
17 *    SCC3       4
18 *    SCC4       5
19 *    BRG1
20 *    BRG2
21 *    BRG3
22 *    BRG4
23 *  Author: Jay Monkman (jmonkman@frasca.com)
24 *  Copyright (C) 1998 by Frasca International, Inc.
25 *
26 *  Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by:
27 *    W. Eric Norum
28 *    Saskatchewan Accelerator Laboratory
29 *    University of Saskatchewan
30 *    Saskatoon, Saskatchewan, CANADA
31 *    eric@skatter.usask.ca
32 *
33 *  COPYRIGHT (c) 1989-1998.
34 *  On-Line Applications Research Corporation (OAR).
35 *
36 *  Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca>
37 *  and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>
38 *  Copyright (c) 1999, National Research Council of Canada
39 *
40 *  The license and distribution terms for this file may be
41 *  found in the file LICENSE in this distribution or at
42 *
43 *  http://www.OARcorp.com/rtems/license.html.
44 *
45 *  $Id$
46 */
47
48#include <rtems.h>
49#include <rtems/libio.h>
50#include <mpc8xx.h>
51#include <mpc8xx/console.h>
52#include <mpc8xx/cpm.h>
53#include <stdlib.h>
54#include <unistd.h>
55#include <termios.h>
56#include <bsp/irq.h>
57#include <bspIo.h>   /* for printk */
58
59extern rtems_cpu_table Cpu_table;
60
61/* BSP supplied routine */
62extern int mbx8xx_console_get_configuration();
63
64/*
65 * Interrupt-driven input buffer
66 */
67#define RXBUFSIZE       16
68
69/*
70 *  I/O buffers and pointers to buffer descriptors.
71 *  Currently, single buffered input is done. This will work only
72 *  if the Rx interrupts are serviced quickly.
73 *
74 *  TODO: Add a least double buffering for safety.
75 */
76static volatile char rxBuf[NUM_PORTS][RXBUFSIZE];
77static volatile char txBuf[NUM_PORTS];
78
79/* SCC/SMC buffer descriptors */
80static volatile m8xxBufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS];
81
82/* Used to track the usage of the baud rate generators */
83static unsigned long brg_spd[4];
84static char  brg_used[4];
85
86/* Used to track termios private data for callbacks */
87struct rtems_termios_tty *ttyp[NUM_PORTS];
88
89/*
90 * Device-specific routines
91 */
92static int m8xx_get_brg_cd(int);
93static unsigned char m8xx_get_brg_clk(int);
94void m8xx_console_reserve_resources(rtems_configuration_table *);
95static int m8xx_smc_set_attributes(int, const struct termios*);
96static int m8xx_scc_set_attributes(int, const struct termios*);
97static void m8xx_smc1_interrupt_handler(void);
98static void m8xx_smc2_interrupt_handler(void);
99static void m8xx_scc2_interrupt_handler(void);
100#if defined(mpc860)
101static void m8xx_scc3_interrupt_handler(void);
102static void m8xx_scc4_interrupt_handler(void);
103#endif
104
105/*
106 * Compute baud-rate-generator configuration register value
107 */
108static int
109m8xx_get_brg_cd (int baud)
110{
111  int divisor;
112  int div16 = 0;
113
114  divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud;
115  if (divisor > 4096) {
116    div16 = 1;
117    divisor = (divisor + 8) / 16;
118  }
119  return M8xx_BRG_EN | M8xx_BRG_EXTC_BRGCLK |
120    ((divisor - 1) << 1) | div16;
121}
122
123
124/*
125 *  This function will fail if more that 4 baud rates have been selected
126 *  at any time since the OS started. It needs to be fixed. FIXME
127 */
128static unsigned
129char m8xx_get_brg_clk(int baud)
130{
131  int i;
132
133  /* first try to find a BRG that is already at the right speed */
134  for ( i = 0; i < 4; i++ ) {
135    if ( brg_spd[i] == baud ) {
136      break;
137    }
138  }
139
140  if ( i == 4 ) { /* I guess we didn't find one */
141    for ( i = 0; i < 4; i++ ) {
142      if ( brg_used[i] == 0 ) {
143        break;
144      }
145    }
146  }
147  if (i != 4) {
148    brg_used[i]++;
149    brg_spd[i]=baud;
150    switch (i) {
151    case 0:
152      m8xx.brgc1 = M8xx_BRG_RST;
153      m8xx.brgc1 = m8xx_get_brg_cd(baud);
154      break;
155    case 1:
156      m8xx.brgc2 = M8xx_BRG_RST;
157      m8xx.brgc2 = m8xx_get_brg_cd(baud);
158      break;
159    case 2:
160      m8xx.brgc3 = M8xx_BRG_RST;
161      m8xx.brgc3 = m8xx_get_brg_cd(baud);
162      break;
163    case 3:
164      m8xx.brgc4 = M8xx_BRG_RST;
165      m8xx.brgc4 = m8xx_get_brg_cd(baud);
166      break;
167    }
168    return i;
169  }
170
171  else
172    return 0xff;
173}
174
175
176/*
177 * Hardware-dependent portion of tcsetattr().
178 */
179static int
180m8xx_smc_set_attributes (int minor, const struct termios *t)
181{
182  int baud, brg=0, csize=0, ssize, psize;
183  rtems_unsigned16 clen=0, cstopb, parenb, parodd, cread; 
184
185  /* Baud rate */
186  switch (t->c_cflag & CBAUD) {
187  default:      baud = -1;      break;
188  case B50:     baud = 50;      break;
189  case B75:     baud = 75;      break;
190  case B110:    baud = 110;     break;
191  case B134:    baud = 134;     break;
192  case B150:    baud = 150;     break;
193  case B200:    baud = 200;     break;
194  case B300:    baud = 300;     break;
195  case B600:    baud = 600;     break;
196  case B1200:   baud = 1200;    break;
197  case B1800:   baud = 1800;    break;
198  case B2400:   baud = 2400;    break;
199  case B4800:   baud = 4800;    break;
200  case B9600:   baud = 9600;    break;
201  case B19200:  baud = 19200;   break;
202  case B38400:  baud = 38400;   break;
203  case B57600:  baud = 57600;   break;
204  case B115200: baud = 115200;  break;
205  case B230400: baud = 230400;  break;
206  case B460800: baud = 460800;  break;
207  }
208  if (baud > 0)
209    brg = m8xx_get_brg_clk(baud);     /* 4 BRGs, 6 serial ports - hopefully */
210                                      /*  at least 2 ports will be the same */
211 
212  /* Number of data bits */
213  switch ( t->c_cflag & CSIZE ) {
214    case CS5:     csize = 5;       break;
215    case CS6:     csize = 6;       break;
216    case CS7:     csize = 7;       break;
217    case CS8:     csize = 8;       break;
218  }
219
220  /* Stop bits */
221  if ( t->c_cflag & CSTOPB ) {
222    cstopb = 0x0400;              /* Two stop bits */
223    ssize  = 2;
224  } else {
225    cstopb = 0x0000;              /* One stop bit */
226    ssize  = 1;
227  }
228
229  /* Parity */
230  if ( t->c_cflag & PARENB ) {
231    parenb = 0x0200;              /* Parity enabled on Tx and Rx */
232    psize  = 1;
233  } else {
234    parenb = 0x0000;              /* No parity on Tx and Rx */
235    psize  = 0;
236  }
237 
238  if ( t->c_cflag & PARODD )
239    parodd = 0x0000;              /* Odd parity */
240  else
241    parodd = 0x0100;
242
243  /*
244   * Character Length = start + data + parity + stop - 1
245   */ 
246  switch ( 1 + csize + psize + ssize - 1 ) {
247    case 6:     clen = 0x3000;       break;
248    case 7:     clen = 0x3800;       break;
249    case 8:     clen = 0x4000;       break;
250    case 9:     clen = 0x4800;       break;
251    case 10:    clen = 0x5000;       break;
252    case 11:    clen = 0x5800;       break;
253  }
254
255  if ( t->c_cflag & CREAD )
256    cread = 0x0023;             /* UART normal operation, enable Rx and Tx */
257  else
258    cread = 0x0021;             /* UART normal operation, enable Tx */
259   
260  /* Write the SIMODE/SMCMR registers */
261  switch (minor) {
262    case SMC1_MINOR:
263      m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) );
264      m8xx.smc1.smcmr = clen | cstopb | parenb | parodd | cread;
265      break;
266    case SMC2_MINOR:
267      m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) );
268      m8xx.smc2.smcmr = clen | cstopb | parenb | parodd | cread;
269      break;
270  }
271  return 0;
272}
273
274
275static int
276m8xx_scc_set_attributes (int minor, const struct termios *t)
277{
278  int baud, brg=0;
279  rtems_unsigned16 csize=0, cstopb, parenb, parodd;
280
281  /* Baud rate */
282  switch (t->c_cflag & CBAUD) {
283  default:      baud = -1;      break;
284  case B50:     baud = 50;      break;
285  case B75:     baud = 75;      break;
286  case B110:    baud = 110;     break;
287  case B134:    baud = 134;     break;
288  case B150:    baud = 150;     break;
289  case B200:    baud = 200;     break;
290  case B300:    baud = 300;     break;
291  case B600:    baud = 600;     break;
292  case B1200:   baud = 1200;    break;
293  case B1800:   baud = 1800;    break;
294  case B2400:   baud = 2400;    break;
295  case B4800:   baud = 4800;    break;
296  case B9600:   baud = 9600;    break;
297  case B19200:  baud = 19200;   break;
298  case B38400:  baud = 38400;   break;
299  case B57600:  baud = 57600;   break;
300  case B115200: baud = 115200;  break;
301  case B230400: baud = 230400;  break;
302  case B460800: baud = 460800;  break;
303  }
304  if (baud > 0)
305    brg = m8xx_get_brg_clk(baud);     /* 4 BRGs, 5 serial ports - hopefully */
306                                      /*  at least 2 ports will be the same */
307                                      /*  Write the SICR register below */
308   
309  /* Number of data bits */
310  switch ( t->c_cflag & CSIZE ) {
311    case CS5:     csize = 0x0000;       break;
312    case CS6:     csize = 0x1000;       break;
313    case CS7:     csize = 0x2000;       break;
314    case CS8:     csize = 0x3000;       break;
315  }
316
317  /* Stop bits */
318  if ( t->c_cflag & CSTOPB )
319    cstopb = 0x4000;              /* Two stop bits */
320  else
321    cstopb = 0x0000;              /* One stop bit */
322   
323  /* Parity */
324  if ( t->c_cflag & PARENB )
325    parenb = 0x0010;              /* Parity enabled on Tx and Rx */
326  else
327    parenb = 0x0000;              /* No parity on Tx and Rx */
328   
329  if ( t->c_cflag & PARODD )
330    parodd = 0x0000;              /* Odd parity */
331  else
332    parodd = 0x000a;
333
334  /* Write the SICR/PSMR Registers */
335  switch (minor) {
336    case SCC2_MINOR:
337      m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) );
338      m8xx.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc2.psmr & 0x8fe0) );
339      break;
340  #if defined(mpc860)
341    case SCC3_MINOR:
342      m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) );
343      m8xx.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc3.psmr & 0x8fe0) );
344      break;
345    case SCC4_MINOR:
346      m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) );
347      m8xx.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc4.psmr & 0x8fe0) );
348      break;
349  #endif
350  }
351 
352  return 0;
353}
354
355
356int 
357m8xx_uart_setAttributes(
358  int minor,
359  const struct termios *t
360)
361{
362  /*
363   * Check that port number is valid
364   */
365  if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) 
366    return 0;
367
368  switch (minor) {
369    case SMC1_MINOR:
370    case SMC2_MINOR:
371      return m8xx_smc_set_attributes( minor, t );
372
373    case SCC2_MINOR:
374    case SCC3_MINOR:
375    case SCC4_MINOR:
376      return m8xx_scc_set_attributes( minor, t );
377  }
378  return 0;
379}
380
381
382/*
383 * Interrupt handlers
384 */
385static void m8xx_scc2_interrupt_handler ()
386{
387  int nb_overflow;
388
389  /*
390   * Buffer received?
391   */
392  if ((m8xx.scc2.sccm & M8xx_SCCE_RX) && (m8xx.scc2.scce & M8xx_SCCE_RX)) {
393    m8xx.scc2.scce = M8xx_SCCE_RX;    /* Clear the event */
394
395
396    /* Check that the buffer is ours */
397    if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
398      rtems_cache_invalidate_multiple_data_lines( 
399        (const void *) RxBd[SCC2_MINOR]->buffer, 
400        RxBd[SCC2_MINOR]->length );
401      nb_overflow = rtems_termios_enqueue_raw_characters(
402        (void *)ttyp[SCC2_MINOR],
403        (char *)RxBd[SCC2_MINOR]->buffer,
404        (int)RxBd[SCC2_MINOR]->length );
405      RxBd[SCC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
406                                 M8xx_BD_INTERRUPT;
407    }
408  }
409
410  /*
411   * Buffer transmitted?
412   */
413  if (m8xx.scc2.scce & M8xx_SCCE_TX) {
414    m8xx.scc2.scce = M8xx_SCCE_TX;  /* Clear the event */
415
416    /* Check that the buffer is ours */
417    if ((TxBd[SCC2_MINOR]->status & M8xx_BD_READY) == 0)
418      rtems_termios_dequeue_characters (
419        (void *)ttyp[SCC2_MINOR],
420        (int)TxBd[SCC2_MINOR]->length);
421  }
422}
423
424
425#ifdef mpc860
426static void
427m8xx_scc3_interrupt_handler (void)
428{
429  int nb_overflow;
430
431  /*
432   * Buffer received?
433   */
434  if ((m8xx.scc3.sccm & M8xx_SCCE_RX) && (m8xx.scc3.scce & M8xx_SCCE_RX)) {
435    m8xx.scc3.scce = M8xx_SCCE_RX;  /* Clear the event */
436
437
438    /* Check that the buffer is ours */
439    if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
440      rtems_cache_invalidate_multiple_data_lines( 
441        (const void *) RxBd[SCC3_MINOR]->buffer, 
442        RxBd[SCC3_MINOR]->length );
443      nb_overflow = rtems_termios_enqueue_raw_characters(
444        (void *)ttyp[SCC3_MINOR],
445        (char *)RxBd[SCC3_MINOR]->buffer,
446        (int)RxBd[SCC3_MINOR]->length );
447      RxBd[SCC3_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
448                                 M8xx_BD_INTERRUPT;
449    }
450  }
451
452  /*
453   * Buffer transmitted?
454   */
455  if (m8xx.scc3.scce & M8xx_SCCE_TX) {
456    m8xx.scc3.scce = M8xx_SCCE_TX;    /* Clear the event */
457
458    /* Check that the buffer is ours */
459    if ((TxBd[SCC3_MINOR]->status & M8xx_BD_READY) == 0)
460      rtems_termios_dequeue_characters (
461        (void *)ttyp[SCC3_MINOR],
462        (int)TxBd[SCC3_MINOR]->length);
463  }
464}
465
466
467static void
468m8xx_scc4_interrupt_handler (void)
469{
470  int nb_overflow;
471
472  /*
473   * Buffer received?
474   */
475  if ((m8xx.scc4.sccm & M8xx_SCCE_RX) && (m8xx.scc4.scce & M8xx_SCCE_RX)) {
476    m8xx.scc4.scce = M8xx_SCCE_RX;  /* Clear the event */
477
478
479    /* Check that the buffer is ours */
480    if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
481      rtems_cache_invalidate_multiple_data_lines( 
482        (const void *) RxBd[SCC4_MINOR]->buffer, 
483        RxBd[SCC4_MINOR]->length );
484      nb_overflow = rtems_termios_enqueue_raw_characters(
485        (void *)ttyp[SCC4_MINOR],
486        (char *)RxBd[SCC4_MINOR]->buffer,
487        (int)RxBd[SCC4_MINOR]->length );
488      RxBd[SCC4_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
489                                 M8xx_BD_INTERRUPT;
490    }
491  }
492
493  /*
494   * Buffer transmitted?
495   */
496  if (m8xx.scc4.scce & M8xx_SCCE_TX) {
497    m8xx.scc4.scce = M8xx_SCCE_TX;    /* Clear the event */
498
499    /* Check that the buffer is ours */
500    if ((TxBd[SCC4_MINOR]->status & M8xx_BD_READY) == 0)
501      rtems_termios_dequeue_characters (
502        (void *)ttyp[SCC4_MINOR],
503        (int)TxBd[SCC4_MINOR]->length);
504  }
505}
506#endif
507
508static void
509m8xx_smc1_interrupt_handler (void)
510{
511  int nb_overflow;
512
513  /*
514   * Buffer received?
515   */
516  if (m8xx.smc1.smce & M8xx_SMCE_RX) {
517    m8xx.smc1.smce = M8xx_SMCE_RX;  /* Clear the event */
518
519
520    /* Check that the buffer is ours */
521    if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
522      rtems_cache_invalidate_multiple_data_lines( 
523        (const void *) RxBd[SMC1_MINOR]->buffer, 
524        RxBd[SMC1_MINOR]->length );
525      nb_overflow = rtems_termios_enqueue_raw_characters(
526        (void *)ttyp[SMC1_MINOR],
527        (char *)RxBd[SMC1_MINOR]->buffer,
528        (int)RxBd[SMC1_MINOR]->length );
529      RxBd[SMC1_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
530                                 M8xx_BD_INTERRUPT;
531    }
532  }
533
534  /*
535   * Buffer transmitted?
536   */
537  if (m8xx.smc1.smce & M8xx_SMCE_TX) {
538    m8xx.smc1.smce = M8xx_SMCE_TX;    /* Clear the event */
539
540    /* Check that the buffer is ours */
541    if ((TxBd[SMC1_MINOR]->status & M8xx_BD_READY) == 0)
542      rtems_termios_dequeue_characters (
543        (void *)ttyp[SMC1_MINOR],
544        (int)TxBd[SMC1_MINOR]->length);
545  }
546}
547
548
549static void
550m8xx_smc2_interrupt_handler (void)
551{
552  int nb_overflow;
553
554  /*
555   * Buffer received?
556   */
557  if (m8xx.smc2.smce & M8xx_SMCE_RX) {
558    m8xx.smc2.smce = M8xx_SMCE_RX;  /* Clear the event */
559
560
561    /* Check that the buffer is ours */
562    if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
563      rtems_cache_invalidate_multiple_data_lines( 
564        (const void *) RxBd[SMC2_MINOR]->buffer, 
565        RxBd[SMC2_MINOR]->length );
566      nb_overflow = rtems_termios_enqueue_raw_characters(
567        (void *)ttyp[SMC2_MINOR],
568        (char *)RxBd[SMC2_MINOR]->buffer,
569        (int)RxBd[SMC2_MINOR]->length );
570      RxBd[SMC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
571                                 M8xx_BD_INTERRUPT;
572    }
573  }
574
575  /*
576   * Buffer transmitted?
577   */
578  if (m8xx.smc2.smce & M8xx_SMCE_TX) {
579    m8xx.smc2.smce = M8xx_SMCE_TX;    /* Clear the event */
580
581    /* Check that the buffer is ours */
582    if ((TxBd[SMC2_MINOR]->status & M8xx_BD_READY) == 0)
583      rtems_termios_dequeue_characters (
584        (void *)ttyp[SMC2_MINOR],
585        (int)TxBd[SMC2_MINOR]->length);
586  }
587}
588
589void m8xx_scc_enable(const rtems_irq_connect_data* ptr)
590{
591  volatile m8xxSCCRegisters_t *sccregs = 0;
592  switch (ptr->name) {
593#if defined(mpc860)
594  case BSP_CPM_IRQ_SCC4 :
595    sccregs = &m8xx.scc4;
596    break;
597  case BSP_CPM_IRQ_SCC3 :
598    sccregs = &m8xx.scc3;
599    break;
600#endif
601  case BSP_CPM_IRQ_SCC2 :
602    sccregs = &m8xx.scc2;
603    break;
604  case BSP_CPM_IRQ_SCC1 :
605    sccregs = &m8xx.scc1;
606    break;
607  default:
608    break;
609  }
610  sccregs->sccm = 3;
611}
612
613void m8xx_scc_disable(const rtems_irq_connect_data* ptr)
614{
615  volatile m8xxSCCRegisters_t *sccregs = 0;
616  switch (ptr->name) {
617#if defined(mpc860)
618  case BSP_CPM_IRQ_SCC4 :
619    sccregs = &m8xx.scc4;
620    break;
621  case BSP_CPM_IRQ_SCC3 :
622    sccregs = &m8xx.scc3;
623    break;
624#endif
625  case BSP_CPM_IRQ_SCC2 :
626    sccregs = &m8xx.scc2;
627    break;
628  case BSP_CPM_IRQ_SCC1 :
629    sccregs = &m8xx.scc1;
630    break;
631  default:
632    break;
633  }
634  sccregs->sccm &= (~3);
635}
636
637int m8xx_scc_isOn(const rtems_irq_connect_data* ptr)
638{
639 return BSP_irq_enabled_at_cpm (ptr->name);
640}
641
642static rtems_irq_connect_data consoleIrqData =
643{
644  BSP_CPM_IRQ_SCC2,
645  (rtems_irq_hdl)m8xx_scc2_interrupt_handler,
646  (rtems_irq_enable) m8xx_scc_enable,
647  (rtems_irq_disable) m8xx_scc_disable,
648  (rtems_irq_is_enabled) m8xx_scc_isOn
649};
650       
651void
652m8xx_uart_scc_initialize (int minor)
653{
654  unsigned char brg;
655  volatile m8xxSCCparms_t *sccparms = 0;
656  volatile m8xxSCCRegisters_t *sccregs = 0;
657  int res;
658
659  /*
660   * Check that minor number is valid
661   */
662  if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) 
663    return;
664
665  /* Get the sicr clock source bit values for 9600 bps */
666  brg = m8xx_get_brg_clk(9600);
667
668  /*
669   * Allocate buffer descriptors
670   */
671  RxBd[minor] = m8xx_bd_allocate(1);
672  TxBd[minor] = m8xx_bd_allocate(1);
673
674  /*
675   *  Get the address of the parameter RAM for the specified port,
676   *  configure I/O port A,C & D and put SMC in NMSI mode, connect
677   *  the SCC to the appropriate BRG.
678   *
679   *  SCC2 TxD is shared with port A bit 12
680   *  SCC2 RxD is shared with port A bit 13
681   *  SCC1 TxD is shared with port A bit 14
682   *  SCC1 RxD is shared with port A bit 15
683   *  SCC4 DCD is shared with port C bit 4
684   *  SCC4 CTS is shared with port C bit 5
685   *  SCC3 DCD is shared with port C bit 6
686   *  SCC3 CTS is shared with port C bit 7
687   *  SCC2 DCD is shared with port C bit 8
688   *  SCC2 CTS is shared with port C bit 9
689   *  SCC1 DCD is shared with port C bit 10
690   *  SCC1 CTS is shared with port C bit 11
691   *  SCC2 RTS is shared with port C bit 14
692   *  SCC1 RTS is shared with port C bit 15
693   *  SCC4 RTS is shared with port D bit 6
694   *  SCC3 RTS is shared with port D bit 7
695   *  SCC4 TxD is shared with port D bit 8
696   *  SCC4 RxD is shared with port D bit 9
697   *  SCC3 TxD is shared with port D bit 10
698   *  SCC3 RxD is shared with port D bit 11
699   */
700  switch (minor) {
701    case SCC2_MINOR:
702      sccparms = &m8xx.scc2p;
703      sccregs = &m8xx.scc2;
704     
705      m8xx.papar |=  0x000C;        /* PA12 & PA13 are dedicated peripheral pins */
706      m8xx.padir &= ~0x000C;        /* PA13 & PA12 must not drive the UART lines */
707      m8xx.paodr &= ~0x000C;        /* PA12 & PA13 are not open drain */
708      m8xx.pcpar |=  0x0002;        /* PC14 is SCC2 RTS */
709      m8xx.pcpar &= ~0x00C0;        /* PC8 & PC9 are SCC2 DCD and CTS */
710      m8xx.pcdir &= ~0x00C2;        /* PC8, PC9 & PC14 must not drive the UART lines */
711      m8xx.pcso  |=  0x00C0;        /* Enable DCD and CTS inputs */
712     
713      m8xx.sicr &= 0xFFFF00FF;      /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */
714      m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */
715      break;
716
717#ifdef mpc860
718    case SCC3_MINOR:
719      sccparms = &m8xx.scc3p;
720      sccregs = &m8xx.scc3;
721     
722      m8xx.pcpar &= ~0x0300;        /* PC6 & PC7 are SCC3 DCD and CTS */
723      m8xx.pcdir &= ~0x0300;        /* PC6 & PC7 must not drive the UART lines */
724      m8xx.pcso  |=  0x0300;        /* Enable DCD and CTS inputs */
725      m8xx.pdpar |=  0x0130;        /* PD7, PD10 & PD11 are dedicated peripheral pins */
726     
727      m8xx.sicr &= 0xFF00FFFF;      /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */
728      m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */
729      break;
730
731    case SCC4_MINOR:
732      sccparms = &m8xx.scc4p;
733      sccregs = &m8xx.scc4;
734     
735      m8xx.pcpar &= ~0x0C00;        /* PC4 & PC5 are SCC4 DCD and CTS */
736      m8xx.pcdir &= ~0x0C00;        /* PC4 & PC5 must not drive the UART lines */
737      m8xx.pcso  |=  0x0C00;        /* Enable DCD and CTS inputs */
738      m8xx.pdpar |=  0x02C0;        /* PD6, PD8 & PD9 are dedicated peripheral pins */
739       
740      m8xx.sicr &= 0x00FFFFFF;      /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */
741      m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */
742      break;
743#endif
744  }
745
746  /*
747   *  Set up SDMA
748   */
749  m8xx.sdcr = 0x01;                 /* as per section 16.10.2.1 MPC821UM/AD */
750
751  /*
752   *  Set up the SCC parameter RAM.
753   */
754  sccparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
755  sccparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
756
757  sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
758  sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
759  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 )
760    sccparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
761  else
762    sccparms->mrblr = 1;            /* Maximum Rx buffer size */
763  sccparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
764  sccparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
765
766  sccparms->un.uart.parec = 0;      /* Clear parity error counter */
767  sccparms->un.uart.frmec = 0;      /* Clear framing error counter */
768  sccparms->un.uart.nosec = 0;      /* Clear noise counter */
769  sccparms->un.uart.brkec = 0;      /* Clear break counter */
770
771  sccparms->un.uart.uaddr[0] = 0;   /* Not in multidrop mode, so clear */
772  sccparms->un.uart.uaddr[1] = 0;   /* Not in multidrop mode, so clear */
773  sccparms->un.uart.toseq  = 0;     /* Tx Out-Of-SEQuence--no XON/XOFF now */
774
775  sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */
776  sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */
777  sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */
778  sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */
779  sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */
780  sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */
781  sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */
782  sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */
783
784
785  sccparms->un.uart.rccm = 0xc0ff;  /* No masking */
786
787  /*
788   * Set up the Receive Buffer Descriptor
789   */
790  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
791  RxBd[minor]->length = 0;
792  RxBd[minor]->buffer = rxBuf[minor];
793
794  /*
795   * Setup the Transmit Buffer Descriptor
796   */
797  TxBd[minor]->status = M8xx_BD_WRAP;
798
799 /*
800   * Set up SCCx general and protocol-specific mode registers
801   */
802  sccregs->gsmr_h = 0x00000020;     /* RFW=low latency operation */
803  sccregs->gsmr_l = 0x00028004;     /* TDCR=RDCR=16x clock mode, MODE=uart*/
804  sccregs->scce = ~0;               /* Clear any pending event */
805  sccregs->sccm = 0;                /* Mask all interrupt/event sources */
806  sccregs->psmr = 0x3000;           /* Normal operation & mode, 1 stop bit,
807                                       8 data bits, no parity */
808  sccregs->dsr = 0x7E7E;            /* No fractional stop bits */
809  sccregs->gsmr_l = 0x00028034;     /* ENT=enable Tx, ENR=enable Rx */
810
811  /*
812   *  Initialize the Rx and Tx with the new parameters.
813   */
814  switch (minor) {
815    case SCC2_MINOR:
816      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC2);
817      break;
818
819#ifdef mpc860
820    case SCC3_MINOR:
821      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC3);
822      break;
823    case SCC4_MINOR:
824      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC4);
825      break;
826#endif
827  }
828  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) {
829    switch (minor) {
830      case SCC2_MINOR:
831        break;
832
833#ifdef mpc860
834    case SCC3_MINOR:
835      consoleIrqData.name = BSP_CPM_IRQ_SCC3;
836      consoleIrqData.hdl = m8xx_scc3_interrupt_handler;
837      break;
838     
839    case SCC4_MINOR:
840      consoleIrqData.name = BSP_CPM_IRQ_SCC4;
841      consoleIrqData.hdl = m8xx_scc4_interrupt_handler;
842      break;
843#endif /* mpc860 */
844    }
845    if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
846        printk("Unable to connect SCC Irq handler\n");
847        rtems_fatal_error_occurred(1);
848    }
849  }
850}
851
852void m8xx_smc_enable(const rtems_irq_connect_data* ptr)
853{
854  volatile m8xxSMCRegisters_t *smcregs = 0;
855  switch (ptr->name) {
856  case BSP_CPM_IRQ_SMC1 :
857    smcregs = &m8xx.smc1;
858    break;
859  case BSP_CPM_IRQ_SMC2_OR_PIP :
860    smcregs = &m8xx.smc2;
861    break;
862  default:
863    break;
864  }
865  smcregs->smcm = 3;
866}
867
868void m8xx_smc_disable(const rtems_irq_connect_data* ptr)
869{
870  volatile m8xxSMCRegisters_t *smcregs = 0;
871  switch (ptr->name) {
872  case BSP_CPM_IRQ_SMC1 :
873    smcregs = &m8xx.smc1;
874    break;
875  case BSP_CPM_IRQ_SMC2_OR_PIP :
876    smcregs = &m8xx.smc2;
877    break;
878  default:
879    break;
880  }
881  smcregs->smcm &= (~3);
882}
883
884int m8xx_smc_isOn(const rtems_irq_connect_data* ptr)
885{
886 return BSP_irq_enabled_at_cpm (ptr->name);
887}
888
889void
890m8xx_uart_smc_initialize (int minor)
891{
892  unsigned char brg;
893  volatile m8xxSMCparms_t *smcparms = 0;
894  volatile m8xxSMCRegisters_t *smcregs = 0;
895
896  /*
897   * Check that minor number is valid
898   */
899  if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) 
900    return;
901
902  /* Get the simode clock source bit values for 9600 bps */
903  brg = m8xx_get_brg_clk(9600);
904
905  /*
906   * Allocate buffer descriptors
907   */
908  RxBd[minor] = m8xx_bd_allocate (1);
909  TxBd[minor] = m8xx_bd_allocate (1);
910
911  /*
912   *  Get the address of the parameter RAM for the specified port,
913   *  configure I/O port B and put SMC in NMSI mode, connect the
914   *  SMC to the appropriate BRG.
915   *
916   *  SMC2 RxD is shared with port B bit 20
917   *  SMC2 TxD is shared with port B bit 21
918   *  SMC1 RxD is shared with port B bit 24
919   *  SMC1 TxD is shared with port B bit 25
920   */
921  switch (minor) {
922    case SMC1_MINOR:
923      smcparms = &m8xx.smc1p;
924      smcregs = &m8xx.smc1;
925     
926      m8xx.pbpar |=  0x000000C0;    /* PB24 & PB25 are dedicated peripheral pins */
927      m8xx.pbdir &= ~0x000000C0;    /* PB24 & PB25 must not drive UART lines */
928      m8xx.pbodr &= ~0x000000C0;    /* PB24 & PB25 are not open drain */
929
930      m8xx.simode &= 0xFFFF0FFF;    /* Clear SMC1CS & SMC1 for NMSI mode */
931      m8xx.simode |= brg << 12;     /* SMC1CS = brg */
932      break;
933
934    case SMC2_MINOR:
935      smcparms = &m8xx.smc2p;
936      smcregs = &m8xx.smc2;
937     
938      m8xx.pbpar |=  0x00000C00;    /* PB20 & PB21 are dedicated peripheral pins */
939      m8xx.pbdir &= ~0x00000C00;    /* PB20 & PB21 must not drive the UART lines */
940      m8xx.pbodr &= ~0x00000C00;    /* PB20 & PB21 are not open drain */
941     
942      m8xx.simode &= 0x0FFFFFFF;    /* Clear SMC2CS & SMC2 for NMSI mode */
943      m8xx.simode |= brg << 28;     /* SMC2CS = brg */
944      break;
945  }
946 
947  /*
948   * Set up SMC1 parameter RAM common to all protocols
949   */
950  smcparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
951  smcparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
952  smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
953  smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
954  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 )
955    smcparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
956  else
957    smcparms->mrblr = 1;            /* Maximum Rx buffer size */
958
959  /*
960   * Set up SMC1 parameter RAM UART-specific parameters
961   */
962  smcparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
963  smcparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
964  smcparms->un.uart.brkec = 0;      /* Clear break counter */
965
966  /*
967   * Set up the Receive Buffer Descriptor
968   */
969  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
970  RxBd[minor]->length = 0;
971  RxBd[minor]->buffer = rxBuf[minor];
972
973  /*
974   * Setup the Transmit Buffer Descriptor
975   */
976  TxBd[minor]->status = M8xx_BD_WRAP;
977
978  /*
979   * Set up SMCx general and protocol-specific mode registers
980   */
981  smcregs->smce = ~0;               /* Clear any pending events */
982  smcregs->smcm = 0;                /* Enable SMC Rx & Tx interrupts */
983  smcregs->smcmr = M8xx_SMCMR_CLEN(9) | M8xx_SMCMR_SM_UART;
984
985  /*
986   * Send "Init parameters" command
987   */
988  switch (minor) {
989    case SMC1_MINOR:
990      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC1);
991      break;
992
993    case SMC2_MINOR:
994      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2);
995      break;
996  }
997 
998  /*
999   * Enable receiver and transmitter
1000   */
1001  smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
1002  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) {
1003    consoleIrqData.on = m8xx_smc_enable;
1004    consoleIrqData.off = m8xx_smc_disable;
1005    consoleIrqData.isOn = m8xx_smc_isOn;
1006    switch (minor) {
1007        case SMC1_MINOR:
1008          consoleIrqData.name = BSP_CPM_IRQ_SMC1;
1009          consoleIrqData.hdl  = m8xx_smc1_interrupt_handler;
1010          break;
1011     
1012        case SMC2_MINOR:
1013          consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP;
1014          consoleIrqData.hdl  = m8xx_smc2_interrupt_handler;
1015          break;
1016    }
1017    if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
1018        printk("Unable to connect SMC Irq handler\n");
1019        rtems_fatal_error_occurred(1);
1020    }
1021  }
1022}
1023
1024void
1025m8xx_uart_initialize(void)
1026{
1027  int i;
1028 
1029  for (i=0; i < 4; i++) {
1030    brg_spd[i] = 0;
1031    brg_used[i] = 0;
1032  }
1033}
1034
1035
1036
1037int
1038m8xx_uart_pollRead(
1039  int minor
1040)
1041{
1042  unsigned char c;
1043
1044  if (RxBd[minor]->status & M8xx_BD_EMPTY) {
1045    return -1;
1046  }
1047  rtems_cache_invalidate_multiple_data_lines( 
1048    (const void *) RxBd[minor]->buffer,
1049    RxBd[minor]->length
1050  );
1051  c = ((char *)RxBd[minor]->buffer)[0];
1052  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP;
1053  return c;
1054}
1055
1056
1057/*
1058 *  TODO: Get a free buffer and set it up.
1059 */
1060int 
1061m8xx_uart_write(
1062  int minor,
1063  const char *buf,
1064  int len
1065)
1066{
1067  rtems_cache_flush_multiple_data_lines( buf, len );
1068  TxBd[minor]->buffer = (char *) buf;
1069  TxBd[minor]->length = len;
1070  TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
1071  return 0;
1072}
1073 
1074
1075int
1076m8xx_uart_pollWrite(
1077  int minor,
1078  const char *buf,
1079  int len
1080)
1081{
1082  while (len--) {
1083    while (TxBd[minor]->status & M8xx_BD_READY)
1084      continue;
1085    txBuf[minor] = *buf++;
1086    rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 );
1087    TxBd[minor]->buffer = &txBuf[minor];
1088    TxBd[minor]->length = 1;
1089    TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP;
1090  }
1091  return 0;
1092}
1093
1094void
1095m8xx_uart_reserve_resources(
1096  rtems_configuration_table *configuration
1097)
1098{
1099  rtems_termios_reserve_resources (configuration, NUM_PORTS);
1100}
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