[8ef3818] | 1 | /* |
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| 2 | * General Serial I/O functions. |
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| 3 | * |
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| 4 | * This file contains the functions for performing serial I/O. |
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| 5 | * The actual system calls (console_*) should be in the BSP part |
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| 6 | * of the source tree. That way different BSPs can use whichever |
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| 7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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| 8 | * this file, and it caused problems with one BSP using SCC2 |
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| 9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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| 10 | * |
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| 11 | * On-chip resources used: |
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| 12 | * resource minor note |
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| 13 | * SMC1 0 |
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| 14 | * SMC2 1 |
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| 15 | * SCC1 2 N/A. Hardwired as ethernet port |
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| 16 | * SCC2 3 |
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| 17 | * SCC3 4 |
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| 18 | * SCC4 5 |
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| 19 | * BRG1 |
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| 20 | * BRG2 |
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| 21 | * BRG3 |
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| 22 | * BRG4 |
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| 23 | * Author: Jay Monkman (jmonkman@frasca.com) |
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| 24 | * Copyright (C) 1998 by Frasca International, Inc. |
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| 25 | * |
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| 26 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: |
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| 27 | * W. Eric Norum |
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| 28 | * Saskatchewan Accelerator Laboratory |
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| 29 | * University of Saskatchewan |
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| 30 | * Saskatoon, Saskatchewan, CANADA |
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| 31 | * eric@skatter.usask.ca |
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| 32 | * |
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| 33 | * COPYRIGHT (c) 1989-1998. |
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| 34 | * On-Line Applications Research Corporation (OAR). |
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| 35 | * |
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| 36 | * Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca> |
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| 37 | * and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> |
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| 38 | * Copyright (c) 1999, National Research Council of Canada |
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| 39 | * |
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| 40 | * The license and distribution terms for this file may be |
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| 41 | * found in the file LICENSE in this distribution or at |
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| 42 | * |
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| 43 | * http://www.OARcorp.com/rtems/license.html. |
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| 44 | * |
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| 45 | * $Id$ |
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| 46 | */ |
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| 47 | |
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[61bd0301] | 48 | #include <rtems.h> |
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[8ef3818] | 49 | #include <rtems/libio.h> |
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| 50 | #include <mpc8xx.h> |
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| 51 | #include <mpc8xx/console.h> |
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[61bd0301] | 52 | #include <mpc8xx/cpm.h> |
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[8ef3818] | 53 | #include <stdlib.h> |
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| 54 | #include <unistd.h> |
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| 55 | #include <termios.h> |
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| 56 | |
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| 57 | extern rtems_cpu_table Cpu_table; |
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| 58 | |
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[8c49701] | 59 | /* BSP supplied routine */ |
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| 60 | extern int mbx8xx_console_use_maximum_buffer_size(void); |
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| 61 | |
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[8ef3818] | 62 | #ifdef EPPCBUG_SMC1 |
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| 63 | extern unsigned32 simask_copy; |
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[38dff47b] | 64 | #endif |
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[8ef3818] | 65 | |
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| 66 | /* |
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| 67 | * Interrupt-driven input buffer |
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| 68 | */ |
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| 69 | #define RXBUFSIZE 16 |
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| 70 | |
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| 71 | /* |
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| 72 | * I/O buffers and pointers to buffer descriptors. |
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| 73 | * Currently, single buffered input is done. This will work only |
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| 74 | * if the Rx interrupts are serviced quickly. |
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| 75 | * |
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| 76 | * TODO: Add a least double buffering for safety. |
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| 77 | */ |
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| 78 | static volatile char rxBuf[NUM_PORTS][RXBUFSIZE]; |
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| 79 | static volatile char txBuf[NUM_PORTS]; |
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| 80 | |
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| 81 | /* SCC/SMC buffer descriptors */ |
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| 82 | static volatile m8xxBufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS]; |
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| 83 | |
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| 84 | /* Used to track the usage of the baud rate generators */ |
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| 85 | static unsigned long brg_spd[4]; |
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| 86 | static char brg_used[4]; |
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| 87 | |
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| 88 | /* Used to track termios private data for callbacks */ |
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| 89 | struct rtems_termios_tty *ttyp[NUM_PORTS]; |
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| 90 | |
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| 91 | /* Used to record previous ISR */ |
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| 92 | static rtems_isr_entry old_handler[NUM_PORTS]; |
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| 93 | |
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| 94 | /* |
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| 95 | * Device-specific routines |
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| 96 | */ |
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| 97 | static int m8xx_get_brg_cd(int); |
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| 98 | static unsigned char m8xx_get_brg_clk(int); |
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| 99 | void m8xx_console_reserve_resources(rtems_configuration_table *); |
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| 100 | static int m8xx_smc_set_attributes(int, const struct termios*); |
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| 101 | static int m8xx_scc_set_attributes(int, const struct termios*); |
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| 102 | static rtems_isr m8xx_smc1_interrupt_handler(rtems_vector_number); |
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| 103 | static rtems_isr m8xx_smc2_interrupt_handler(rtems_vector_number); |
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| 104 | static rtems_isr m8xx_scc2_interrupt_handler(rtems_vector_number); |
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| 105 | #if defined(mpc860) |
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| 106 | static rtems_isr m8xx_scc3_interrupt_handler(rtems_vector_number); |
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| 107 | static rtems_isr m8xx_scc4_interrupt_handler(rtems_vector_number); |
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| 108 | #endif |
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| 109 | |
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| 110 | /* |
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| 111 | * Compute baud-rate-generator configuration register value |
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| 112 | */ |
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| 113 | static int |
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| 114 | m8xx_get_brg_cd (int baud) |
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| 115 | { |
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| 116 | int divisor; |
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| 117 | int div16 = 0; |
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| 118 | |
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| 119 | divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud; |
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| 120 | if (divisor > 4096) { |
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| 121 | div16 = 1; |
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| 122 | divisor = (divisor + 8) / 16; |
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| 123 | } |
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| 124 | return M8xx_BRG_EN | M8xx_BRG_EXTC_BRGCLK | |
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| 125 | ((divisor - 1) << 1) | div16; |
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| 126 | } |
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| 127 | |
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| 128 | |
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| 129 | /* |
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| 130 | * This function will fail if more that 4 baud rates have been selected |
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| 131 | * at any time since the OS started. It needs to be fixed. FIXME |
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| 132 | */ |
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| 133 | static unsigned |
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| 134 | char m8xx_get_brg_clk(int baud) |
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| 135 | { |
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| 136 | int i; |
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| 137 | |
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| 138 | /* first try to find a BRG that is already at the right speed */ |
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| 139 | for ( i = 0; i < 4; i++ ) { |
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| 140 | if ( brg_spd[i] == baud ) { |
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| 141 | break; |
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| 142 | } |
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| 143 | } |
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| 144 | |
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| 145 | if ( i == 4 ) { /* I guess we didn't find one */ |
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| 146 | for ( i = 0; i < 4; i++ ) { |
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| 147 | if ( brg_used[i] == 0 ) { |
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| 148 | break; |
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| 149 | } |
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| 150 | } |
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| 151 | } |
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| 152 | if (i != 4) { |
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| 153 | brg_used[i]++; |
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| 154 | brg_spd[i]=baud; |
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| 155 | switch (i) { |
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| 156 | case 0: |
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| 157 | m8xx.brgc1 = M8xx_BRG_RST; |
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| 158 | m8xx.brgc1 = m8xx_get_brg_cd(baud); |
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| 159 | break; |
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| 160 | case 1: |
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| 161 | m8xx.brgc2 = M8xx_BRG_RST; |
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| 162 | m8xx.brgc2 = m8xx_get_brg_cd(baud); |
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| 163 | break; |
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| 164 | case 2: |
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| 165 | m8xx.brgc3 = M8xx_BRG_RST; |
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| 166 | m8xx.brgc3 = m8xx_get_brg_cd(baud); |
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| 167 | break; |
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| 168 | case 3: |
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| 169 | m8xx.brgc4 = M8xx_BRG_RST; |
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| 170 | m8xx.brgc4 = m8xx_get_brg_cd(baud); |
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| 171 | break; |
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| 172 | } |
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| 173 | return i; |
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| 174 | } |
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| 175 | |
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| 176 | else |
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| 177 | return 0xff; |
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| 178 | } |
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| 179 | |
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| 180 | |
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| 181 | /* |
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| 182 | * Hardware-dependent portion of tcsetattr(). |
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| 183 | */ |
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| 184 | static int |
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| 185 | m8xx_smc_set_attributes (int minor, const struct termios *t) |
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| 186 | { |
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[21c8738] | 187 | int baud, brg=0, csize=0, ssize, psize; |
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| 188 | rtems_unsigned16 clen=0, cstopb, parenb, parodd, cread; |
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[8ef3818] | 189 | |
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| 190 | /* Baud rate */ |
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| 191 | switch (t->c_cflag & CBAUD) { |
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| 192 | default: baud = -1; break; |
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| 193 | case B50: baud = 50; break; |
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| 194 | case B75: baud = 75; break; |
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| 195 | case B110: baud = 110; break; |
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| 196 | case B134: baud = 134; break; |
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| 197 | case B150: baud = 150; break; |
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| 198 | case B200: baud = 200; break; |
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| 199 | case B300: baud = 300; break; |
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| 200 | case B600: baud = 600; break; |
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| 201 | case B1200: baud = 1200; break; |
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| 202 | case B1800: baud = 1800; break; |
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| 203 | case B2400: baud = 2400; break; |
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| 204 | case B4800: baud = 4800; break; |
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| 205 | case B9600: baud = 9600; break; |
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| 206 | case B19200: baud = 19200; break; |
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| 207 | case B38400: baud = 38400; break; |
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| 208 | case B57600: baud = 57600; break; |
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| 209 | case B115200: baud = 115200; break; |
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| 210 | case B230400: baud = 230400; break; |
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| 211 | case B460800: baud = 460800; break; |
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| 212 | } |
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| 213 | if (baud > 0) |
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| 214 | brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ |
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| 215 | /* at least 2 ports will be the same */ |
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| 216 | |
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| 217 | /* Number of data bits */ |
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| 218 | switch ( t->c_cflag & CSIZE ) { |
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| 219 | case CS5: csize = 5; break; |
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| 220 | case CS6: csize = 6; break; |
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| 221 | case CS7: csize = 7; break; |
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| 222 | case CS8: csize = 8; break; |
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| 223 | } |
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| 224 | |
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| 225 | /* Stop bits */ |
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| 226 | if ( t->c_cflag & CSTOPB ) { |
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| 227 | cstopb = 0x0400; /* Two stop bits */ |
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| 228 | ssize = 2; |
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| 229 | } else { |
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| 230 | cstopb = 0x0000; /* One stop bit */ |
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| 231 | ssize = 1; |
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| 232 | } |
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| 233 | |
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| 234 | /* Parity */ |
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| 235 | if ( t->c_cflag & PARENB ) { |
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| 236 | parenb = 0x0200; /* Parity enabled on Tx and Rx */ |
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| 237 | psize = 1; |
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| 238 | } else { |
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| 239 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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| 240 | psize = 0; |
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| 241 | } |
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| 242 | |
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| 243 | if ( t->c_cflag & PARODD ) |
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| 244 | parodd = 0x0000; /* Odd parity */ |
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| 245 | else |
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| 246 | parodd = 0x0100; |
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| 247 | |
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| 248 | /* |
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| 249 | * Character Length = start + data + parity + stop - 1 |
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| 250 | */ |
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| 251 | switch ( 1 + csize + psize + ssize - 1 ) { |
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| 252 | case 6: clen = 0x3000; break; |
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| 253 | case 7: clen = 0x3800; break; |
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| 254 | case 8: clen = 0x4000; break; |
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| 255 | case 9: clen = 0x4800; break; |
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| 256 | case 10: clen = 0x5000; break; |
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| 257 | case 11: clen = 0x5800; break; |
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| 258 | } |
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| 259 | |
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| 260 | if ( t->c_cflag & CREAD ) |
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| 261 | cread = 0x0023; /* UART normal operation, enable Rx and Tx */ |
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| 262 | else |
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| 263 | cread = 0x0021; /* UART normal operation, enable Tx */ |
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| 264 | |
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| 265 | /* Write the SIMODE/SMCMR registers */ |
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| 266 | switch (minor) { |
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| 267 | case SMC1_MINOR: |
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| 268 | m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) ); |
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| 269 | m8xx.smc1.smcmr = clen | cstopb | parenb | parodd | cread; |
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| 270 | break; |
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| 271 | case SMC2_MINOR: |
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| 272 | m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) ); |
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| 273 | m8xx.smc2.smcmr = clen | cstopb | parenb | parodd | cread; |
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| 274 | break; |
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| 275 | } |
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| 276 | return 0; |
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| 277 | } |
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| 278 | |
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| 279 | |
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| 280 | static int |
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| 281 | m8xx_scc_set_attributes (int minor, const struct termios *t) |
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| 282 | { |
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[21c8738] | 283 | int baud, brg=0; |
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| 284 | rtems_unsigned16 csize=0, cstopb, parenb, parodd; |
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[8ef3818] | 285 | |
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| 286 | /* Baud rate */ |
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| 287 | switch (t->c_cflag & CBAUD) { |
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| 288 | default: baud = -1; break; |
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| 289 | case B50: baud = 50; break; |
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| 290 | case B75: baud = 75; break; |
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| 291 | case B110: baud = 110; break; |
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| 292 | case B134: baud = 134; break; |
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| 293 | case B150: baud = 150; break; |
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| 294 | case B200: baud = 200; break; |
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| 295 | case B300: baud = 300; break; |
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| 296 | case B600: baud = 600; break; |
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| 297 | case B1200: baud = 1200; break; |
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| 298 | case B1800: baud = 1800; break; |
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| 299 | case B2400: baud = 2400; break; |
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| 300 | case B4800: baud = 4800; break; |
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| 301 | case B9600: baud = 9600; break; |
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| 302 | case B19200: baud = 19200; break; |
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| 303 | case B38400: baud = 38400; break; |
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| 304 | case B57600: baud = 57600; break; |
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| 305 | case B115200: baud = 115200; break; |
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| 306 | case B230400: baud = 230400; break; |
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| 307 | case B460800: baud = 460800; break; |
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| 308 | } |
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| 309 | if (baud > 0) |
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| 310 | brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ |
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| 311 | /* at least 2 ports will be the same */ |
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| 312 | /* Write the SICR register below */ |
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| 313 | |
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| 314 | /* Number of data bits */ |
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| 315 | switch ( t->c_cflag & CSIZE ) { |
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| 316 | case CS5: csize = 0x0000; break; |
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| 317 | case CS6: csize = 0x1000; break; |
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| 318 | case CS7: csize = 0x2000; break; |
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| 319 | case CS8: csize = 0x3000; break; |
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| 320 | } |
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| 321 | |
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| 322 | /* Stop bits */ |
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| 323 | if ( t->c_cflag & CSTOPB ) |
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| 324 | cstopb = 0x4000; /* Two stop bits */ |
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| 325 | else |
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| 326 | cstopb = 0x0000; /* One stop bit */ |
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| 327 | |
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| 328 | /* Parity */ |
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| 329 | if ( t->c_cflag & PARENB ) |
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| 330 | parenb = 0x0010; /* Parity enabled on Tx and Rx */ |
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| 331 | else |
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| 332 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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| 333 | |
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| 334 | if ( t->c_cflag & PARODD ) |
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| 335 | parodd = 0x0000; /* Odd parity */ |
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| 336 | else |
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| 337 | parodd = 0x000a; |
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| 338 | |
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| 339 | /* Write the SICR/PSMR Registers */ |
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| 340 | switch (minor) { |
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| 341 | case SCC2_MINOR: |
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| 342 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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| 343 | m8xx.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc2.psmr & 0x8fe0) ); |
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| 344 | break; |
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| 345 | #if defined(mpc860) |
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| 346 | case SCC3_MINOR: |
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| 347 | m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) ); |
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| 348 | m8xx.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc3.psmr & 0x8fe0) ); |
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| 349 | break; |
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| 350 | case SCC4_MINOR: |
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| 351 | m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) ); |
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| 352 | m8xx.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc4.psmr & 0x8fe0) ); |
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| 353 | break; |
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| 354 | #endif |
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| 355 | } |
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| 356 | |
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| 357 | return 0; |
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| 358 | } |
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| 359 | |
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| 360 | |
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| 361 | int |
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| 362 | m8xx_uart_setAttributes( |
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| 363 | int minor, |
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| 364 | const struct termios *t |
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| 365 | ) |
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| 366 | { |
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| 367 | /* |
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| 368 | * Check that port number is valid |
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| 369 | */ |
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| 370 | if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) |
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| 371 | return 0; |
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| 372 | |
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| 373 | switch (minor) { |
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| 374 | case SMC1_MINOR: |
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| 375 | case SMC2_MINOR: |
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| 376 | return m8xx_smc_set_attributes( minor, t ); |
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| 377 | |
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| 378 | case SCC2_MINOR: |
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| 379 | case SCC3_MINOR: |
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| 380 | case SCC4_MINOR: |
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| 381 | return m8xx_scc_set_attributes( minor, t ); |
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| 382 | } |
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| 383 | return 0; |
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| 384 | } |
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| 385 | |
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| 386 | |
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| 387 | /* |
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| 388 | * Interrupt handlers |
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| 389 | */ |
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| 390 | static rtems_isr |
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| 391 | m8xx_scc2_interrupt_handler (rtems_vector_number v) |
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| 392 | { |
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| 393 | int nb_overflow; |
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| 394 | |
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| 395 | /* |
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| 396 | * Buffer received? |
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| 397 | */ |
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| 398 | if ((m8xx.scc2.sccm & M8xx_SCCE_RX) && (m8xx.scc2.scce & M8xx_SCCE_RX)) { |
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| 399 | m8xx.scc2.scce = M8xx_SCCE_RX; /* Clear the event */ |
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| 400 | |
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| 401 | |
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| 402 | /* Check that the buffer is ours */ |
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| 403 | if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
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[5e77d129] | 404 | rtems_cache_invalidate_multiple_data_lines( |
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[61bd0301] | 405 | (const void *) RxBd[SCC2_MINOR]->buffer, |
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[8ef3818] | 406 | RxBd[SCC2_MINOR]->length ); |
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| 407 | nb_overflow = rtems_termios_enqueue_raw_characters( |
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| 408 | (void *)ttyp[SCC2_MINOR], |
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| 409 | (char *)RxBd[SCC2_MINOR]->buffer, |
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| 410 | (int)RxBd[SCC2_MINOR]->length ); |
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| 411 | RxBd[SCC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
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| 412 | M8xx_BD_INTERRUPT; |
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| 413 | } |
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| 414 | } |
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| 415 | |
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| 416 | /* |
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| 417 | * Buffer transmitted? |
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| 418 | */ |
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| 419 | if (m8xx.scc2.scce & M8xx_SCCE_TX) { |
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| 420 | m8xx.scc2.scce = M8xx_SCCE_TX; /* Clear the event */ |
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| 421 | |
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| 422 | /* Check that the buffer is ours */ |
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| 423 | if ((TxBd[SCC2_MINOR]->status & M8xx_BD_READY) == 0) |
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| 424 | rtems_termios_dequeue_characters ( |
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| 425 | (void *)ttyp[SCC2_MINOR], |
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| 426 | (int)TxBd[SCC2_MINOR]->length); |
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| 427 | } |
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| 428 | m8xx.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ |
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| 429 | } |
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| 430 | |
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| 431 | |
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| 432 | #ifdef mpc860 |
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| 433 | static rtems_isr |
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| 434 | m8xx_scc3_interrupt_handler (rtems_vector_number v) |
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| 435 | { |
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| 436 | int nb_overflow; |
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| 437 | |
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| 438 | /* |
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| 439 | * Buffer received? |
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| 440 | */ |
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| 441 | if ((m8xx.scc3.sccm & M8xx_SCCE_RX) && (m8xx.scc3.scce & M8xx_SCCE_RX)) { |
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| 442 | m8xx.scc3.scce = M8xx_SCCE_RX; /* Clear the event */ |
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| 443 | |
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| 444 | |
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| 445 | /* Check that the buffer is ours */ |
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| 446 | if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
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[5e77d129] | 447 | rtems_cache_invalidate_multiple_data_lines( |
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[61bd0301] | 448 | (const void *) RxBd[SCC3_MINOR]->buffer, |
---|
[8ef3818] | 449 | RxBd[SCC3_MINOR]->length ); |
---|
| 450 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 451 | (void *)ttyp[SCC3_MINOR], |
---|
| 452 | (char *)RxBd[SCC3_MINOR]->buffer, |
---|
| 453 | (int)RxBd[SCC3_MINOR]->length ); |
---|
| 454 | RxBd[SCC3_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
| 455 | M8xx_BD_INTERRUPT; |
---|
| 456 | } |
---|
| 457 | } |
---|
| 458 | |
---|
| 459 | /* |
---|
| 460 | * Buffer transmitted? |
---|
| 461 | */ |
---|
| 462 | if (m8xx.scc3.scce & M8xx_SCCE_TX) { |
---|
| 463 | m8xx.scc3.scce = M8xx_SCCE_TX; /* Clear the event */ |
---|
| 464 | |
---|
| 465 | /* Check that the buffer is ours */ |
---|
| 466 | if ((TxBd[SCC3_MINOR]->status & M8xx_BD_READY) == 0) |
---|
| 467 | rtems_termios_dequeue_characters ( |
---|
| 468 | (void *)ttyp[SCC3_MINOR], |
---|
| 469 | (int)TxBd[SCC3_MINOR]->length); |
---|
| 470 | } |
---|
| 471 | m8xx.cisr = 1UL << 28; /* Clear SCC3 interrupt-in-service bit */ |
---|
| 472 | } |
---|
| 473 | |
---|
| 474 | |
---|
| 475 | static rtems_isr |
---|
| 476 | m8xx_scc4_interrupt_handler (rtems_vector_number v) |
---|
| 477 | { |
---|
| 478 | int nb_overflow; |
---|
| 479 | |
---|
| 480 | /* |
---|
| 481 | * Buffer received? |
---|
| 482 | */ |
---|
| 483 | if ((m8xx.scc4.sccm & M8xx_SCCE_RX) && (m8xx.scc4.scce & M8xx_SCCE_RX)) { |
---|
| 484 | m8xx.scc4.scce = M8xx_SCCE_RX; /* Clear the event */ |
---|
| 485 | |
---|
| 486 | |
---|
| 487 | /* Check that the buffer is ours */ |
---|
| 488 | if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
[5e77d129] | 489 | rtems_cache_invalidate_multiple_data_lines( |
---|
[61bd0301] | 490 | (const void *) RxBd[SCC4_MINOR]->buffer, |
---|
[8ef3818] | 491 | RxBd[SCC4_MINOR]->length ); |
---|
| 492 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 493 | (void *)ttyp[SCC4_MINOR], |
---|
| 494 | (char *)RxBd[SCC4_MINOR]->buffer, |
---|
| 495 | (int)RxBd[SCC4_MINOR]->length ); |
---|
| 496 | RxBd[SCC4_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
| 497 | M8xx_BD_INTERRUPT; |
---|
| 498 | } |
---|
| 499 | } |
---|
| 500 | |
---|
| 501 | /* |
---|
| 502 | * Buffer transmitted? |
---|
| 503 | */ |
---|
| 504 | if (m8xx.scc4.scce & M8xx_SCCE_TX) { |
---|
| 505 | m8xx.scc4.scce = M8xx_SCCE_TX; /* Clear the event */ |
---|
| 506 | |
---|
| 507 | /* Check that the buffer is ours */ |
---|
| 508 | if ((TxBd[SCC4_MINOR]->status & M8xx_BD_READY) == 0) |
---|
| 509 | rtems_termios_dequeue_characters ( |
---|
| 510 | (void *)ttyp[SCC4_MINOR], |
---|
| 511 | (int)TxBd[SCC4_MINOR]->length); |
---|
| 512 | } |
---|
| 513 | m8xx.cisr = 1UL << 27; /* Clear SCC4 interrupt-in-service bit */ |
---|
| 514 | } |
---|
| 515 | #endif |
---|
| 516 | |
---|
| 517 | static rtems_isr |
---|
| 518 | m8xx_smc1_interrupt_handler (rtems_vector_number v) |
---|
| 519 | { |
---|
| 520 | int nb_overflow; |
---|
| 521 | |
---|
| 522 | /* |
---|
| 523 | * Buffer received? |
---|
| 524 | */ |
---|
| 525 | if (m8xx.smc1.smce & M8xx_SMCE_RX) { |
---|
| 526 | m8xx.smc1.smce = M8xx_SMCE_RX; /* Clear the event */ |
---|
| 527 | |
---|
| 528 | |
---|
| 529 | /* Check that the buffer is ours */ |
---|
| 530 | if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
[5e77d129] | 531 | rtems_cache_invalidate_multiple_data_lines( |
---|
[61bd0301] | 532 | (const void *) RxBd[SMC1_MINOR]->buffer, |
---|
[8ef3818] | 533 | RxBd[SMC1_MINOR]->length ); |
---|
| 534 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 535 | (void *)ttyp[SMC1_MINOR], |
---|
| 536 | (char *)RxBd[SMC1_MINOR]->buffer, |
---|
| 537 | (int)RxBd[SMC1_MINOR]->length ); |
---|
| 538 | RxBd[SMC1_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
| 539 | M8xx_BD_INTERRUPT; |
---|
| 540 | } |
---|
| 541 | } |
---|
| 542 | |
---|
| 543 | /* |
---|
| 544 | * Buffer transmitted? |
---|
| 545 | */ |
---|
| 546 | if (m8xx.smc1.smce & M8xx_SMCE_TX) { |
---|
| 547 | m8xx.smc1.smce = M8xx_SMCE_TX; /* Clear the event */ |
---|
| 548 | |
---|
| 549 | /* Check that the buffer is ours */ |
---|
| 550 | if ((TxBd[SMC1_MINOR]->status & M8xx_BD_READY) == 0) |
---|
| 551 | rtems_termios_dequeue_characters ( |
---|
| 552 | (void *)ttyp[SMC1_MINOR], |
---|
| 553 | (int)TxBd[SMC1_MINOR]->length); |
---|
| 554 | } |
---|
| 555 | m8xx.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ |
---|
| 556 | } |
---|
| 557 | |
---|
| 558 | |
---|
| 559 | static rtems_isr |
---|
| 560 | m8xx_smc2_interrupt_handler (rtems_vector_number v) |
---|
| 561 | { |
---|
| 562 | int nb_overflow; |
---|
| 563 | |
---|
| 564 | /* |
---|
| 565 | * Buffer received? |
---|
| 566 | */ |
---|
| 567 | if (m8xx.smc2.smce & M8xx_SMCE_RX) { |
---|
| 568 | m8xx.smc2.smce = M8xx_SMCE_RX; /* Clear the event */ |
---|
| 569 | |
---|
| 570 | |
---|
| 571 | /* Check that the buffer is ours */ |
---|
| 572 | if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { |
---|
[5e77d129] | 573 | rtems_cache_invalidate_multiple_data_lines( |
---|
[61bd0301] | 574 | (const void *) RxBd[SMC2_MINOR]->buffer, |
---|
[8ef3818] | 575 | RxBd[SMC2_MINOR]->length ); |
---|
| 576 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 577 | (void *)ttyp[SMC2_MINOR], |
---|
| 578 | (char *)RxBd[SMC2_MINOR]->buffer, |
---|
| 579 | (int)RxBd[SMC2_MINOR]->length ); |
---|
| 580 | RxBd[SMC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | |
---|
| 581 | M8xx_BD_INTERRUPT; |
---|
| 582 | } |
---|
| 583 | } |
---|
| 584 | |
---|
| 585 | /* |
---|
| 586 | * Buffer transmitted? |
---|
| 587 | */ |
---|
| 588 | if (m8xx.smc2.smce & M8xx_SMCE_TX) { |
---|
| 589 | m8xx.smc2.smce = M8xx_SMCE_TX; /* Clear the event */ |
---|
| 590 | |
---|
| 591 | /* Check that the buffer is ours */ |
---|
| 592 | if ((TxBd[SMC2_MINOR]->status & M8xx_BD_READY) == 0) |
---|
| 593 | rtems_termios_dequeue_characters ( |
---|
| 594 | (void *)ttyp[SMC2_MINOR], |
---|
| 595 | (int)TxBd[SMC2_MINOR]->length); |
---|
| 596 | } |
---|
| 597 | m8xx.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ |
---|
| 598 | } |
---|
| 599 | |
---|
| 600 | |
---|
| 601 | void |
---|
| 602 | m8xx_uart_scc_initialize (int minor) |
---|
| 603 | { |
---|
| 604 | unsigned char brg; |
---|
[21c8738] | 605 | volatile m8xxSCCparms_t *sccparms = 0; |
---|
| 606 | volatile m8xxSCCRegisters_t *sccregs = 0; |
---|
[8ef3818] | 607 | |
---|
| 608 | /* |
---|
| 609 | * Check that minor number is valid |
---|
| 610 | */ |
---|
| 611 | if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) |
---|
| 612 | return; |
---|
| 613 | |
---|
| 614 | /* Get the sicr clock source bit values for 9600 bps */ |
---|
| 615 | brg = m8xx_get_brg_clk(9600); |
---|
| 616 | |
---|
| 617 | /* |
---|
| 618 | * Allocate buffer descriptors |
---|
| 619 | */ |
---|
| 620 | RxBd[minor] = m8xx_bd_allocate(1); |
---|
| 621 | TxBd[minor] = m8xx_bd_allocate(1); |
---|
| 622 | |
---|
| 623 | /* |
---|
| 624 | * Get the address of the parameter RAM for the specified port, |
---|
| 625 | * configure I/O port A,C & D and put SMC in NMSI mode, connect |
---|
| 626 | * the SCC to the appropriate BRG. |
---|
| 627 | * |
---|
| 628 | * SCC2 TxD is shared with port A bit 12 |
---|
| 629 | * SCC2 RxD is shared with port A bit 13 |
---|
| 630 | * SCC1 TxD is shared with port A bit 14 |
---|
| 631 | * SCC1 RxD is shared with port A bit 15 |
---|
| 632 | * SCC4 DCD is shared with port C bit 4 |
---|
| 633 | * SCC4 CTS is shared with port C bit 5 |
---|
| 634 | * SCC3 DCD is shared with port C bit 6 |
---|
| 635 | * SCC3 CTS is shared with port C bit 7 |
---|
| 636 | * SCC2 DCD is shared with port C bit 8 |
---|
| 637 | * SCC2 CTS is shared with port C bit 9 |
---|
| 638 | * SCC1 DCD is shared with port C bit 10 |
---|
| 639 | * SCC1 CTS is shared with port C bit 11 |
---|
| 640 | * SCC2 RTS is shared with port C bit 14 |
---|
| 641 | * SCC1 RTS is shared with port C bit 15 |
---|
| 642 | * SCC4 RTS is shared with port D bit 6 |
---|
| 643 | * SCC3 RTS is shared with port D bit 7 |
---|
| 644 | * SCC4 TxD is shared with port D bit 8 |
---|
| 645 | * SCC4 RxD is shared with port D bit 9 |
---|
| 646 | * SCC3 TxD is shared with port D bit 10 |
---|
| 647 | * SCC3 RxD is shared with port D bit 11 |
---|
| 648 | */ |
---|
| 649 | switch (minor) { |
---|
| 650 | case SCC2_MINOR: |
---|
| 651 | sccparms = &m8xx.scc2p; |
---|
| 652 | sccregs = &m8xx.scc2; |
---|
| 653 | |
---|
| 654 | m8xx.papar |= 0x000C; /* PA12 & PA13 are dedicated peripheral pins */ |
---|
| 655 | m8xx.padir &= ~0x000C; /* PA13 & PA12 must not drive the UART lines */ |
---|
| 656 | m8xx.paodr &= ~0x000C; /* PA12 & PA13 are not open drain */ |
---|
| 657 | m8xx.pcpar |= 0x0002; /* PC14 is SCC2 RTS */ |
---|
| 658 | m8xx.pcpar &= ~0x00C0; /* PC8 & PC9 are SCC2 DCD and CTS */ |
---|
| 659 | m8xx.pcdir &= ~0x00C2; /* PC8, PC9 & PC14 must not drive the UART lines */ |
---|
| 660 | m8xx.pcso |= 0x00C0; /* Enable DCD and CTS inputs */ |
---|
| 661 | |
---|
| 662 | m8xx.sicr &= 0xFFFF00FF; /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */ |
---|
| 663 | m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */ |
---|
| 664 | break; |
---|
| 665 | |
---|
| 666 | #ifdef mpc860 |
---|
| 667 | case SCC3_MINOR: |
---|
| 668 | sccparms = &m8xx.scc3p; |
---|
| 669 | sccregs = &m8xx.scc3; |
---|
| 670 | |
---|
| 671 | m8xx.pcpar &= ~0x0300; /* PC6 & PC7 are SCC3 DCD and CTS */ |
---|
| 672 | m8xx.pcdir &= ~0x0300; /* PC6 & PC7 must not drive the UART lines */ |
---|
| 673 | m8xx.pcso |= 0x0300; /* Enable DCD and CTS inputs */ |
---|
| 674 | m8xx.pdpar |= 0x0130; /* PD7, PD10 & PD11 are dedicated peripheral pins */ |
---|
| 675 | |
---|
| 676 | m8xx.sicr &= 0xFF00FFFF; /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */ |
---|
| 677 | m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */ |
---|
| 678 | break; |
---|
| 679 | |
---|
| 680 | case SCC4_MINOR: |
---|
| 681 | sccparms = &m8xx.scc4p; |
---|
| 682 | sccregs = &m8xx.scc4; |
---|
| 683 | |
---|
| 684 | m8xx.pcpar &= ~0x0C00; /* PC4 & PC5 are SCC4 DCD and CTS */ |
---|
| 685 | m8xx.pcdir &= ~0x0C00; /* PC4 & PC5 must not drive the UART lines */ |
---|
| 686 | m8xx.pcso |= 0x0C00; /* Enable DCD and CTS inputs */ |
---|
| 687 | m8xx.pdpar |= 0x02C0; /* PD6, PD8 & PD9 are dedicated peripheral pins */ |
---|
| 688 | |
---|
| 689 | m8xx.sicr &= 0x00FFFFFF; /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */ |
---|
| 690 | m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */ |
---|
| 691 | break; |
---|
| 692 | #endif |
---|
| 693 | } |
---|
| 694 | |
---|
| 695 | /* |
---|
| 696 | * Set up SDMA |
---|
| 697 | */ |
---|
| 698 | m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */ |
---|
| 699 | |
---|
| 700 | /* |
---|
| 701 | * Set up the SCC parameter RAM. |
---|
| 702 | */ |
---|
| 703 | sccparms->rbase = (char *)RxBd[minor] - (char *)&m8xx; |
---|
| 704 | sccparms->tbase = (char *)TxBd[minor] - (char *)&m8xx; |
---|
| 705 | |
---|
| 706 | sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); |
---|
| 707 | sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); |
---|
[8c49701] | 708 | if ( mbx8xx_console_use_maximum_buffer_size() ) |
---|
[f018b1a] | 709 | sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
| 710 | else |
---|
| 711 | sccparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
[8ef3818] | 712 | sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
| 713 | sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
| 714 | |
---|
| 715 | sccparms->un.uart.parec = 0; /* Clear parity error counter */ |
---|
| 716 | sccparms->un.uart.frmec = 0; /* Clear framing error counter */ |
---|
| 717 | sccparms->un.uart.nosec = 0; /* Clear noise counter */ |
---|
| 718 | sccparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
| 719 | |
---|
| 720 | sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */ |
---|
| 721 | sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */ |
---|
| 722 | sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */ |
---|
| 723 | |
---|
| 724 | sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */ |
---|
| 725 | sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */ |
---|
| 726 | sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */ |
---|
| 727 | sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */ |
---|
| 728 | sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */ |
---|
| 729 | sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */ |
---|
| 730 | sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */ |
---|
| 731 | sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */ |
---|
| 732 | |
---|
| 733 | |
---|
| 734 | sccparms->un.uart.rccm = 0xc0ff; /* No masking */ |
---|
| 735 | |
---|
| 736 | /* |
---|
| 737 | * Set up the Receive Buffer Descriptor |
---|
| 738 | */ |
---|
| 739 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
| 740 | RxBd[minor]->length = 0; |
---|
| 741 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
| 742 | |
---|
| 743 | /* |
---|
| 744 | * Setup the Transmit Buffer Descriptor |
---|
| 745 | */ |
---|
| 746 | TxBd[minor]->status = M8xx_BD_WRAP; |
---|
| 747 | |
---|
| 748 | /* |
---|
| 749 | * Set up SCCx general and protocol-specific mode registers |
---|
| 750 | */ |
---|
| 751 | sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */ |
---|
| 752 | sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/ |
---|
| 753 | sccregs->scce = ~0; /* Clear any pending event */ |
---|
| 754 | sccregs->sccm = 0; /* Mask all interrupt/event sources */ |
---|
| 755 | sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit, |
---|
| 756 | 8 data bits, no parity */ |
---|
| 757 | sccregs->dsr = 0x7E7E; /* No fractional stop bits */ |
---|
| 758 | sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */ |
---|
| 759 | |
---|
| 760 | /* |
---|
| 761 | * Initialize the Rx and Tx with the new parameters. |
---|
| 762 | */ |
---|
| 763 | switch (minor) { |
---|
| 764 | case SCC2_MINOR: |
---|
| 765 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC2); |
---|
| 766 | break; |
---|
| 767 | |
---|
| 768 | #ifdef mpc860 |
---|
| 769 | case SCC3_MINOR: |
---|
| 770 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC3); |
---|
| 771 | break; |
---|
| 772 | case SCC4_MINOR: |
---|
| 773 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC4); |
---|
| 774 | break; |
---|
| 775 | #endif |
---|
| 776 | } |
---|
[f018b1a] | 777 | #if NVRAM_CONFIGURE == 1 |
---|
| 778 | if ( (nvram->console_mode & 0x06) == 0x02 ) { |
---|
| 779 | switch (minor) { |
---|
| 780 | case SCC2_MINOR: |
---|
| 781 | rtems_interrupt_catch (m8xx_scc2_interrupt_handler, |
---|
| 782 | PPC_IRQ_CPM_SCC2, |
---|
| 783 | &old_handler[minor]); |
---|
| 784 | |
---|
| 785 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 786 | m8xx.cimr |= 1UL << 29; /* Enable SCC2 interrupts */ |
---|
| 787 | break; |
---|
| 788 | |
---|
| 789 | #ifdef mpc860 |
---|
| 790 | case SCC3_MINOR: |
---|
| 791 | rtems_interrupt_catch (m8xx_scc3_interrupt_handler, |
---|
| 792 | PPC_IRQ_CPM_SCC3, |
---|
| 793 | &old_handler[minor]); |
---|
| 794 | |
---|
| 795 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 796 | m8xx.cimr |= 1UL << 28; /* Enable SCC2 interrupts */ |
---|
| 797 | break; |
---|
| 798 | |
---|
| 799 | case SCC4_MINOR: |
---|
| 800 | rtems_interrupt_catch (m8xx_scc4_interrupt_handler, |
---|
| 801 | PPC_IRQ_CPM_SCC4, |
---|
| 802 | &old_handler[minor]); |
---|
| 803 | |
---|
| 804 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 805 | m8xx.cimr |= 1UL << 27; /* Enable SCC2 interrupts */ |
---|
| 806 | break; |
---|
| 807 | #endif /* mpc860 */ |
---|
| 808 | } |
---|
| 809 | } |
---|
| 810 | |
---|
| 811 | #else /* NVRAM_CONFIGURE != 1 */ |
---|
| 812 | |
---|
[38dff47b] | 813 | #if UARTS_IO_MODE == 1 |
---|
[8ef3818] | 814 | switch (minor) { |
---|
| 815 | case SCC2_MINOR: |
---|
| 816 | rtems_interrupt_catch (m8xx_scc2_interrupt_handler, |
---|
| 817 | PPC_IRQ_CPM_SCC2, |
---|
| 818 | &old_handler[minor]); |
---|
| 819 | |
---|
| 820 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 821 | m8xx.cimr |= 1UL << 29; /* Enable SCC2 interrupts */ |
---|
| 822 | break; |
---|
| 823 | |
---|
| 824 | #ifdef mpc860 |
---|
| 825 | case SCC3_MINOR: |
---|
| 826 | rtems_interrupt_catch (m8xx_scc3_interrupt_handler, |
---|
| 827 | PPC_IRQ_CPM_SCC3, |
---|
| 828 | &old_handler[minor]); |
---|
| 829 | |
---|
| 830 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 831 | m8xx.cimr |= 1UL << 28; /* Enable SCC2 interrupts */ |
---|
| 832 | break; |
---|
| 833 | |
---|
| 834 | case SCC4_MINOR: |
---|
| 835 | rtems_interrupt_catch (m8xx_scc4_interrupt_handler, |
---|
| 836 | PPC_IRQ_CPM_SCC4, |
---|
| 837 | &old_handler[minor]); |
---|
| 838 | |
---|
| 839 | sccregs->sccm = 3; /* Enable SCC2 Rx & Tx interrupts */ |
---|
| 840 | m8xx.cimr |= 1UL << 27; /* Enable SCC2 interrupts */ |
---|
| 841 | break; |
---|
| 842 | #endif /* mpc860 */ |
---|
| 843 | } |
---|
[38dff47b] | 844 | #endif /* UARTS_IO_MODE */ |
---|
[f018b1a] | 845 | |
---|
| 846 | #endif /* NVRAM_CONFIGURE */ |
---|
[8ef3818] | 847 | } |
---|
| 848 | |
---|
| 849 | |
---|
| 850 | void |
---|
| 851 | m8xx_uart_smc_initialize (int minor) |
---|
| 852 | { |
---|
| 853 | unsigned char brg; |
---|
[21c8738] | 854 | volatile m8xxSMCparms_t *smcparms = 0; |
---|
| 855 | volatile m8xxSMCRegisters_t *smcregs = 0; |
---|
[8ef3818] | 856 | |
---|
| 857 | /* |
---|
| 858 | * Check that minor number is valid |
---|
| 859 | */ |
---|
| 860 | if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) |
---|
| 861 | return; |
---|
| 862 | |
---|
| 863 | /* Get the simode clock source bit values for 9600 bps */ |
---|
| 864 | brg = m8xx_get_brg_clk(9600); |
---|
| 865 | |
---|
| 866 | /* |
---|
| 867 | * Allocate buffer descriptors |
---|
| 868 | */ |
---|
| 869 | RxBd[minor] = m8xx_bd_allocate (1); |
---|
| 870 | TxBd[minor] = m8xx_bd_allocate (1); |
---|
| 871 | |
---|
| 872 | /* |
---|
| 873 | * Get the address of the parameter RAM for the specified port, |
---|
| 874 | * configure I/O port B and put SMC in NMSI mode, connect the |
---|
| 875 | * SMC to the appropriate BRG. |
---|
| 876 | * |
---|
| 877 | * SMC2 RxD is shared with port B bit 20 |
---|
| 878 | * SMC2 TxD is shared with port B bit 21 |
---|
| 879 | * SMC1 RxD is shared with port B bit 24 |
---|
| 880 | * SMC1 TxD is shared with port B bit 25 |
---|
| 881 | */ |
---|
| 882 | switch (minor) { |
---|
| 883 | case SMC1_MINOR: |
---|
| 884 | smcparms = &m8xx.smc1p; |
---|
| 885 | smcregs = &m8xx.smc1; |
---|
| 886 | |
---|
| 887 | m8xx.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ |
---|
| 888 | m8xx.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ |
---|
| 889 | m8xx.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ |
---|
| 890 | |
---|
| 891 | m8xx.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */ |
---|
| 892 | m8xx.simode |= brg << 12; /* SMC1CS = brg */ |
---|
| 893 | break; |
---|
| 894 | |
---|
| 895 | case SMC2_MINOR: |
---|
| 896 | smcparms = &m8xx.smc2p; |
---|
| 897 | smcregs = &m8xx.smc2; |
---|
| 898 | |
---|
| 899 | m8xx.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ |
---|
| 900 | m8xx.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ |
---|
| 901 | m8xx.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ |
---|
| 902 | |
---|
| 903 | m8xx.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ |
---|
| 904 | m8xx.simode |= brg << 28; /* SMC2CS = brg */ |
---|
| 905 | break; |
---|
| 906 | } |
---|
| 907 | |
---|
| 908 | /* |
---|
| 909 | * Set up SMC1 parameter RAM common to all protocols |
---|
| 910 | */ |
---|
| 911 | smcparms->rbase = (char *)RxBd[minor] - (char *)&m8xx; |
---|
| 912 | smcparms->tbase = (char *)TxBd[minor] - (char *)&m8xx; |
---|
| 913 | smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); |
---|
| 914 | smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); |
---|
[f018b1a] | 915 | #if NVRAM_CONFIGURE == 1 |
---|
| 916 | if ( (nvram->console_mode & 0x06) == 0x02 ) |
---|
| 917 | smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
| 918 | else |
---|
| 919 | smcparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
| 920 | #else |
---|
[38dff47b] | 921 | #if UARTS_IO_MODE == 1 |
---|
[8ef3818] | 922 | smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
| 923 | #else |
---|
| 924 | smcparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
[f018b1a] | 925 | #endif |
---|
[8ef3818] | 926 | #endif |
---|
| 927 | |
---|
| 928 | /* |
---|
| 929 | * Set up SMC1 parameter RAM UART-specific parameters |
---|
| 930 | */ |
---|
| 931 | smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
| 932 | smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
| 933 | smcparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
| 934 | |
---|
| 935 | /* |
---|
| 936 | * Set up the Receive Buffer Descriptor |
---|
| 937 | */ |
---|
| 938 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
| 939 | RxBd[minor]->length = 0; |
---|
| 940 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
| 941 | |
---|
| 942 | /* |
---|
| 943 | * Setup the Transmit Buffer Descriptor |
---|
| 944 | */ |
---|
| 945 | TxBd[minor]->status = M8xx_BD_WRAP; |
---|
| 946 | |
---|
| 947 | /* |
---|
| 948 | * Set up SMCx general and protocol-specific mode registers |
---|
| 949 | */ |
---|
| 950 | smcregs->smce = ~0; /* Clear any pending events */ |
---|
| 951 | smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */ |
---|
| 952 | smcregs->smcmr = M8xx_SMCMR_CLEN(9) | M8xx_SMCMR_SM_UART; |
---|
| 953 | |
---|
| 954 | /* |
---|
| 955 | * Send "Init parameters" command |
---|
| 956 | */ |
---|
| 957 | switch (minor) { |
---|
| 958 | case SMC1_MINOR: |
---|
| 959 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC1); |
---|
| 960 | break; |
---|
| 961 | |
---|
| 962 | case SMC2_MINOR: |
---|
| 963 | m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2); |
---|
| 964 | break; |
---|
| 965 | } |
---|
| 966 | |
---|
| 967 | /* |
---|
| 968 | * Enable receiver and transmitter |
---|
| 969 | */ |
---|
| 970 | smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN; |
---|
[f018b1a] | 971 | #if NVRAM_CONFIGURE == 1 |
---|
| 972 | if ( (nvram->console_mode & 0x06) == 0x02 ) { |
---|
| 973 | switch (minor) { |
---|
| 974 | case SMC1_MINOR: |
---|
| 975 | rtems_interrupt_catch (m8xx_smc1_interrupt_handler, |
---|
| 976 | PPC_IRQ_CPM_SMC1, |
---|
| 977 | &old_handler[minor]); |
---|
| 978 | |
---|
| 979 | smcregs->smcm = 3; /* Enable SMC1 Rx & Tx interrupts */ |
---|
| 980 | m8xx.cimr |= 1UL << 4; /* Enable SMC1 interrupts */ |
---|
| 981 | break; |
---|
| 982 | |
---|
| 983 | case SMC2_MINOR: |
---|
| 984 | rtems_interrupt_catch (m8xx_smc2_interrupt_handler, |
---|
| 985 | PPC_IRQ_CPM_SMC2, |
---|
| 986 | &old_handler[minor]); |
---|
| 987 | |
---|
| 988 | smcregs->smcm = 3; /* Enable SMC2 Rx & Tx interrupts */ |
---|
| 989 | m8xx.cimr |= 1UL << 3; /* Enable SMC2 interrupts */ |
---|
| 990 | break; |
---|
| 991 | } |
---|
| 992 | } |
---|
| 993 | #else |
---|
[38dff47b] | 994 | #if UARTS_IO_MODE == 1 |
---|
[8ef3818] | 995 | switch (minor) { |
---|
| 996 | case SMC1_MINOR: |
---|
| 997 | rtems_interrupt_catch (m8xx_smc1_interrupt_handler, |
---|
| 998 | PPC_IRQ_CPM_SMC1, |
---|
| 999 | &old_handler[minor]); |
---|
| 1000 | |
---|
| 1001 | smcregs->smcm = 3; /* Enable SMC1 Rx & Tx interrupts */ |
---|
| 1002 | m8xx.cimr |= 1UL << 4; /* Enable SMC1 interrupts */ |
---|
| 1003 | break; |
---|
| 1004 | |
---|
| 1005 | case SMC2_MINOR: |
---|
| 1006 | rtems_interrupt_catch (m8xx_smc2_interrupt_handler, |
---|
| 1007 | PPC_IRQ_CPM_SMC2, |
---|
| 1008 | &old_handler[minor]); |
---|
| 1009 | |
---|
| 1010 | smcregs->smcm = 3; /* Enable SMC2 Rx & Tx interrupts */ |
---|
| 1011 | m8xx.cimr |= 1UL << 3; /* Enable SMC2 interrupts */ |
---|
| 1012 | break; |
---|
| 1013 | } |
---|
| 1014 | #endif |
---|
[f018b1a] | 1015 | |
---|
| 1016 | #endif |
---|
[8ef3818] | 1017 | } |
---|
| 1018 | |
---|
| 1019 | void |
---|
| 1020 | m8xx_uart_initialize(void) |
---|
| 1021 | { |
---|
| 1022 | int i; |
---|
| 1023 | |
---|
| 1024 | for (i=0; i < 4; i++) { |
---|
| 1025 | brg_spd[i] = 0; |
---|
| 1026 | brg_used[i] = 0; |
---|
| 1027 | } |
---|
| 1028 | } |
---|
| 1029 | |
---|
| 1030 | |
---|
| 1031 | void |
---|
| 1032 | m8xx_uart_interrupts_initialize(void) |
---|
| 1033 | { |
---|
| 1034 | #ifdef mpc860 |
---|
| 1035 | m8xx.cicr = 0x00E43F80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
| 1036 | SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */ |
---|
| 1037 | #else |
---|
| 1038 | m8xx.cicr = 0x00043F80; /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */ |
---|
| 1039 | #endif |
---|
[38dff47b] | 1040 | m8xx.simask |= M8xx_SIMASK_LVM1; /* Enable level interrupts */ |
---|
[8ef3818] | 1041 | #ifdef EPPCBUG_SMC1 |
---|
[38dff47b] | 1042 | simask_copy = m8xx.simask; |
---|
| 1043 | #endif |
---|
[8ef3818] | 1044 | } |
---|
| 1045 | |
---|
| 1046 | |
---|
| 1047 | int |
---|
| 1048 | m8xx_uart_pollRead( |
---|
| 1049 | int minor |
---|
| 1050 | ) |
---|
| 1051 | { |
---|
| 1052 | unsigned char c; |
---|
| 1053 | |
---|
| 1054 | if (RxBd[minor]->status & M8xx_BD_EMPTY) { |
---|
| 1055 | return -1; |
---|
| 1056 | } |
---|
[5e77d129] | 1057 | rtems_cache_invalidate_multiple_data_lines( |
---|
[61bd0301] | 1058 | (const void *) RxBd[minor]->buffer, |
---|
| 1059 | RxBd[minor]->length |
---|
| 1060 | ); |
---|
[8ef3818] | 1061 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
| 1062 | RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP; |
---|
| 1063 | return c; |
---|
| 1064 | } |
---|
| 1065 | |
---|
| 1066 | |
---|
| 1067 | /* |
---|
| 1068 | * TODO: Get a free buffer and set it up. |
---|
| 1069 | */ |
---|
| 1070 | int |
---|
| 1071 | m8xx_uart_write( |
---|
| 1072 | int minor, |
---|
| 1073 | const char *buf, |
---|
| 1074 | int len |
---|
| 1075 | ) |
---|
| 1076 | { |
---|
[5e77d129] | 1077 | rtems_cache_flush_multiple_data_lines( buf, len ); |
---|
[8ef3818] | 1078 | TxBd[minor]->buffer = (char *) buf; |
---|
| 1079 | TxBd[minor]->length = len; |
---|
| 1080 | TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; |
---|
| 1081 | return 0; |
---|
| 1082 | } |
---|
| 1083 | |
---|
| 1084 | |
---|
| 1085 | int |
---|
| 1086 | m8xx_uart_pollWrite( |
---|
| 1087 | int minor, |
---|
| 1088 | const char *buf, |
---|
| 1089 | int len |
---|
| 1090 | ) |
---|
| 1091 | { |
---|
| 1092 | while (len--) { |
---|
| 1093 | while (TxBd[minor]->status & M8xx_BD_READY) |
---|
| 1094 | continue; |
---|
| 1095 | txBuf[minor] = *buf++; |
---|
[21c8738] | 1096 | rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 ); |
---|
[8ef3818] | 1097 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
| 1098 | TxBd[minor]->length = 1; |
---|
| 1099 | TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP; |
---|
| 1100 | } |
---|
| 1101 | return 0; |
---|
| 1102 | } |
---|
| 1103 | |
---|
| 1104 | void |
---|
| 1105 | m8xx_uart_reserve_resources( |
---|
| 1106 | rtems_configuration_table *configuration |
---|
| 1107 | ) |
---|
| 1108 | { |
---|
| 1109 | rtems_termios_reserve_resources (configuration, NUM_PORTS); |
---|
| 1110 | } |
---|