[8ef3818] | 1 | /* clock.c |
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| 2 | * |
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| 3 | * This routine initializes the PIT on the MPC8xx. |
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| 4 | * The tick frequency is specified by the bsp. |
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| 5 | * |
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| 6 | * Author: Jay Monkman (jmonkman@frasca.com) |
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| 7 | * Copyright (C) 1998 by Frasca International, Inc. |
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| 8 | * |
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| 9 | * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: |
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| 10 | * |
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| 11 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 12 | * |
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| 13 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 14 | * |
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| 15 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 16 | * without any express or implied warranty: |
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| 17 | * permission to use, copy, modify, and distribute this file |
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| 18 | * for any purpose is hereby granted without fee, provided that |
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| 19 | * the above copyright notice and this notice appears in all |
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| 20 | * copies, and that the name of i-cubed limited not be used in |
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| 21 | * advertising or publicity pertaining to distribution of the |
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| 22 | * software without specific, written prior permission. |
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| 23 | * i-cubed limited makes no representations about the suitability |
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| 24 | * of this software for any purpose. |
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| 25 | * |
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| 26 | * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: |
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| 27 | * |
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| 28 | * COPYRIGHT (c) 1989-1998. |
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| 29 | * On-Line Applications Research Corporation (OAR). |
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| 30 | * Copyright assigned to U.S. Government, 1994. |
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| 31 | * |
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| 32 | * The license and distribution terms for this file may be |
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| 33 | * found in the file LICENSE in this distribution or at |
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| 34 | * http://www.OARcorp.com/rtems/license.html. |
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| 35 | * |
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| 36 | * $Id$ |
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| 37 | */ |
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| 38 | |
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| 39 | #include <bsp.h> |
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| 40 | #include <clockdrv.h> |
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| 41 | #include <rtems/libio.h> |
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| 42 | |
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| 43 | #include <stdlib.h> /* for atexit() */ |
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| 44 | #include <mpc8xx.h> |
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| 45 | |
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| 46 | extern rtems_cpu_table Cpu_table; /* owned by BSP */ |
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| 47 | |
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| 48 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 49 | extern volatile m8xx_t m8xx; |
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| 50 | |
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| 51 | void Clock_exit( void ); |
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| 52 | |
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| 53 | /* |
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| 54 | * These are set by clock driver during its init |
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| 55 | */ |
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| 56 | |
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| 57 | rtems_device_major_number rtems_clock_major = ~0; |
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| 58 | rtems_device_minor_number rtems_clock_minor; |
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| 59 | |
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| 60 | /* |
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| 61 | * ISR Handler |
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| 62 | */ |
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| 63 | rtems_isr Clock_isr(rtems_vector_number vector) |
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| 64 | { |
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| 65 | m8xx.piscr |= M8xx_PISCR_PS; |
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| 66 | Clock_driver_ticks++; |
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| 67 | rtems_clock_tick(); |
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| 68 | } |
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| 69 | |
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| 70 | void Install_clock(rtems_isr_entry clock_isr) |
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| 71 | { |
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| 72 | #ifdef EPPCBUG_SMC1 |
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| 73 | extern unsigned32 simask_copy; |
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| 74 | #endif /* EPPCBUG_SMC1 */ |
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| 75 | |
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| 76 | rtems_isr_entry previous_isr; |
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| 77 | rtems_unsigned32 pit_value; |
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| 78 | |
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| 79 | Clock_driver_ticks = 0; |
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| 80 | |
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| 81 | pit_value = (BSP_Configuration.microseconds_per_tick * |
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| 82 | Cpu_table.clicks_per_usec) - 1 ; |
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| 83 | |
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| 84 | if (pit_value > 0xffff) { /* pit is only 16 bits long */ |
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| 85 | rtems_fatal_error_occurred(-1); |
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| 86 | } |
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| 87 | if (BSP_Configuration.ticks_per_timeslice) { |
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| 88 | |
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| 89 | /* |
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| 90 | * initialize the interval here |
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| 91 | * First tick is set to right amount of time in the future |
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| 92 | * Future ticks will be incremented over last value set |
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| 93 | * in order to provide consistent clicks in the face of |
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| 94 | * interrupt overhead |
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| 95 | */ |
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| 96 | |
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| 97 | rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); |
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| 98 | |
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| 99 | m8xx.sccr &= ~(1<<24); |
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| 100 | m8xx.pitc = pit_value; |
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| 101 | |
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| 102 | /* set PIT irq level, enable PIT, PIT interrupts */ |
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| 103 | /* and clear int. status */ |
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| 104 | m8xx.piscr = M8xx_PISCR_PIRQ(0) | |
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| 105 | M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; |
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| 106 | |
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| 107 | #ifdef EPPCBUG_SMC1 |
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| 108 | simask_copy = m8xx.simask | M8xx_SIMASK_LVM0; |
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| 109 | #endif /* EPPCBUG_SMC1 */ |
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| 110 | m8xx.simask |= M8xx_SIMASK_LVM0; |
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| 111 | } |
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| 112 | atexit(Clock_exit); |
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| 113 | } |
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| 114 | |
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| 115 | void |
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| 116 | ReInstall_clock(rtems_isr_entry new_clock_isr) |
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| 117 | { |
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| 118 | rtems_isr_entry previous_isr; |
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| 119 | rtems_unsigned32 isrlevel = 0; |
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| 120 | |
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| 121 | rtems_interrupt_disable(isrlevel); |
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| 122 | |
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| 123 | rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr); |
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| 124 | |
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| 125 | rtems_interrupt_enable(isrlevel); |
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| 126 | } |
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| 127 | |
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| 128 | |
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| 129 | /* |
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| 130 | * Called via atexit() |
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| 131 | * Remove the clock interrupt handler by setting handler to NULL |
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| 132 | */ |
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| 133 | void |
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| 134 | Clock_exit(void) |
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| 135 | { |
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| 136 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 137 | /* disable PIT and PIT interrupts */ |
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| 138 | m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); |
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| 139 | |
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| 140 | (void) set_vector(0, PPC_IRQ_LVL0, 1); |
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| 141 | } |
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| 142 | } |
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| 143 | |
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| 144 | rtems_device_driver Clock_initialize( |
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| 145 | rtems_device_major_number major, |
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| 146 | rtems_device_minor_number minor, |
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| 147 | void *pargp |
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| 148 | ) |
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| 149 | { |
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| 150 | Install_clock( Clock_isr ); |
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| 151 | |
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| 152 | /* |
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| 153 | * make major/minor avail to others such as shared memory driver |
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| 154 | */ |
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| 155 | |
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| 156 | rtems_clock_major = major; |
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| 157 | rtems_clock_minor = minor; |
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| 158 | |
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| 159 | return RTEMS_SUCCESSFUL; |
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| 160 | } |
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| 161 | |
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| 162 | rtems_device_driver Clock_control( |
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| 163 | rtems_device_major_number major, |
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| 164 | rtems_device_minor_number minor, |
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| 165 | void *pargp |
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| 166 | ) |
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| 167 | { |
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| 168 | rtems_libio_ioctl_args_t *args = pargp; |
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| 169 | |
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| 170 | if (args == 0) |
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| 171 | goto done; |
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| 172 | |
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| 173 | /* |
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| 174 | * This is hokey, but until we get a defined interface |
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| 175 | * to do this, it will just be this simple... |
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| 176 | */ |
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| 177 | |
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| 178 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { |
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| 179 | Clock_isr(PPC_IRQ_LVL0); |
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| 180 | } |
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| 181 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { |
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| 182 | ReInstall_clock(args->buffer); |
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| 183 | } |
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| 184 | |
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| 185 | done: |
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| 186 | return RTEMS_SUCCESSFUL; |
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| 187 | } |
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| 188 | |
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