[8ef3818] | 1 | /* clock.c |
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| 2 | * |
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| 3 | * This routine initializes the PIT on the MPC8xx. |
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| 4 | * The tick frequency is specified by the bsp. |
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[780eab4] | 5 | */ |
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| 6 | |
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| 7 | /* |
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[8ef3818] | 8 | * Author: Jay Monkman (jmonkman@frasca.com) |
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| 9 | * Copyright (C) 1998 by Frasca International, Inc. |
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| 10 | * |
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| 11 | * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: |
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| 12 | * |
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| 13 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 14 | * |
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| 15 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 16 | * |
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| 17 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 18 | * without any express or implied warranty: |
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| 19 | * permission to use, copy, modify, and distribute this file |
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| 20 | * for any purpose is hereby granted without fee, provided that |
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| 21 | * the above copyright notice and this notice appears in all |
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| 22 | * copies, and that the name of i-cubed limited not be used in |
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| 23 | * advertising or publicity pertaining to distribution of the |
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| 24 | * software without specific, written prior permission. |
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| 25 | * i-cubed limited makes no representations about the suitability |
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| 26 | * of this software for any purpose. |
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| 27 | * |
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| 28 | * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: |
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| 29 | * |
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[c4cc8199] | 30 | * COPYRIGHT (c) 1989-2007. |
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[8ef3818] | 31 | * On-Line Applications Research Corporation (OAR). |
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| 32 | * |
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| 33 | * The license and distribution terms for this file may be |
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| 34 | * found in the file LICENSE in this distribution or at |
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[c499856] | 35 | * http://www.rtems.org/license/LICENSE. |
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[8ef3818] | 36 | */ |
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| 37 | |
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[61bd0301] | 38 | #include <rtems.h> |
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[11c2382] | 39 | #include <rtems/clockdrv.h> |
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[8ef3818] | 40 | #include <rtems/libio.h> |
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[e1df032] | 41 | #include <rtems/powerpc/powerpc.h> |
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[8ef3818] | 42 | |
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| 43 | #include <stdlib.h> /* for atexit() */ |
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| 44 | #include <mpc8xx.h> |
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[3507f3f9] | 45 | #include <bsp.h> |
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[8ef3818] | 46 | |
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[66c373bf] | 47 | volatile uint32_t Clock_driver_ticks; |
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[8ef3818] | 48 | extern volatile m8xx_t m8xx; |
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[c8bcff57] | 49 | extern int BSP_get_clock_irq_level(void); |
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[d1dde59] | 50 | extern uint32_t bsp_clicks_per_usec; |
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[8ef3818] | 51 | |
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| 52 | /* |
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[780eab4] | 53 | * Prototypes |
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[8ef3818] | 54 | */ |
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[780eab4] | 55 | rtems_isr Clock_isr(rtems_vector_number vector); |
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| 56 | void Clock_exit( void ); |
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| 57 | void clockOn(void* unused); |
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| 58 | void clockOff(void* unused); |
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| 59 | int clockIsOn(void* unused); |
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| 60 | void Install_clock(rtems_isr_entry clock_isr); |
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| 61 | void ReInstall_clock(rtems_isr_entry new_clock_isr); |
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[359e537] | 62 | |
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[8ef3818] | 63 | /* |
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| 64 | * ISR Handler |
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| 65 | */ |
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| 66 | rtems_isr Clock_isr(rtems_vector_number vector) |
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| 67 | { |
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| 68 | m8xx.piscr |= M8xx_PISCR_PS; |
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| 69 | Clock_driver_ticks++; |
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| 70 | rtems_clock_tick(); |
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| 71 | } |
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| 72 | |
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[37731c2b] | 73 | void clockOn(void* unused) |
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[8ef3818] | 74 | { |
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[37731c2b] | 75 | unsigned desiredLevel; |
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[66c373bf] | 76 | uint32_t pit_value; |
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[663e5293] | 77 | uint32_t extclk; |
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[9a73f421] | 78 | bool force_prescaler = false; |
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[663e5293] | 79 | uint32_t immr_val; |
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[c4cc8199] | 80 | |
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| 81 | if (bsp_clicks_per_usec == 0) { |
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[0130f653] | 82 | /* |
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| 83 | * oscclk is too low for PIT, compute extclk and derive PIT from there |
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| 84 | */ |
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[663e5293] | 85 | /* |
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| 86 | * determine external input clock by examining the PLL settings |
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| 87 | * this must be done differently depending on type of PLL |
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| 88 | */ |
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| 89 | _mfspr(immr_val,M8xx_IMMR); |
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| 90 | if (8 == ((immr_val & 0x0000FF00) >> 8)) { |
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| 91 | /* |
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| 92 | * for MPC866: complex PLL |
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| 93 | */ |
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| 94 | uint32_t plprcr_val; |
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| 95 | uint32_t mfn_value; |
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| 96 | uint32_t mfd_value; |
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| 97 | uint32_t mfi_value; |
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| 98 | uint32_t pdf_value; |
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| 99 | uint32_t s_value; |
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| 100 | |
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| 101 | plprcr_val = m8xx.plprcr; |
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| 102 | mfn_value = (plprcr_val & (0xf8000000)) >> (31- 4); |
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| 103 | mfd_value = (plprcr_val & (0x07c00000)) >> (31- 9); |
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| 104 | s_value = (plprcr_val & (0x00300000)) >> (31-11); |
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| 105 | mfi_value = (plprcr_val & (0x000f0000)) >> (31-15); |
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| 106 | pdf_value = (plprcr_val & (0x00000006)) >> (31-30); |
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[359e537] | 107 | extclk = (((uint64_t)bsp_clock_speed) |
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[780eab4] | 108 | * ((pdf_value + 1) * (mfd_value + 1)) |
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| 109 | / (mfi_value * (mfd_value + 1) + mfn_value) |
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| 110 | * (1 << s_value)); |
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[663e5293] | 111 | } |
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| 112 | else { |
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| 113 | /* |
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| 114 | * for MPC860/850 etc: simple PLL |
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| 115 | */ |
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| 116 | uint32_t mf_value; |
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| 117 | mf_value = m8xx.plprcr >> 20; |
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| 118 | extclk = bsp_clock_speed / (mf_value+1); |
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| 119 | } |
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| 120 | pit_value = (extclk |
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[780eab4] | 121 | / 1000 |
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| 122 | / 4 |
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| 123 | * rtems_configuration_get_microseconds_per_tick() |
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| 124 | / 1000); |
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[0130f653] | 125 | m8xx.sccr |= (1<<23); |
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[9a73f421] | 126 | force_prescaler = true; |
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[0130f653] | 127 | } |
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| 128 | else { |
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| 129 | pit_value = (rtems_configuration_get_microseconds_per_tick() * |
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[780eab4] | 130 | bsp_clicks_per_usec); |
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[359e537] | 131 | |
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[0130f653] | 132 | m8xx.sccr &= ~(1<<23); |
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| 133 | } |
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[780eab4] | 134 | |
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| 135 | if ((pit_value > 0xffff) || force_prescaler) { |
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[0130f653] | 136 | /* |
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| 137 | * try to activate prescaler |
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| 138 | * NOTE: divider generates odd values now... |
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| 139 | */ |
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| 140 | pit_value = pit_value / 128; |
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| 141 | m8xx.sccr |= (1<<24); |
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| 142 | } |
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| 143 | else { |
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| 144 | m8xx.sccr &= ~(1<<24); |
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| 145 | } |
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| 146 | |
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[8ef3818] | 147 | if (pit_value > 0xffff) { /* pit is only 16 bits long */ |
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| 148 | rtems_fatal_error_occurred(-1); |
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[37731c2b] | 149 | } |
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[0130f653] | 150 | m8xx.pitc = pit_value - 1; |
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[37731c2b] | 151 | |
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| 152 | desiredLevel = BSP_get_clock_irq_level(); |
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[61bd0301] | 153 | /* set PIT irq level, enable PIT, PIT interrupts */ |
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| 154 | /* and clear int. status */ |
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[37731c2b] | 155 | m8xx.piscr = M8xx_PISCR_PIRQ(desiredLevel) | |
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| 156 | M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; |
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[8ef3818] | 157 | } |
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[780eab4] | 158 | |
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[37731c2b] | 159 | /* |
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| 160 | * Called via atexit() |
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| 161 | * Remove the clock interrupt handler by setting handler to NULL |
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| 162 | */ |
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[780eab4] | 163 | void clockOff(void* unused) |
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[8ef3818] | 164 | { |
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[37731c2b] | 165 | /* disable PIT and PIT interrupts */ |
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[359e537] | 166 | m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); |
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[8ef3818] | 167 | } |
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| 168 | |
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[37731c2b] | 169 | int clockIsOn(void* unused) |
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| 170 | { |
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[780eab4] | 171 | if (m8xx.piscr & M8xx_PISCR_PIE) |
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| 172 | return 1; |
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[37731c2b] | 173 | return 0; |
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| 174 | } |
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[8ef3818] | 175 | |
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| 176 | /* |
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| 177 | * Called via atexit() |
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| 178 | * Remove the clock interrupt handler by setting handler to NULL |
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| 179 | */ |
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[780eab4] | 180 | void Clock_exit(void) |
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[8ef3818] | 181 | { |
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[37731c2b] | 182 | (void) BSP_disconnect_clock_handler (); |
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[8ef3818] | 183 | } |
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| 184 | |
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[37731c2b] | 185 | void Install_clock(rtems_isr_entry clock_isr) |
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| 186 | { |
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| 187 | Clock_driver_ticks = 0; |
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| 188 | |
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| 189 | BSP_connect_clock_handler (clock_isr); |
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| 190 | atexit(Clock_exit); |
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| 191 | } |
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| 192 | |
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[780eab4] | 193 | void ReInstall_clock(rtems_isr_entry new_clock_isr) |
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[37731c2b] | 194 | { |
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| 195 | BSP_connect_clock_handler (new_clock_isr); |
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| 196 | } |
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| 197 | |
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[8ef3818] | 198 | rtems_device_driver Clock_initialize( |
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| 199 | rtems_device_major_number major, |
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| 200 | rtems_device_minor_number minor, |
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| 201 | void *pargp |
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| 202 | ) |
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| 203 | { |
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| 204 | Install_clock( Clock_isr ); |
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[359e537] | 205 | |
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[8ef3818] | 206 | return RTEMS_SUCCESSFUL; |
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| 207 | } |
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