source: rtems/c/src/lib/libcpu/powerpc/mpc860/include/mpc860.h @ fbe75c6e

4.104.114.84.95
Last change on this file since fbe75c6e was fbe75c6e, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 1999 at 6:17:33 PM

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

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1/*
2**************************************************************************
3**************************************************************************
4**                                                                      **
5**  MOTOROLA MPC860 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER     **
6**                             POWERQUICC                               **
7**                                                                      **
8**                        HARDWARE DECLARATIONS                         **
9**                                                                      **
10**                                                                      **
11**  Submitted By:                                                       **
12**                                                                      **
13**      W. Eric Norum                                                   **
14**      Saskatchewan Accelerator Laboratory                             **
15**      University of Saskatchewan                                      **
16**      107 North Road                                                  **
17**      Saskatoon, Saskatchewan, CANADA                                 **
18**      S7N 5C6                                                         **
19**                                                                      **
20**      eric@skatter.usask.ca                                           **
21**                                                                      **
22**  Modified for use with the MPC860 (original code was for MC68360)    **
23**  by                                                                  **
24**      Jay Monkman                                                     **
25**      Frasca International, Inc.                                      **
26**      906 E. Airport Rd.                                              **
27**      Urbana, IL, 61801                                               **
28**                                                                      **
29**      jmonkman@frasca.com                                             **
30**                                                                      **
31**************************************************************************
32**************************************************************************
33*/
34
35#ifndef __MPC860_h
36#define __MPC860_h
37
38#ifndef ASM
39/*
40  Macros for SPRs
41*/
42
43#define M860_MI_CTR_GPM       (1<<31)
44#define M860_MI_CTR_PPM       (1<<30)
45#define M860_MI_CTR_CIDEF     (1<<29)
46#define M860_MI_CTR_RSV4I     (1<<27)
47#define M860_MI_CTR_PPCS      (1<<25)
48
49#define M860_MD_CTR_GPM       (1<<31)
50#define M860_MD_CTR_PPM       (1<<30)
51#define M860_MD_CTR_CIDEF     (1<<29)
52#define M860_MD_CTR_WTDEF     (1<<28)
53#define M860_MD_CTR_RSV4D     (1<<27)
54#define M860_MD_CTR_TWAM      (1<<26)
55#define M860_MD_CTR_PPCS      (1<<25)
56
57#define M860_MI_EPN_VALID     (1<<9)
58
59#define M860_MD_EPN_VALID     (1<<9)
60
61#define M860_MI_TWC_G         (1<<4)
62#define M860_MI_TWC_PSS       (0<<2)
63#define M860_MI_TWC_PS512     (1<<2)
64#define M860_MI_TWC_PS8       (3<<2)
65#define M860_MI_TWC_VALID     (1)
66
67#define M860_MD_TWC_G         (1<<4)
68#define M860_MD_TWC_PSS       (0<<2)
69#define M860_MD_TWC_PS512     (1<<2)
70#define M860_MD_TWC_PS8       (3<<2)
71#define M860_MD_TWC_WT        (1<<1)
72#define M860_MD_TWC_VALID     (1)
73
74#define M860_MI_RPN_F         (0xf<<4)
75#define M860_MI_RPN_16K       (1<<3)
76#define M860_MI_RPN_SHARED    (1<<2)
77#define M860_MI_RPN_CI        (1<<1)
78#define M860_MI_RPN_VALID     (1)
79
80#define M860_MD_RPN_CHANGE    (1<<8)
81#define M860_MD_RPN_F         (0xf<<4)
82#define M860_MD_RPN_16K       (1<<3)
83#define M860_MD_RPN_SHARED    (1<<2)
84#define M860_MD_RPN_CI        (1<<1)
85#define M860_MD_RPN_VALID     (1)
86
87#define M860_MI_AP_Kp         (1)
88
89#define M860_MD_AP_Kp         (1)
90
91#define M860_CACHE_CMD_SFWT          (0x1<<24)
92#define M860_CACHE_CMD_ENABLE        (0x2<<24)
93#define M860_CACHE_CMD_CFWT          (0x3<<24)
94#define M860_CACHE_CMD_DISABLE       (0x4<<24)
95#define M860_CACHE_CMD_STLES         (0x5<<24)
96#define M860_CACHE_CMD_LLCB          (0x6<<24)
97#define M860_CACHE_CMD_CLES          (0x7<<24)
98#define M860_CACHE_CMD_UNLOCK        (0x8<<24)
99#define M860_CACHE_CMD_UNLOCKALL     (0xa<<24)
100#define M860_CACHE_CMD_INVALIDATE    (0xc<<24)
101#define M860_CACHE_CMD_FLUSH         (0xe<<24)
102
103
104
105/*
106*************************************************************************
107*                         REGISTER SUBBLOCKS                            *
108*************************************************************************
109*/
110
111/*
112 * Memory controller registers
113 */
114typedef struct m860MEMCRegisters_ {
115  rtems_unsigned32        br;
116  rtems_unsigned32        or;
117} m860MEMCRegisters_t;
118
119/*
120 * Serial Communications Controller registers
121 */
122typedef struct m860SCCRegisters_ {
123  rtems_unsigned32        gsmr_l;
124  rtems_unsigned32        gsmr_h;
125  rtems_unsigned16        psmr;
126  rtems_unsigned16        _pad0;
127  rtems_unsigned16        todr;
128  rtems_unsigned16        dsr;
129  rtems_unsigned16        scce;
130  rtems_unsigned16        _pad1;
131  rtems_unsigned16        sccm;
132  rtems_unsigned8         _pad2;
133  rtems_unsigned8         sccs;
134  rtems_unsigned32        _pad3[2];
135} m860SCCRegisters_t;
136
137/*
138 * Serial Management Controller registers
139 */
140typedef struct m860SMCRegisters_ {
141  rtems_unsigned16        _pad0;
142  rtems_unsigned16        smcmr;
143  rtems_unsigned16        _pad1;
144  rtems_unsigned8         smce;
145  rtems_unsigned8         _pad2;
146  rtems_unsigned16        _pad3;
147  rtems_unsigned8         smcm;
148  rtems_unsigned8         _pad4;
149  rtems_unsigned32        _pad5;
150} m860SMCRegisters_t;
151
152/*
153 * Fast Ethernet Controller registers (Only on MPC860T)
154 */
155typedef struct m860FECRegisters_ {
156  rtems_unsigned32    addr_low;
157  rtems_unsigned32    addr_high;
158  rtems_unsigned32    hash_table_high;
159  rtems_unsigned32    hash_table_low;
160  rtems_unsigned32    r_des_start;
161  rtems_unsigned32    x_des_start;
162  rtems_unsigned32    r_buf_size;
163  rtems_unsigned32    _pad0[9];
164  rtems_unsigned32    ecntrl;
165  rtems_unsigned32    ievent;
166  rtems_unsigned32    imask;
167  rtems_unsigned32    ivec;
168  rtems_unsigned32    r_des_active;
169  rtems_unsigned32    x_des_active;
170  rtems_unsigned32    _pad1[10];
171  rtems_unsigned32    mii_data;
172  rtems_unsigned32    mii_speed;
173  rtems_unsigned32    _pad2[17];
174  rtems_unsigned32    r_bound;
175  rtems_unsigned32    r_fstart;
176  rtems_unsigned32    _pad3[6];
177  rtems_unsigned32    x_fstart;
178  rtems_unsigned32    _pad4[17];
179  rtems_unsigned32    fun_code;
180  rtems_unsigned32    _pad5[3];
181  rtems_unsigned32    r_cntrl;
182  rtems_unsigned32    r_hash;
183  rtems_unsigned32    _pad6[14];
184  rtems_unsigned32    x_cntrl;
185  rtems_unsigned32    _pad7[30];
186
187} m860FECRegisters_t;
188
189#define M860_FEC_IEVENT_HBERR  (1 << 31)
190#define M860_FEC_IEVENT_BABR   (1 << 30)
191#define M860_FEC_IEVENT_BABT   (1 << 29)
192#define M860_FEC_IEVENT_GRA    (1 << 28)
193#define M860_FEC_IEVENT_TFINT  (1 << 27)
194#define M860_FEC_IEVENT_TXB    (1 << 26)
195#define M860_FEC_IEVENT_RFINT  (1 << 25)
196#define M860_FEC_IEVENT_RXB    (1 << 24)
197#define M860_FEC_IEVENT_MII    (1 << 23)
198#define M860_FEC_IEVENT_EBERR  (1 << 22)
199#define M860_FEC_IMASK_HBEEN   (1 << 31)
200#define M860_FEC_IMASK_BREEN   (1 << 30)
201#define M860_FEC_IMASK_BTEN    (1 << 29)
202#define M860_FEC_IMASK_GRAEN   (1 << 28)
203#define M860_FEC_IMASK_TFIEN   (1 << 27)
204#define M860_FEC_IMASK_TBIEN   (1 << 26)
205#define M860_FEC_IMASK_RFIEN   (1 << 25)
206#define M860_FEC_IMASK_RBIEN   (1 << 24)
207#define M860_FEC_IMASK_MIIEN   (1 << 23)
208#define M860_FEC_IMASK_EBERREN (1 << 22)
209
210
211/*
212*************************************************************************
213*                         Miscellaneous Parameters                      *
214*************************************************************************
215*/
216typedef struct m860MiscParms_ {
217  rtems_unsigned16        rev_num;
218  rtems_unsigned16        _res1;
219  rtems_unsigned32        _res2;
220  rtems_unsigned32        _res3;
221} m860MiscParms_t;
222
223/*
224*************************************************************************
225*                              RISC Timers                              *
226*************************************************************************
227*/
228typedef struct m860TimerParms_ {
229  rtems_unsigned16        tm_base;
230  rtems_unsigned16        _tm_ptr;
231  rtems_unsigned16        _r_tmr;
232  rtems_unsigned16        _r_tmv;
233  rtems_unsigned32        tm_cmd;
234  rtems_unsigned32        tm_cnt;
235} m860TimerParms_t;
236
237/*
238 * RISC Controller Configuration Register (RCCR)
239 * All other bits in this register are reserved.
240 */
241#define M860_RCCR_TIME          (1<<15)    /* Enable timer */
242#define M860_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
243#define M860_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
244#define M860_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
245#define M860_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
246#define M860_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
247#define M860_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
248#define M860_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */
249
250/*
251 * Command register
252 * Set up this register before issuing a M860_CR_OP_SET_TIMER command.
253 */
254#define M860_TM_CMD_V           (1<<31)         /* Set to enable timer */
255#define M860_TM_CMD_R           (1<<30)         /* Set for automatic restart */
256#define M860_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
257#define M860_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
258#define M860_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
259
260/*
261*************************************************************************
262*                               DMA Controllers                         *
263*************************************************************************
264*/
265typedef struct m860IDMAparms_ {
266  rtems_unsigned16        ibase;
267  rtems_unsigned16        dcmr;
268  rtems_unsigned32        _sapr;
269  rtems_unsigned32        _dapr;
270  rtems_unsigned16        ibptr;
271  rtems_unsigned16        _write_sp;
272  rtems_unsigned32        _s_byte_c;
273  rtems_unsigned32        _d_byte_c;
274  rtems_unsigned32        _s_state;
275  rtems_unsigned32        _itemp[4];
276  rtems_unsigned32        _sr_mem;
277  rtems_unsigned16        _read_sp;
278  rtems_unsigned16        _res0;
279  rtems_unsigned16        _res1;
280  rtems_unsigned16        _res2;
281  rtems_unsigned32        _d_state;
282} m860IDMAparms_t;
283
284
285/*
286*************************************************************************
287*                               DSP                                     *
288*************************************************************************
289*/
290typedef struct m860DSPparms_ {
291  rtems_unsigned32        fdbase;
292  rtems_unsigned32        _fd_ptr;
293  rtems_unsigned32        _dstate;
294  rtems_unsigned32        _pad0;
295  rtems_unsigned16        _dstatus;
296  rtems_unsigned16        _i;
297  rtems_unsigned16        _tap;
298  rtems_unsigned16        _cbase;
299  rtems_unsigned16        _pad1;
300  rtems_unsigned16        _xptr;
301  rtems_unsigned16        _pad2;
302  rtems_unsigned16        _yptr;
303  rtems_unsigned16        _m;
304  rtems_unsigned16        _pad3;
305  rtems_unsigned16        _n;
306  rtems_unsigned16        _pad4;
307  rtems_unsigned16        _k;
308  rtems_unsigned16        _pad5;
309} m860DSPparms_t;
310
311/*
312*************************************************************************
313*                   Serial Communication Controllers                    *
314*************************************************************************
315*/
316typedef struct m860SCCparms_ {
317  rtems_unsigned16        rbase;
318  rtems_unsigned16        tbase;
319  rtems_unsigned8         rfcr;
320  rtems_unsigned8         tfcr;
321  rtems_unsigned16        mrblr;
322  rtems_unsigned32        _rstate;
323  rtems_unsigned32        _pad0;
324  rtems_unsigned16        _rbptr;
325  rtems_unsigned16        _pad1;
326  rtems_unsigned32        _pad2;
327  rtems_unsigned32        _tstate;
328  rtems_unsigned32        _pad3;
329  rtems_unsigned16        _tbptr;
330  rtems_unsigned16        _pad4;
331  rtems_unsigned32        _pad5;
332  rtems_unsigned32        _rcrc;
333  rtems_unsigned32        _tcrc;
334  union {
335    struct {
336      rtems_unsigned32        _res0;
337      rtems_unsigned32        _res1;
338      rtems_unsigned16        max_idl;
339      rtems_unsigned16        _idlc;
340      rtems_unsigned16        brkcr;
341      rtems_unsigned16        parec;
342      rtems_unsigned16        frmec;
343      rtems_unsigned16        nosec;
344      rtems_unsigned16        brkec;
345      rtems_unsigned16        brklen;
346      rtems_unsigned16        uaddr[2];
347      rtems_unsigned16        _rtemp;
348      rtems_unsigned16        toseq;
349      rtems_unsigned16        character[8];
350      rtems_unsigned16        rccm;
351      rtems_unsigned16        rccr;
352      rtems_unsigned16        rlbc;
353    } uart;
354  } un;
355} m860SCCparms_t;
356
357typedef struct m860SCCENparms_ {
358  rtems_unsigned16        rbase;
359  rtems_unsigned16        tbase;
360  rtems_unsigned8         rfcr;
361  rtems_unsigned8         tfcr;
362  rtems_unsigned16        mrblr;
363  rtems_unsigned32        _rstate;
364  rtems_unsigned32        _pad0;
365  rtems_unsigned16        _rbptr;
366  rtems_unsigned16        _pad1;
367  rtems_unsigned32        _pad2;
368  rtems_unsigned32        _tstate;
369  rtems_unsigned32        _pad3;
370  rtems_unsigned16        _tbptr;
371  rtems_unsigned16        _pad4;
372  rtems_unsigned32        _pad5;
373  rtems_unsigned32        _rcrc;
374  rtems_unsigned32        _tcrc;
375  union {
376    struct {
377      rtems_unsigned32        _res0;
378      rtems_unsigned32        _res1;
379      rtems_unsigned16        max_idl;
380      rtems_unsigned16        _idlc;
381      rtems_unsigned16        brkcr;
382      rtems_unsigned16        parec;
383      rtems_unsigned16        frmec;
384      rtems_unsigned16        nosec;
385      rtems_unsigned16        brkec;
386      rtems_unsigned16        brklen;
387      rtems_unsigned16        uaddr[2];
388      rtems_unsigned16        _rtemp;
389      rtems_unsigned16        toseq;
390      rtems_unsigned16        character[8];
391      rtems_unsigned16        rccm;
392      rtems_unsigned16        rccr;
393      rtems_unsigned16        rlbc;
394    } uart;
395    struct {
396      rtems_unsigned32        c_pres;
397      rtems_unsigned32        c_mask;
398      rtems_unsigned32        crcec;
399      rtems_unsigned32        alec;
400      rtems_unsigned32        disfc;
401      rtems_unsigned16        pads;
402      rtems_unsigned16        ret_lim;
403      rtems_unsigned16        _ret_cnt;
404      rtems_unsigned16        mflr;
405      rtems_unsigned16        minflr;
406      rtems_unsigned16        maxd1;
407      rtems_unsigned16        maxd2;
408      rtems_unsigned16        _maxd;
409      rtems_unsigned16        dma_cnt;
410      rtems_unsigned16        _max_b;
411      rtems_unsigned16        gaddr1;
412      rtems_unsigned16        gaddr2;
413      rtems_unsigned16        gaddr3;
414      rtems_unsigned16        gaddr4;
415      rtems_unsigned32        _tbuf0data0;
416      rtems_unsigned32        _tbuf0data1;
417      rtems_unsigned32        _tbuf0rba0;
418      rtems_unsigned32        _tbuf0crc;
419      rtems_unsigned16        _tbuf0bcnt;
420      rtems_unsigned16        paddr_h;
421      rtems_unsigned16        paddr_m;
422      rtems_unsigned16        paddr_l;
423      rtems_unsigned16        p_per;
424      rtems_unsigned16        _rfbd_ptr;
425      rtems_unsigned16        _tfbd_ptr;
426      rtems_unsigned16        _tlbd_ptr;
427      rtems_unsigned32        _tbuf1data0;
428      rtems_unsigned32        _tbuf1data1;
429      rtems_unsigned32        _tbuf1rba0;
430      rtems_unsigned32        _tbuf1crc;
431      rtems_unsigned16        _tbuf1bcnt;
432      rtems_unsigned16        _tx_len;
433      rtems_unsigned16        iaddr1;
434      rtems_unsigned16        iaddr2;
435      rtems_unsigned16        iaddr3;
436      rtems_unsigned16        iaddr4;
437      rtems_unsigned16        _boff_cnt;
438      rtems_unsigned16        taddr_l;
439      rtems_unsigned16        taddr_m;
440      rtems_unsigned16        taddr_h;
441    } ethernet;
442  } un;
443} m860SCCENparms_t;
444
445/*
446 * Receive and transmit function code register bits
447 * These apply to the function code registers of all devices, not just SCC.
448 */
449#define M860_RFCR_BO(x)         ((x)<<3)
450#define M860_RFCR_MOT           (2<<3)
451#define M860_RFCR_DMA_SPACE(x)  (x)
452#define M860_TFCR_BO(x)         ((x)<<3)
453#define M860_TFCR_MOT           (2<<3)
454#define M860_TFCR_DMA_SPACE(x)  (x)
455
456/*
457*************************************************************************
458*                     Serial Management Controllers                     *
459*************************************************************************
460*/
461typedef struct m860SMCparms_ {
462  rtems_unsigned16        rbase;
463  rtems_unsigned16        tbase;
464  rtems_unsigned8         rfcr;
465  rtems_unsigned8         tfcr;
466  rtems_unsigned16        mrblr;
467  rtems_unsigned32        _rstate;
468  rtems_unsigned32        _pad0;
469  rtems_unsigned16        _rbptr;
470  rtems_unsigned16        _pad1;
471  rtems_unsigned32        _pad2;
472  rtems_unsigned32        _tstate;
473  rtems_unsigned32        _pad3;
474  rtems_unsigned16        _tbptr;
475  rtems_unsigned16        _pad4;
476  rtems_unsigned32        _pad5;
477  union {
478    struct {
479      rtems_unsigned16        max_idl;
480      rtems_unsigned16        _idlc;
481      rtems_unsigned16        brklen;
482      rtems_unsigned16        brkec;
483      rtems_unsigned16        brkcr;
484      rtems_unsigned16        _r_mask;
485    } uart;
486    struct {
487      rtems_unsigned16        _pad0[5];
488    } transparent;
489  } un;
490} m860SMCparms_t;
491
492/*
493 * Mode register
494 */
495#define M860_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
496#define M860_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
497#define M860_SMCMR_PARITY               (1<<9)       /* Enable parity */
498#define M860_SMCMR_EVEN                 (1<<8)       /* Even parity */
499#define M860_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
500#define M860_SMCMR_SM_UART              (2<<4)       /* UART Mode */
501#define M860_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
502#define M860_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
503#define M860_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
504#define M860_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
505#define M860_SMCMR_REN                  (1<<0)       /* Enable receiver */
506
507/*
508 * Event and mask registers (SMCE, SMCM)
509 */
510#define M860_SMCE_BRKE  (1<<6)
511#define M860_SMCE_BRK   (1<<4)
512#define M860_SMCE_BSY   (1<<2)
513#define M860_SMCE_TX    (1<<1)
514#define M860_SMCE_RX    (1<<0)
515
516/*
517*************************************************************************
518*                      Serial Peripheral Interface                      *
519*************************************************************************
520*/
521typedef struct m860SPIparms_ {
522  rtems_unsigned16        rbase;
523  rtems_unsigned16        tbase;
524  rtems_unsigned8         rfcr;
525  rtems_unsigned8         tfcr;
526  rtems_unsigned16        mrblr;
527  rtems_unsigned32        _rstate;
528  rtems_unsigned32        _pad0;
529  rtems_unsigned16        _rbptr;
530  rtems_unsigned16        _pad1;
531  rtems_unsigned32        _pad2;
532  rtems_unsigned32        _tstate;
533  rtems_unsigned32        _pad3;
534  rtems_unsigned16        _tbptr;
535  rtems_unsigned16        _pad4;
536  rtems_unsigned32        _pad5;
537} m860SPIparms_t;
538
539/*
540 * Mode register (SPMODE)
541 */
542#define M860_SPMODE_LOOP                (1<<14) /* Local loopback mode */
543#define M860_SPMODE_CI                  (1<<13) /* Clock invert */
544#define M860_SPMODE_CP                  (1<<12) /* Clock phase */
545#define M860_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
546#define M860_SPMODE_REV                 (1<<10) /* Reverse data */
547#define M860_SPMODE_MASTER              (1<<9)  /* SPI is master */
548#define M860_SPMODE_EN                  (1<<8)  /* Enable SPI */
549#define M860_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
550#define M860_SPMODE_PM(x)               (x)     /* Prescaler modulus */
551
552/*
553 * Mode register (SPCOM)
554 */
555#define M860_SPCOM_STR                  (1<<7)  /* Start transmit */
556
557/*
558 * Event and mask registers (SPIE, SPIM)
559 */
560#define M860_SPIE_MME   (1<<5)          /* Multi-master error */
561#define M860_SPIE_TXE   (1<<4)          /* Tx error */
562#define M860_SPIE_BSY   (1<<2)          /* Busy condition*/
563#define M860_SPIE_TXB   (1<<1)          /* Tx buffer */
564#define M860_SPIE_RXB   (1<<0)          /* Rx buffer */
565
566/*
567*************************************************************************
568*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
569*************************************************************************
570*/
571typedef struct m860BufferDescriptor_ {
572  rtems_unsigned16        status;
573  rtems_unsigned16        length;
574  volatile void           *buffer;
575} m860BufferDescriptor_t;
576
577/*
578 * Bits in receive buffer descriptor status word
579 */
580#define M860_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
581#define M860_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
582#define M860_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
583#define M860_BD_LAST            (1<<11) /* Ethernet, SPI */
584#define M860_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
585#define M860_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
586#define M860_BD_ADDRESS         (1<<10) /* SCC UART */
587#define M860_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
588#define M860_BD_MISS            (1<<8)  /* Ethernet */
589#define M860_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
590#define M860_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
591#define M860_BD_LONG            (1<<5)  /* Ethernet */
592#define M860_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
593#define M860_BD_NONALIGNED      (1<<4)  /* Ethernet */
594#define M860_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
595#define M860_BD_SHORT           (1<<3)  /* Ethernet */
596#define M860_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
597#define M860_BD_CRC_ERROR       (1<<2)  /* Ethernet */
598#define M860_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
599#define M860_BD_COLLISION       (1<<0)  /* Ethernet */
600#define M860_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
601#define M860_BD_MASTER_ERROR    (1<<0)  /* SPI */
602
603/*
604 * Bits in transmit buffer descriptor status word
605 * Many bits have the same meaning as those in receiver buffer descriptors.
606 */
607#define M860_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
608#define M860_BD_PAD             (1<<14) /* Ethernet */
609#define M860_BD_CTS_REPORT      (1<<11) /* SCC UART */
610#define M860_BD_TX_CRC          (1<<10) /* Ethernet */
611#define M860_BD_DEFER           (1<<9)  /* Ethernet */
612#define M860_BD_HEARTBEAT       (1<<8)  /* Ethernet */
613#define M860_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
614#define M860_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
615#define M860_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
616#define M860_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
617#define M860_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
618#define M860_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
619#define M860_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
620#define M860_BD_CTS_LOST        (1<<0)  /* SCC UART */
621
622/*
623*************************************************************************
624*                           IDMA Buffer Descriptors                     *
625*************************************************************************
626*/
627typedef struct m860IDMABufferDescriptor_ {
628  rtems_unsigned16        status;
629  rtems_unsigned8         dfcr;       
630  rtems_unsigned8         sfcr;       
631  rtems_unsigned32        length;
632  void                    *source;
633  void                    *destination;
634} m860IDMABufferDescriptor_t;
635
636/*
637*************************************************************************
638*       RISC Communication Processor Module Command Register (CR)       *
639*************************************************************************
640*/
641#define M860_CR_RST             (1<<15) /* Reset communication processor */
642#define M860_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
643#define M860_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
644#define M860_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
645#define M860_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
646#define M860_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
647#define M860_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
648#define M860_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
649#define M860_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
650#define M860_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
651#define M860_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
652#define M860_CR_OP_SET_TIMER    (8<<8)  /* Timer */
653#define M860_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
654#define M860_CR_OP_RESERT_BCS   (10<<8) /* SCC */
655#define M860_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
656#define M860_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
657#define M860_CR_OP_START_DSP    (12<<8) /* DSP */
658#define M860_CR_OP_INIT_DSP     (13<<8) /* DSP */
659
660#define M860_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
661#define M860_CR_CHAN_I2C        (1<<4)
662#define M860_CR_CHAN_IDMA1      (1<<4)
663#define M860_CR_CHAN_SCC2       (4<<4)
664#define M860_CR_CHAN_SPI        (5<<4)
665#define M860_CR_CHAN_IDMA2      (5<<4)
666#define M860_CR_CHAN_TIMER      (5<<4)
667#define M860_CR_CHAN_SCC3       (8<<4)
668#define M860_CR_CHAN_SMC1       (9<<4)
669#define M860_CR_CHAN_DSP1       (9<<4)
670#define M860_CR_CHAN_SCC4       (12<<4)
671#define M860_CR_CHAN_SMC2       (13<<4)
672#define M860_CR_CHAN_DSP2       (13<<4)
673#define M860_CR_FLG             (1<<0)  /* Command flag */
674
675/*
676*************************************************************************
677*                 System Protection Control Register (SYPCR)            *
678*************************************************************************
679*/
680#define M860_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
681#define M860_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
682#define M860_SYPCR_BME          (1<<7)      /* Bus monitor enable */
683#define M860_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
684#define M860_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
685#define M860_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
686#define M860_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
687
688/*
689*************************************************************************
690*                        Memory Control Registers                       *
691*************************************************************************
692*/
693#define M860_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
694#define M860_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
695#define M860_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
696#define M860_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
697#define M860_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
698#define M860_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
699#define M860_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
700#define M860_MSR_WPER           (1<<7)  /* Write protection error */
701#define M860_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
702#define M860_BR_BA(x)           ((x)&0xffff8000) /* Base address */
703#define M860_BR_AT(x)           ((x)<<12) /* Address type */
704#define M860_BR_PS8             (1<<10)  /* 8 bit port */
705#define M860_BR_PS16            (2<<10)  /* 16 bit port */
706#define M860_BR_PS32            (0<<10)  /* 32 bit port */
707#define M860_BR_PARE            (1<<9)   /* Parity checking enable */
708#define M860_BR_WP              (1<<8)   /* Write protect */
709#define M860_BR_MS_GPCM         (0<<6)   /* GPCM */
710#define M860_BR_MS_UPMA         (2<<6)   /* UPM A */
711#define M860_BR_MS_UPMB         (3<<6)   /* UPM B */
712#define M860_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */
713
714#define M860_MEMC_OR_32K        0xffff8000      /* Address range */
715#define M860_MEMC_OR_64K        0xffff0000
716#define M860_MEMC_OR_128K       0xfffe0000
717#define M860_MEMC_OR_256K       0xfffc0000
718#define M860_MEMC_OR_512K       0xfff80000
719#define M860_MEMC_OR_1M         0xfff00000
720#define M860_MEMC_OR_2M         0xffe00000
721#define M860_MEMC_OR_4M         0xffc00000
722#define M860_MEMC_OR_8M         0xff800000
723#define M860_MEMC_OR_16M        0xff000000
724#define M860_MEMC_OR_32M        0xfe000000
725#define M860_MEMC_OR_64M        0xfc000000
726#define M860_MEMC_OR_128        0xf8000000
727#define M860_MEMC_OR_256M       0xf0000000
728#define M860_MEMC_OR_512M       0xe0000000
729#define M860_MEMC_OR_1G         0xc0000000
730#define M860_MEMC_OR_2G         0x80000000
731#define M860_MEMC_OR_4G         0x00000000
732#define M860_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
733#define M860_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
734#define M860_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
735#define M860_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
736#define M860_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
737#define M860_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
738#define M860_MEMC_OR_BI         (1<8)       /* Burst inhibit */
739#define M860_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
740#define M860_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
741#define M860_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
742#define M860_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
743
744/*
745*************************************************************************
746*                         UPM Registers (MxMR)                          *
747*************************************************************************
748*/
749#define M860_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
750#define M860_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
751#define M860_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
752#define M860_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
753#define M860_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
754#define M860_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
755#define M860_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
756#define M860_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
757/*
758*************************************************************************
759*                         Memory Command Register (MCR)                 *
760*************************************************************************
761*/
762#define M860_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
763#define M860_MEMC_MCR_READ      (1<<30)     /* READ command */
764#define M860_MEMC_MCR_RUN       (2<<30)     /* RUN command */
765#define M860_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
766#define M860_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
767#define M860_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
768#define M860_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
769#define M860_MEMC_MCR_MAD(x)    (x)         /* Machine address */
770
771
772
773/*
774*************************************************************************
775*                         SI Mode Register (SIMODE)                     *
776*************************************************************************
777*/
778#define M860_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
779#define M860_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
780#define M860_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
781#define M860_SI_SMC2_BRG2       (1<<28)
782#define M860_SI_SMC2_BRG3       (2<<28)
783#define M860_SI_SMC2_BRG4       (3<<28)
784#define M860_SI_SMC2_CLK5       (0<<28)
785#define M860_SI_SMC2_CLK6       (1<<28)
786#define M860_SI_SMC2_CLK7       (2<<28)
787#define M860_SI_SMC2_CLK8       (3<<28)
788#define M860_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
789#define M860_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
790#define M860_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
791#define M860_SI_SMC1_BRG2       (1<<12)
792#define M860_SI_SMC1_BRG3       (2<<12)
793#define M860_SI_SMC1_BRG4       (3<<12)
794#define M860_SI_SMC1_CLK1       (0<<12)
795#define M860_SI_SMC1_CLK2       (1<<12)
796#define M860_SI_SMC1_CLK3       (2<<12)
797#define M860_SI_SMC1_CLK4       (3<<12)
798
799/*
800*************************************************************************
801*                  SDMA Configuration Register (SDCR)                   *
802*************************************************************************
803*/
804#define M860_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
805#define M860_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
806
807/*
808*************************************************************************
809*                  SDMA Status Register (SDSR)                          *
810*************************************************************************
811*/
812#define M860_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
813#define M860_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
814#define M860_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
815
816/*
817*************************************************************************
818*                      Baud (sic) Rate Generators                       *
819*************************************************************************
820*/
821#define M860_BRG_RST            (1<<17)         /* Reset generator */
822#define M860_BRG_EN             (1<<16)         /* Enable generator */
823#define M860_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
824#define M860_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
825#define M860_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
826#define M860_BRG_ATB            (1<<13)         /* Autobaud */
827#define M860_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
828#define M860_BRG_57600          (32<<1)
829#define M860_BRG_38400          (64<<1)
830#define M860_BRG_19200          (129<<1)
831#define M860_BRG_9600           (259<<1)
832#define M860_BRG_4800           (520<<1)
833#define M860_BRG_2400           (1040<<1)
834#define M860_BRG_1200           (2082<<1)
835#define M860_BRG_600            ((259<<1) | 1)
836#define M860_BRG_300            ((520<<1) | 1)
837#define M860_BRG_150            ((1040<<1) | 1)
838#define M860_BRG_75             ((2080<<1) | 1)
839
840#define M860_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
841#define M860_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
842#define M860_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
843#define M860_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
844#define M860_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
845#define M860_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
846#define M860_TGCR_STP1          (1<<1)    /* Stop timer */
847#define M860_TGCR_STP2          (1<<5)    /* Stop timer */
848#define M860_TGCR_STP3          (1<<9)    /* Stop timer */
849#define M860_TGCR_STP4          (1<<13)   /* Stop timer */
850#define M860_TGCR_RST1          (1<<0)    /* Enable timer */
851#define M860_TGCR_RST2          (1<<4)    /* Enable timer */
852#define M860_TGCR_RST3          (1<<8)    /* Enable timer */
853#define M860_TGCR_RST4          (1<<12)   /* Enable timer */
854#define M860_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
855#define M860_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
856
857#define M860_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
858#define M860_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
859#define M860_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
860#define M860_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
861#define M860_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
862#define M860_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
863#define M860_TMR_RESTART        (1<<3)    /* Restart timer after reference */
864#define M860_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
865#define M860_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
866#define M860_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
867#define M860_TMR_TGATE          (1<<0)    /* TGATE controls timer */
868
869#define M860_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
870#define M860_PISCR_PS           (1<<7)    /* PIT Interrupt state */
871#define M860_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
872#define M860_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
873#define M860_PISCR_PTE          (1<<0)    /* PIT enable */
874
875#define M860_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
876#define M860_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
877#define M860_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
878#define M860_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
879#define M860_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
880#define M860_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
881#define M860_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
882
883#define M860_SIMASK_IRM0        (1<<31)
884#define M860_SIMASK_LVM0        (1<<30)
885#define M860_SIMASK_IRM1        (1<<29)
886#define M860_SIMASK_LVM1        (1<<28)
887#define M860_SIMASK_IRM2        (1<<27)
888#define M860_SIMASK_LVM2        (1<<26)
889#define M860_SIMASK_IRM3        (1<<25)
890#define M860_SIMASK_LVM3        (1<<24)
891#define M860_SIMASK_IRM4        (1<<23)
892#define M860_SIMASK_LVM4        (1<<22)
893#define M860_SIMASK_IRM5        (1<<21)
894#define M860_SIMASK_LVM5        (1<<20)
895#define M860_SIMASK_IRM6        (1<<19)
896#define M860_SIMASK_LVM6        (1<<18)
897#define M860_SIMASK_IRM7        (1<<17)
898#define M860_SIMASK_LVM7        (1<<16)
899
900#define M860_SIUMCR_EARB        (1<<31)
901#define M860_SIUMCR_EARP0       (0<<28)
902#define M860_SIUMCR_EARP1       (1<<28)
903#define M860_SIUMCR_EARP2       (2<<28)
904#define M860_SIUMCR_EARP3       (3<<28)
905#define M860_SIUMCR_EARP4       (4<<28)
906#define M860_SIUMCR_EARP5       (5<<28)
907#define M860_SIUMCR_EARP6       (6<<28)
908#define M860_SIUMCR_EARP7       (7<<28)
909#define M860_SIUMCR_DSHW        (1<<23)
910#define M860_SIUMCR_DBGC0       (0<<21)
911#define M860_SIUMCR_DBGC1       (1<<21)
912#define M860_SIUMCR_DBGC2       (2<<21)
913#define M860_SIUMCR_DBGC3       (3<<21)
914#define M860_SIUMCR_DBPC0       (0<<19)
915#define M860_SIUMCR_DBPC1       (1<<19)
916#define M860_SIUMCR_DBPC2       (2<<19)
917#define M860_SIUMCR_DBPC3       (3<<19)
918#define M860_SIUMCR_FRC         (1<<17)
919#define M860_SIUMCR_DLK         (1<<16)
920#define M860_SIUMCR_PNCS        (1<<15)
921#define M860_SIUMCR_OPAR        (1<<14)
922#define M860_SIUMCR_DPC         (1<<13)
923#define M860_SIUMCR_MPRE        (1<<12)
924#define M860_SIUMCR_MLRC0       (0<<10)
925#define M860_SIUMCR_MLRC1       (1<<10)
926#define M860_SIUMCR_MLRC2       (2<<10)
927#define M860_SIUMCR_MLRC3       (3<<10)
928#define M860_SIUMCR_AEME        (1<<9)
929#define M860_SIUMCR_SEME        (1<<8)
930#define M860_SIUMCR_BSC         (1<<7)
931#define M860_SIUMCR_GB5E        (1<<6)
932#define M860_SIUMCR_B2DD        (1<<5)
933#define M860_SIUMCR_B3DD        (1<<4)
934/*
935*************************************************************************
936*                 MPC860 DUAL-PORT RAM AND REGISTERS                    *
937*************************************************************************
938*/
939typedef struct m860_ {
940       
941  /*
942   * SIU Block
943   */
944  rtems_unsigned32      siumcr;
945  rtems_unsigned32      sypcr;
946  rtems_unsigned32      swt;
947  rtems_unsigned16      _pad0;
948  rtems_unsigned16      swsr;
949  rtems_unsigned32      sipend;
950  rtems_unsigned32      simask;
951  rtems_unsigned32      siel;
952  rtems_unsigned32      sivec;
953  rtems_unsigned32      tesr;
954  rtems_unsigned32      _pad1[3];
955  rtems_unsigned32      sdcr;
956  rtems_unsigned8       _pad2[0x80-0x34];
957 
958  /*
959   * PCMCIA Block
960   */
961  rtems_unsigned32      pbr0;
962  rtems_unsigned32      por0;
963  rtems_unsigned32      pbr1;
964  rtems_unsigned32      por1;
965  rtems_unsigned32      pbr2;
966  rtems_unsigned32      por2;
967  rtems_unsigned32      pbr3;
968  rtems_unsigned32      por3;
969  rtems_unsigned32      pbr4;
970  rtems_unsigned32      por4;
971  rtems_unsigned32      pbr5;
972  rtems_unsigned32      por5;
973  rtems_unsigned32      pbr6;
974  rtems_unsigned32      por6;
975  rtems_unsigned32      pbr7;
976  rtems_unsigned32      por7;
977  rtems_unsigned8       _pad3[0xe0-0xc0];
978  rtems_unsigned32      pgcra;
979  rtems_unsigned32      pgcrb;
980  rtems_unsigned32      pscr;
981  rtems_unsigned32      _pad4;
982  rtems_unsigned32      pipr;
983  rtems_unsigned32      _pad5;
984  rtems_unsigned32      per;
985  rtems_unsigned32      _pad6;
986 
987  /*
988   * MEMC Block
989   */
990  m860MEMCRegisters_t   memc[8];
991  rtems_unsigned8       _pad7[0x164-0x140];
992  rtems_unsigned32      mar;
993  rtems_unsigned32      mcr;
994  rtems_unsigned32      _pad8;
995  rtems_unsigned32      mamr;
996  rtems_unsigned32      mbmr;
997  rtems_unsigned16      mstat;
998  rtems_unsigned16      mptpr;
999  rtems_unsigned32      mdr;
1000  rtems_unsigned8       _pad9[0x200-0x180];
1001 
1002  /*
1003   * System integration timers
1004   */
1005  rtems_unsigned16      tbscr;
1006  rtems_unsigned16      _pad10;
1007  rtems_unsigned32      tbreff0;
1008  rtems_unsigned32      tbreff1;
1009  rtems_unsigned8       _pad11[0x220-0x20c];
1010  rtems_unsigned16      rtcsc;
1011  rtems_unsigned16      _pad12;
1012  rtems_unsigned32      rtc;
1013  rtems_unsigned32      rtsec;
1014  rtems_unsigned32      rtcal;
1015  rtems_unsigned32      _pad13[4];
1016  rtems_unsigned16      piscr;
1017  rtems_unsigned16      _pad14;
1018  rtems_unsigned16      pitc;
1019  rtems_unsigned16      _pad_14_1;
1020  rtems_unsigned16      pitr;
1021  rtems_unsigned16      _pad_14_2;
1022  rtems_unsigned8       _pad15[0x280-0x24c];
1023 
1024 
1025  /*
1026   * Clocks and Reset
1027   */
1028  rtems_unsigned32      sccr;
1029  rtems_unsigned32      plprcr;
1030  rtems_unsigned32      rsr;
1031  rtems_unsigned8       _pad16[0x300-0x28c];
1032 
1033 
1034  /*
1035   * System integration timers keys
1036   */
1037  rtems_unsigned32      tbscrk;
1038  rtems_unsigned32      tbreff0k;
1039  rtems_unsigned32      tbreff1k;
1040  rtems_unsigned32      tbk;
1041  rtems_unsigned32      _pad17[4];
1042  rtems_unsigned32      rtcsk;
1043  rtems_unsigned32      rtck;
1044  rtems_unsigned32      rtseck;
1045  rtems_unsigned32      rtcalk;
1046  rtems_unsigned32      _pad18[4];
1047  rtems_unsigned32      piscrk;
1048  rtems_unsigned32      pitck;
1049  rtems_unsigned8       _pad19[0x380-0x348];
1050 
1051  /*
1052   * Clocks and Reset Keys
1053   */
1054  rtems_unsigned32      sccrk;
1055  rtems_unsigned32      plprck;
1056  rtems_unsigned32      rsrk;
1057  rtems_unsigned8       _pad20[0x400-0x38c];
1058  rtems_unsigned8       _pad21[0x800-0x400];
1059  rtems_unsigned8       _pad22[0x860-0x800];
1060 
1061 
1062  /*
1063   * I2C
1064   */
1065  rtems_unsigned8       i2mod;
1066  rtems_unsigned8       _pad23[3];
1067  rtems_unsigned8       i2add;
1068  rtems_unsigned8       _pad24[3];
1069  rtems_unsigned8       i2brg;
1070  rtems_unsigned8       _pad25[3];
1071  rtems_unsigned8       i2com;
1072  rtems_unsigned8       _pad26[3];
1073  rtems_unsigned8       i2cer;
1074  rtems_unsigned8       _pad27[3];
1075  rtems_unsigned8       i2cmr;
1076  rtems_unsigned8       _pad28[0x900-0x875];
1077 
1078  /*
1079   * DMA Block
1080   */
1081  rtems_unsigned32      _pad29;
1082  rtems_unsigned32      sdar;
1083  rtems_unsigned8       sdsr;
1084  rtems_unsigned8       _pad30[3];
1085  rtems_unsigned8       sdmr;
1086  rtems_unsigned8       _pad31[3];
1087  rtems_unsigned8       idsr1;
1088  rtems_unsigned8       _pad32[3];
1089  rtems_unsigned8       idmr1;
1090  rtems_unsigned8       _pad33[3];
1091  rtems_unsigned8       idsr2;
1092  rtems_unsigned8       _pad34[3];
1093  rtems_unsigned8       idmr2;
1094  rtems_unsigned8       _pad35[0x930-0x91d];
1095 
1096 
1097 
1098  /*
1099   * CPM Interrupt Control Block
1100   */
1101  rtems_unsigned16      civr;
1102  rtems_unsigned8       _pad36[14];
1103  rtems_unsigned32      cicr;
1104  rtems_unsigned32      cipr;
1105  rtems_unsigned32      cimr;
1106  rtems_unsigned32      cisr;
1107 
1108  /*
1109   * I/O Port Block
1110   */
1111  rtems_unsigned16      padir;
1112  rtems_unsigned16      papar;
1113  rtems_unsigned16      paodr;
1114  rtems_unsigned16      padat;
1115  rtems_unsigned8       _pad37[8];
1116  rtems_unsigned16      pcdir;
1117  rtems_unsigned16      pcpar;
1118  rtems_unsigned16      pcso;
1119  rtems_unsigned16      pcdat;
1120  rtems_unsigned16      pcint;
1121  rtems_unsigned8       _pad39[6];
1122  rtems_unsigned16      pddir;
1123  rtems_unsigned16      pdpar;
1124  rtems_unsigned16      _pad40;
1125  rtems_unsigned16      pddat;
1126  rtems_unsigned8       _pad41[8];
1127 
1128  /*
1129   * CPM Timers Block
1130   */
1131  rtems_unsigned16      tgcr;
1132  rtems_unsigned8       _pad42[14];
1133  rtems_unsigned16      tmr1;
1134  rtems_unsigned16      tmr2;
1135  rtems_unsigned16      trr1;
1136  rtems_unsigned16      trr2;
1137  rtems_unsigned16      tcr1;
1138  rtems_unsigned16      tcr2;
1139  rtems_unsigned16      tcn1;
1140  rtems_unsigned16      tcn2;
1141  rtems_unsigned16      tmr3;
1142  rtems_unsigned16      tmr4;
1143  rtems_unsigned16      trr3;
1144  rtems_unsigned16      trr4;
1145  rtems_unsigned16      tcr3;
1146  rtems_unsigned16      tcr4;
1147  rtems_unsigned16      tcn3;
1148  rtems_unsigned16      tcn4;
1149  rtems_unsigned16      ter1;
1150  rtems_unsigned16      ter2;
1151  rtems_unsigned16      ter3;
1152  rtems_unsigned16      ter4;
1153  rtems_unsigned8       _pad43[8];
1154 
1155 
1156 
1157  /*
1158   * CPM Block
1159   */
1160  rtems_unsigned16      cpcr;
1161  rtems_unsigned16      _pad44;
1162  rtems_unsigned16      rccr;
1163  rtems_unsigned8       _pad45;
1164  rtems_unsigned8       rmds;
1165  rtems_unsigned32      rmdr;
1166  rtems_unsigned16      rctr1;
1167  rtems_unsigned16      rctr2;
1168  rtems_unsigned16      rctr3;
1169  rtems_unsigned16      rctr4;
1170  rtems_unsigned16      _pad46;
1171  rtems_unsigned16      rter;
1172  rtems_unsigned16      _pad47;
1173  rtems_unsigned16      rtmr;
1174  rtems_unsigned8       _pad48[0x9f0-0x9dc];
1175 
1176  /*
1177   * BRG Block
1178   */
1179  rtems_unsigned32      brgc1;
1180  rtems_unsigned32      brgc2;
1181  rtems_unsigned32      brgc3;
1182  rtems_unsigned32      brgc4;
1183 
1184  /*
1185   * SCC Block
1186   */
1187  m860SCCRegisters_t    scc1;
1188  m860SCCRegisters_t    scc2;
1189  m860SCCRegisters_t    scc3;
1190  m860SCCRegisters_t    scc4;
1191 
1192  /*
1193   * SMC Block
1194   */
1195  m860SMCRegisters_t    smc1;
1196  m860SMCRegisters_t    smc2;
1197 
1198  /*
1199   * SPI Block
1200   */
1201  rtems_unsigned16      spmode;
1202  rtems_unsigned16      _pad49[2];
1203  rtems_unsigned8       spie;
1204  rtems_unsigned8       _pad50;
1205  rtems_unsigned16      _pad51;
1206  rtems_unsigned8       spim;
1207  rtems_unsigned8       _pad52[2];
1208  rtems_unsigned8       spcom;
1209  rtems_unsigned16      _pad53[2];
1210 
1211  /*
1212   * PIP Block
1213   */
1214  rtems_unsigned16      pipc;
1215  rtems_unsigned16      _pad54;
1216  rtems_unsigned16      ptpr;
1217  rtems_unsigned32      pbdir;
1218  rtems_unsigned32      pbpar;
1219  rtems_unsigned16      _pad55;
1220  rtems_unsigned16      pbodr;
1221  rtems_unsigned32      pbdat;
1222  rtems_unsigned32      _pad56[6];
1223 
1224  /*
1225   * SI Block
1226   */
1227  rtems_unsigned32      simode;
1228  rtems_unsigned8       sigmr;
1229  rtems_unsigned8       _pad57;
1230  rtems_unsigned8       sistr;
1231  rtems_unsigned8       sicmr;
1232  rtems_unsigned32      _pad58;
1233  rtems_unsigned32      sicr;
1234  rtems_unsigned16      sirp[2];
1235  rtems_unsigned32      _pad59[3];
1236  rtems_unsigned8       _pad60[0xc00-0xb00];
1237  rtems_unsigned8       siram[512];
1238
1239  /*
1240   * This is only used on the MPC860T - for the Fast Ethernet Controller (FEC)
1241   */
1242  m860FECRegisters_t         fec;
1243
1244  rtems_unsigned8       _pad62[0x2000-0x1000];
1245  /*
1246   * Dual-port RAM
1247   */
1248  rtems_unsigned8       dpram0[0x200];  /* BD/DATA/UCODE */
1249  rtems_unsigned8       dpram1[0x200];  /* BD/DATA/UCODE */
1250  rtems_unsigned8       dpram2[0x400];  /* BD/DATA/UCODE */
1251  rtems_unsigned8       dpram3[0x600];  /* BD/DATA*/
1252  rtems_unsigned8       dpram4[0x200];  /* BD/DATA/UCODE */
1253  rtems_unsigned8       _pad63[0x3c00-0x3000];
1254 
1255  /* When using SCC1 for ethernet, we lose the use of I2C since
1256   *  their parameters would overlap. Motorola has a microcode
1257   *  patch to move parameters around so that both can be used
1258   *  together. It is available on their web site somewhere
1259   *  under http://www.mot.com/mpc860. If ethernet is used on
1260   *  one (or more) of the other SCCs, then other CPM features
1261   *  will be unavailable:
1262   *    SCC2    -> lose SPI
1263   *    SCC3    -> lose SMC1
1264   *    SCC4    -> lose SMC2
1265   */
1266  m860SCCENparms_t      scc1p;
1267  rtems_unsigned8       _rsv1[0xCB0-0xC00-sizeof(m860SCCENparms_t)];
1268  m860MiscParms_t       miscp;
1269  rtems_unsigned8       _rsv2[0xcc0-0xCB0-sizeof(m860MiscParms_t)];
1270  m860IDMAparms_t       idma1p;
1271  rtems_unsigned8       _rsv3[0xd00-0xcc0-sizeof(m860IDMAparms_t)];
1272 
1273  m860SCCparms_t        scc2p;
1274  rtems_unsigned8       _rsv4[0xD80-0xD00-sizeof(m860SCCparms_t)];
1275  m860SPIparms_t        spip;
1276  rtems_unsigned8       _rsv5[0xDB0-0xD80-sizeof(m860SPIparms_t)];
1277  m860TimerParms_t      tmp;
1278  rtems_unsigned8       _rsv6[0xDC0-0xDB0-sizeof(m860TimerParms_t)];
1279  m860IDMAparms_t       idma2p;
1280  rtems_unsigned8       _rsv7[0xE00-0xDC0-sizeof(m860IDMAparms_t)];
1281 
1282  m860SCCparms_t        scc3p;
1283  rtems_unsigned8       _rsv8[0xE80-0xE00-sizeof(m860SCCparms_t)];
1284  m860SMCparms_t        smc1p;
1285  rtems_unsigned8       _rsv9[0xEC0-0xE80-sizeof(m860SMCparms_t)];
1286  m860DSPparms_t        dsp1p;
1287  rtems_unsigned8       _rsv10[0xF00-0xEC0-sizeof(m860DSPparms_t)];
1288 
1289  m860SCCparms_t        scc4p;
1290  rtems_unsigned8       _rsv11[0xF80-0xF00-sizeof(m860SCCparms_t)];
1291  m860SMCparms_t        smc2p;
1292  rtems_unsigned8       _rsv12[0xFC0-0xF80-sizeof(m860SMCparms_t)];
1293  m860DSPparms_t        dsp2p;
1294  rtems_unsigned8       _rsv13[0x1000-0xFC0-sizeof(m860DSPparms_t)];
1295} m860_t;
1296
1297extern volatile m860_t m860;
1298#endif /* ASM */
1299
1300#endif /* __MPC860_h */
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