[fbe75c6e] | 1 | /* |
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| 2 | ************************************************************************** |
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| 3 | ************************************************************************** |
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| 4 | ** ** |
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| 5 | ** MOTOROLA MPC860 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** |
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| 6 | ** POWERQUICC ** |
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| 7 | ** ** |
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| 8 | ** HARDWARE DECLARATIONS ** |
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| 9 | ** ** |
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| 10 | ** ** |
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| 11 | ** Submitted By: ** |
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| 12 | ** ** |
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| 13 | ** W. Eric Norum ** |
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| 14 | ** Saskatchewan Accelerator Laboratory ** |
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| 15 | ** University of Saskatchewan ** |
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| 16 | ** 107 North Road ** |
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| 17 | ** Saskatoon, Saskatchewan, CANADA ** |
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| 18 | ** S7N 5C6 ** |
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| 19 | ** ** |
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| 20 | ** eric@skatter.usask.ca ** |
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| 21 | ** ** |
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| 22 | ** Modified for use with the MPC860 (original code was for MC68360) ** |
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| 23 | ** by ** |
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| 24 | ** Jay Monkman ** |
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| 25 | ** Frasca International, Inc. ** |
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| 26 | ** 906 E. Airport Rd. ** |
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| 27 | ** Urbana, IL, 61801 ** |
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| 28 | ** ** |
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| 29 | ** jmonkman@frasca.com ** |
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| 30 | ** ** |
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| 31 | ************************************************************************** |
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| 32 | ************************************************************************** |
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| 33 | */ |
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| 34 | |
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| 35 | #ifndef __MPC860_h |
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| 36 | #define __MPC860_h |
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| 37 | |
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| 38 | #ifndef ASM |
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| 39 | /* |
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| 40 | Macros for SPRs |
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| 41 | */ |
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| 42 | |
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| 43 | #define M860_MI_CTR_GPM (1<<31) |
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| 44 | #define M860_MI_CTR_PPM (1<<30) |
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| 45 | #define M860_MI_CTR_CIDEF (1<<29) |
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| 46 | #define M860_MI_CTR_RSV4I (1<<27) |
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| 47 | #define M860_MI_CTR_PPCS (1<<25) |
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| 48 | |
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| 49 | #define M860_MD_CTR_GPM (1<<31) |
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| 50 | #define M860_MD_CTR_PPM (1<<30) |
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| 51 | #define M860_MD_CTR_CIDEF (1<<29) |
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| 52 | #define M860_MD_CTR_WTDEF (1<<28) |
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| 53 | #define M860_MD_CTR_RSV4D (1<<27) |
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| 54 | #define M860_MD_CTR_TWAM (1<<26) |
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| 55 | #define M860_MD_CTR_PPCS (1<<25) |
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| 56 | |
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| 57 | #define M860_MI_EPN_VALID (1<<9) |
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| 58 | |
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| 59 | #define M860_MD_EPN_VALID (1<<9) |
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| 60 | |
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| 61 | #define M860_MI_TWC_G (1<<4) |
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| 62 | #define M860_MI_TWC_PSS (0<<2) |
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| 63 | #define M860_MI_TWC_PS512 (1<<2) |
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| 64 | #define M860_MI_TWC_PS8 (3<<2) |
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| 65 | #define M860_MI_TWC_VALID (1) |
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| 66 | |
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| 67 | #define M860_MD_TWC_G (1<<4) |
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| 68 | #define M860_MD_TWC_PSS (0<<2) |
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| 69 | #define M860_MD_TWC_PS512 (1<<2) |
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| 70 | #define M860_MD_TWC_PS8 (3<<2) |
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| 71 | #define M860_MD_TWC_WT (1<<1) |
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| 72 | #define M860_MD_TWC_VALID (1) |
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| 73 | |
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| 74 | #define M860_MI_RPN_F (0xf<<4) |
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| 75 | #define M860_MI_RPN_16K (1<<3) |
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| 76 | #define M860_MI_RPN_SHARED (1<<2) |
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| 77 | #define M860_MI_RPN_CI (1<<1) |
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| 78 | #define M860_MI_RPN_VALID (1) |
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| 79 | |
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| 80 | #define M860_MD_RPN_CHANGE (1<<8) |
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| 81 | #define M860_MD_RPN_F (0xf<<4) |
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| 82 | #define M860_MD_RPN_16K (1<<3) |
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| 83 | #define M860_MD_RPN_SHARED (1<<2) |
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| 84 | #define M860_MD_RPN_CI (1<<1) |
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| 85 | #define M860_MD_RPN_VALID (1) |
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| 86 | |
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| 87 | #define M860_MI_AP_Kp (1) |
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| 88 | |
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| 89 | #define M860_MD_AP_Kp (1) |
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| 90 | |
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| 91 | #define M860_CACHE_CMD_SFWT (0x1<<24) |
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| 92 | #define M860_CACHE_CMD_ENABLE (0x2<<24) |
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| 93 | #define M860_CACHE_CMD_CFWT (0x3<<24) |
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| 94 | #define M860_CACHE_CMD_DISABLE (0x4<<24) |
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| 95 | #define M860_CACHE_CMD_STLES (0x5<<24) |
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| 96 | #define M860_CACHE_CMD_LLCB (0x6<<24) |
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| 97 | #define M860_CACHE_CMD_CLES (0x7<<24) |
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| 98 | #define M860_CACHE_CMD_UNLOCK (0x8<<24) |
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| 99 | #define M860_CACHE_CMD_UNLOCKALL (0xa<<24) |
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| 100 | #define M860_CACHE_CMD_INVALIDATE (0xc<<24) |
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| 101 | #define M860_CACHE_CMD_FLUSH (0xe<<24) |
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| 102 | |
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| 103 | |
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| 104 | |
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| 105 | /* |
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| 106 | ************************************************************************* |
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| 107 | * REGISTER SUBBLOCKS * |
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| 108 | ************************************************************************* |
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| 109 | */ |
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| 110 | |
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| 111 | /* |
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| 112 | * Memory controller registers |
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| 113 | */ |
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| 114 | typedef struct m860MEMCRegisters_ { |
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| 115 | rtems_unsigned32 br; |
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| 116 | rtems_unsigned32 or; |
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| 117 | } m860MEMCRegisters_t; |
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| 118 | |
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| 119 | /* |
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| 120 | * Serial Communications Controller registers |
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| 121 | */ |
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| 122 | typedef struct m860SCCRegisters_ { |
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| 123 | rtems_unsigned32 gsmr_l; |
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| 124 | rtems_unsigned32 gsmr_h; |
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| 125 | rtems_unsigned16 psmr; |
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| 126 | rtems_unsigned16 _pad0; |
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| 127 | rtems_unsigned16 todr; |
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| 128 | rtems_unsigned16 dsr; |
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| 129 | rtems_unsigned16 scce; |
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| 130 | rtems_unsigned16 _pad1; |
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| 131 | rtems_unsigned16 sccm; |
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| 132 | rtems_unsigned8 _pad2; |
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| 133 | rtems_unsigned8 sccs; |
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| 134 | rtems_unsigned32 _pad3[2]; |
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| 135 | } m860SCCRegisters_t; |
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| 136 | |
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| 137 | /* |
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| 138 | * Serial Management Controller registers |
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| 139 | */ |
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| 140 | typedef struct m860SMCRegisters_ { |
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| 141 | rtems_unsigned16 _pad0; |
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| 142 | rtems_unsigned16 smcmr; |
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| 143 | rtems_unsigned16 _pad1; |
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| 144 | rtems_unsigned8 smce; |
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| 145 | rtems_unsigned8 _pad2; |
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| 146 | rtems_unsigned16 _pad3; |
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| 147 | rtems_unsigned8 smcm; |
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| 148 | rtems_unsigned8 _pad4; |
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| 149 | rtems_unsigned32 _pad5; |
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| 150 | } m860SMCRegisters_t; |
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| 151 | |
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| 152 | /* |
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| 153 | * Fast Ethernet Controller registers (Only on MPC860T) |
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| 154 | */ |
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| 155 | typedef struct m860FECRegisters_ { |
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| 156 | rtems_unsigned32 addr_low; |
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| 157 | rtems_unsigned32 addr_high; |
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| 158 | rtems_unsigned32 hash_table_high; |
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| 159 | rtems_unsigned32 hash_table_low; |
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| 160 | rtems_unsigned32 r_des_start; |
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| 161 | rtems_unsigned32 x_des_start; |
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| 162 | rtems_unsigned32 r_buf_size; |
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| 163 | rtems_unsigned32 _pad0[9]; |
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| 164 | rtems_unsigned32 ecntrl; |
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| 165 | rtems_unsigned32 ievent; |
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| 166 | rtems_unsigned32 imask; |
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| 167 | rtems_unsigned32 ivec; |
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| 168 | rtems_unsigned32 r_des_active; |
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| 169 | rtems_unsigned32 x_des_active; |
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| 170 | rtems_unsigned32 _pad1[10]; |
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| 171 | rtems_unsigned32 mii_data; |
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| 172 | rtems_unsigned32 mii_speed; |
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| 173 | rtems_unsigned32 _pad2[17]; |
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| 174 | rtems_unsigned32 r_bound; |
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| 175 | rtems_unsigned32 r_fstart; |
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| 176 | rtems_unsigned32 _pad3[6]; |
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| 177 | rtems_unsigned32 x_fstart; |
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| 178 | rtems_unsigned32 _pad4[17]; |
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| 179 | rtems_unsigned32 fun_code; |
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| 180 | rtems_unsigned32 _pad5[3]; |
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| 181 | rtems_unsigned32 r_cntrl; |
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| 182 | rtems_unsigned32 r_hash; |
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| 183 | rtems_unsigned32 _pad6[14]; |
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| 184 | rtems_unsigned32 x_cntrl; |
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| 185 | rtems_unsigned32 _pad7[30]; |
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| 186 | |
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| 187 | } m860FECRegisters_t; |
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| 188 | |
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| 189 | #define M860_FEC_IEVENT_HBERR (1 << 31) |
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| 190 | #define M860_FEC_IEVENT_BABR (1 << 30) |
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| 191 | #define M860_FEC_IEVENT_BABT (1 << 29) |
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| 192 | #define M860_FEC_IEVENT_GRA (1 << 28) |
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| 193 | #define M860_FEC_IEVENT_TFINT (1 << 27) |
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| 194 | #define M860_FEC_IEVENT_TXB (1 << 26) |
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| 195 | #define M860_FEC_IEVENT_RFINT (1 << 25) |
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| 196 | #define M860_FEC_IEVENT_RXB (1 << 24) |
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| 197 | #define M860_FEC_IEVENT_MII (1 << 23) |
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| 198 | #define M860_FEC_IEVENT_EBERR (1 << 22) |
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| 199 | #define M860_FEC_IMASK_HBEEN (1 << 31) |
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| 200 | #define M860_FEC_IMASK_BREEN (1 << 30) |
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| 201 | #define M860_FEC_IMASK_BTEN (1 << 29) |
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| 202 | #define M860_FEC_IMASK_GRAEN (1 << 28) |
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| 203 | #define M860_FEC_IMASK_TFIEN (1 << 27) |
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| 204 | #define M860_FEC_IMASK_TBIEN (1 << 26) |
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| 205 | #define M860_FEC_IMASK_RFIEN (1 << 25) |
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| 206 | #define M860_FEC_IMASK_RBIEN (1 << 24) |
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| 207 | #define M860_FEC_IMASK_MIIEN (1 << 23) |
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| 208 | #define M860_FEC_IMASK_EBERREN (1 << 22) |
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| 209 | |
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| 210 | |
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| 211 | /* |
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| 212 | ************************************************************************* |
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| 213 | * Miscellaneous Parameters * |
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| 214 | ************************************************************************* |
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| 215 | */ |
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| 216 | typedef struct m860MiscParms_ { |
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| 217 | rtems_unsigned16 rev_num; |
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| 218 | rtems_unsigned16 _res1; |
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| 219 | rtems_unsigned32 _res2; |
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| 220 | rtems_unsigned32 _res3; |
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| 221 | } m860MiscParms_t; |
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| 222 | |
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| 223 | /* |
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| 224 | ************************************************************************* |
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| 225 | * RISC Timers * |
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| 226 | ************************************************************************* |
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| 227 | */ |
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| 228 | typedef struct m860TimerParms_ { |
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| 229 | rtems_unsigned16 tm_base; |
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| 230 | rtems_unsigned16 _tm_ptr; |
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| 231 | rtems_unsigned16 _r_tmr; |
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| 232 | rtems_unsigned16 _r_tmv; |
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| 233 | rtems_unsigned32 tm_cmd; |
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| 234 | rtems_unsigned32 tm_cnt; |
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| 235 | } m860TimerParms_t; |
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| 236 | |
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| 237 | /* |
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| 238 | * RISC Controller Configuration Register (RCCR) |
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| 239 | * All other bits in this register are reserved. |
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| 240 | */ |
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| 241 | #define M860_RCCR_TIME (1<<15) /* Enable timer */ |
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| 242 | #define M860_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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| 243 | #define M860_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ |
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| 244 | #define M860_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ |
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| 245 | #define M860_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ |
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| 246 | #define M860_RCCR_EIE (1<<3) /* External Interrupt Enable */ |
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| 247 | #define M860_RCCR_SCD (1<<2) /* Scheduler Configuration */ |
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| 248 | #define M860_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ |
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| 249 | |
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| 250 | /* |
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| 251 | * Command register |
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| 252 | * Set up this register before issuing a M860_CR_OP_SET_TIMER command. |
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| 253 | */ |
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| 254 | #define M860_TM_CMD_V (1<<31) /* Set to enable timer */ |
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| 255 | #define M860_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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| 256 | #define M860_TM_CMD_PWM (1<<29) /* Set for PWM operation */ |
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| 257 | #define M860_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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| 258 | #define M860_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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| 259 | |
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| 260 | /* |
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| 261 | ************************************************************************* |
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| 262 | * DMA Controllers * |
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| 263 | ************************************************************************* |
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| 264 | */ |
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| 265 | typedef struct m860IDMAparms_ { |
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| 266 | rtems_unsigned16 ibase; |
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| 267 | rtems_unsigned16 dcmr; |
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| 268 | rtems_unsigned32 _sapr; |
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| 269 | rtems_unsigned32 _dapr; |
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| 270 | rtems_unsigned16 ibptr; |
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| 271 | rtems_unsigned16 _write_sp; |
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| 272 | rtems_unsigned32 _s_byte_c; |
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| 273 | rtems_unsigned32 _d_byte_c; |
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| 274 | rtems_unsigned32 _s_state; |
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| 275 | rtems_unsigned32 _itemp[4]; |
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| 276 | rtems_unsigned32 _sr_mem; |
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| 277 | rtems_unsigned16 _read_sp; |
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| 278 | rtems_unsigned16 _res0; |
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| 279 | rtems_unsigned16 _res1; |
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| 280 | rtems_unsigned16 _res2; |
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| 281 | rtems_unsigned32 _d_state; |
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| 282 | } m860IDMAparms_t; |
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| 283 | |
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| 284 | |
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| 285 | /* |
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| 286 | ************************************************************************* |
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| 287 | * DSP * |
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| 288 | ************************************************************************* |
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| 289 | */ |
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| 290 | typedef struct m860DSPparms_ { |
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| 291 | rtems_unsigned32 fdbase; |
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| 292 | rtems_unsigned32 _fd_ptr; |
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| 293 | rtems_unsigned32 _dstate; |
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| 294 | rtems_unsigned32 _pad0; |
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| 295 | rtems_unsigned16 _dstatus; |
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| 296 | rtems_unsigned16 _i; |
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| 297 | rtems_unsigned16 _tap; |
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| 298 | rtems_unsigned16 _cbase; |
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| 299 | rtems_unsigned16 _pad1; |
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| 300 | rtems_unsigned16 _xptr; |
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| 301 | rtems_unsigned16 _pad2; |
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| 302 | rtems_unsigned16 _yptr; |
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| 303 | rtems_unsigned16 _m; |
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| 304 | rtems_unsigned16 _pad3; |
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| 305 | rtems_unsigned16 _n; |
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| 306 | rtems_unsigned16 _pad4; |
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| 307 | rtems_unsigned16 _k; |
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| 308 | rtems_unsigned16 _pad5; |
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| 309 | } m860DSPparms_t; |
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| 310 | |
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| 311 | /* |
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| 312 | ************************************************************************* |
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| 313 | * Serial Communication Controllers * |
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| 314 | ************************************************************************* |
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| 315 | */ |
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| 316 | typedef struct m860SCCparms_ { |
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| 317 | rtems_unsigned16 rbase; |
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| 318 | rtems_unsigned16 tbase; |
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| 319 | rtems_unsigned8 rfcr; |
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| 320 | rtems_unsigned8 tfcr; |
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| 321 | rtems_unsigned16 mrblr; |
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| 322 | rtems_unsigned32 _rstate; |
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| 323 | rtems_unsigned32 _pad0; |
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| 324 | rtems_unsigned16 _rbptr; |
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| 325 | rtems_unsigned16 _pad1; |
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| 326 | rtems_unsigned32 _pad2; |
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| 327 | rtems_unsigned32 _tstate; |
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| 328 | rtems_unsigned32 _pad3; |
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| 329 | rtems_unsigned16 _tbptr; |
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| 330 | rtems_unsigned16 _pad4; |
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| 331 | rtems_unsigned32 _pad5; |
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| 332 | rtems_unsigned32 _rcrc; |
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| 333 | rtems_unsigned32 _tcrc; |
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| 334 | union { |
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| 335 | struct { |
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| 336 | rtems_unsigned32 _res0; |
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| 337 | rtems_unsigned32 _res1; |
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| 338 | rtems_unsigned16 max_idl; |
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| 339 | rtems_unsigned16 _idlc; |
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| 340 | rtems_unsigned16 brkcr; |
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| 341 | rtems_unsigned16 parec; |
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| 342 | rtems_unsigned16 frmec; |
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| 343 | rtems_unsigned16 nosec; |
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| 344 | rtems_unsigned16 brkec; |
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| 345 | rtems_unsigned16 brklen; |
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| 346 | rtems_unsigned16 uaddr[2]; |
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| 347 | rtems_unsigned16 _rtemp; |
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| 348 | rtems_unsigned16 toseq; |
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| 349 | rtems_unsigned16 character[8]; |
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| 350 | rtems_unsigned16 rccm; |
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| 351 | rtems_unsigned16 rccr; |
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| 352 | rtems_unsigned16 rlbc; |
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| 353 | } uart; |
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| 354 | } un; |
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| 355 | } m860SCCparms_t; |
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| 356 | |
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| 357 | typedef struct m860SCCENparms_ { |
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| 358 | rtems_unsigned16 rbase; |
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| 359 | rtems_unsigned16 tbase; |
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| 360 | rtems_unsigned8 rfcr; |
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| 361 | rtems_unsigned8 tfcr; |
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| 362 | rtems_unsigned16 mrblr; |
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| 363 | rtems_unsigned32 _rstate; |
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| 364 | rtems_unsigned32 _pad0; |
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| 365 | rtems_unsigned16 _rbptr; |
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| 366 | rtems_unsigned16 _pad1; |
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| 367 | rtems_unsigned32 _pad2; |
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| 368 | rtems_unsigned32 _tstate; |
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| 369 | rtems_unsigned32 _pad3; |
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| 370 | rtems_unsigned16 _tbptr; |
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| 371 | rtems_unsigned16 _pad4; |
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| 372 | rtems_unsigned32 _pad5; |
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| 373 | rtems_unsigned32 _rcrc; |
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| 374 | rtems_unsigned32 _tcrc; |
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| 375 | union { |
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| 376 | struct { |
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| 377 | rtems_unsigned32 _res0; |
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| 378 | rtems_unsigned32 _res1; |
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| 379 | rtems_unsigned16 max_idl; |
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| 380 | rtems_unsigned16 _idlc; |
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| 381 | rtems_unsigned16 brkcr; |
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| 382 | rtems_unsigned16 parec; |
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| 383 | rtems_unsigned16 frmec; |
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| 384 | rtems_unsigned16 nosec; |
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| 385 | rtems_unsigned16 brkec; |
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| 386 | rtems_unsigned16 brklen; |
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| 387 | rtems_unsigned16 uaddr[2]; |
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| 388 | rtems_unsigned16 _rtemp; |
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| 389 | rtems_unsigned16 toseq; |
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| 390 | rtems_unsigned16 character[8]; |
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| 391 | rtems_unsigned16 rccm; |
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| 392 | rtems_unsigned16 rccr; |
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| 393 | rtems_unsigned16 rlbc; |
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| 394 | } uart; |
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| 395 | struct { |
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| 396 | rtems_unsigned32 c_pres; |
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| 397 | rtems_unsigned32 c_mask; |
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| 398 | rtems_unsigned32 crcec; |
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| 399 | rtems_unsigned32 alec; |
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| 400 | rtems_unsigned32 disfc; |
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| 401 | rtems_unsigned16 pads; |
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| 402 | rtems_unsigned16 ret_lim; |
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| 403 | rtems_unsigned16 _ret_cnt; |
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| 404 | rtems_unsigned16 mflr; |
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| 405 | rtems_unsigned16 minflr; |
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| 406 | rtems_unsigned16 maxd1; |
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| 407 | rtems_unsigned16 maxd2; |
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| 408 | rtems_unsigned16 _maxd; |
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| 409 | rtems_unsigned16 dma_cnt; |
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| 410 | rtems_unsigned16 _max_b; |
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| 411 | rtems_unsigned16 gaddr1; |
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| 412 | rtems_unsigned16 gaddr2; |
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| 413 | rtems_unsigned16 gaddr3; |
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| 414 | rtems_unsigned16 gaddr4; |
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| 415 | rtems_unsigned32 _tbuf0data0; |
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| 416 | rtems_unsigned32 _tbuf0data1; |
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| 417 | rtems_unsigned32 _tbuf0rba0; |
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| 418 | rtems_unsigned32 _tbuf0crc; |
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| 419 | rtems_unsigned16 _tbuf0bcnt; |
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| 420 | rtems_unsigned16 paddr_h; |
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| 421 | rtems_unsigned16 paddr_m; |
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| 422 | rtems_unsigned16 paddr_l; |
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| 423 | rtems_unsigned16 p_per; |
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| 424 | rtems_unsigned16 _rfbd_ptr; |
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| 425 | rtems_unsigned16 _tfbd_ptr; |
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| 426 | rtems_unsigned16 _tlbd_ptr; |
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| 427 | rtems_unsigned32 _tbuf1data0; |
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| 428 | rtems_unsigned32 _tbuf1data1; |
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| 429 | rtems_unsigned32 _tbuf1rba0; |
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| 430 | rtems_unsigned32 _tbuf1crc; |
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| 431 | rtems_unsigned16 _tbuf1bcnt; |
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| 432 | rtems_unsigned16 _tx_len; |
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| 433 | rtems_unsigned16 iaddr1; |
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| 434 | rtems_unsigned16 iaddr2; |
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| 435 | rtems_unsigned16 iaddr3; |
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| 436 | rtems_unsigned16 iaddr4; |
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| 437 | rtems_unsigned16 _boff_cnt; |
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| 438 | rtems_unsigned16 taddr_l; |
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| 439 | rtems_unsigned16 taddr_m; |
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| 440 | rtems_unsigned16 taddr_h; |
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| 441 | } ethernet; |
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| 442 | } un; |
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| 443 | } m860SCCENparms_t; |
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| 444 | |
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| 445 | /* |
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| 446 | * Receive and transmit function code register bits |
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| 447 | * These apply to the function code registers of all devices, not just SCC. |
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| 448 | */ |
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| 449 | #define M860_RFCR_BO(x) ((x)<<3) |
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| 450 | #define M860_RFCR_MOT (2<<3) |
---|
| 451 | #define M860_RFCR_DMA_SPACE(x) (x) |
---|
| 452 | #define M860_TFCR_BO(x) ((x)<<3) |
---|
| 453 | #define M860_TFCR_MOT (2<<3) |
---|
| 454 | #define M860_TFCR_DMA_SPACE(x) (x) |
---|
| 455 | |
---|
| 456 | /* |
---|
| 457 | ************************************************************************* |
---|
| 458 | * Serial Management Controllers * |
---|
| 459 | ************************************************************************* |
---|
| 460 | */ |
---|
| 461 | typedef struct m860SMCparms_ { |
---|
| 462 | rtems_unsigned16 rbase; |
---|
| 463 | rtems_unsigned16 tbase; |
---|
| 464 | rtems_unsigned8 rfcr; |
---|
| 465 | rtems_unsigned8 tfcr; |
---|
| 466 | rtems_unsigned16 mrblr; |
---|
| 467 | rtems_unsigned32 _rstate; |
---|
| 468 | rtems_unsigned32 _pad0; |
---|
| 469 | rtems_unsigned16 _rbptr; |
---|
| 470 | rtems_unsigned16 _pad1; |
---|
| 471 | rtems_unsigned32 _pad2; |
---|
| 472 | rtems_unsigned32 _tstate; |
---|
| 473 | rtems_unsigned32 _pad3; |
---|
| 474 | rtems_unsigned16 _tbptr; |
---|
| 475 | rtems_unsigned16 _pad4; |
---|
| 476 | rtems_unsigned32 _pad5; |
---|
| 477 | union { |
---|
| 478 | struct { |
---|
| 479 | rtems_unsigned16 max_idl; |
---|
| 480 | rtems_unsigned16 _idlc; |
---|
| 481 | rtems_unsigned16 brklen; |
---|
| 482 | rtems_unsigned16 brkec; |
---|
| 483 | rtems_unsigned16 brkcr; |
---|
| 484 | rtems_unsigned16 _r_mask; |
---|
| 485 | } uart; |
---|
| 486 | struct { |
---|
| 487 | rtems_unsigned16 _pad0[5]; |
---|
| 488 | } transparent; |
---|
| 489 | } un; |
---|
| 490 | } m860SMCparms_t; |
---|
| 491 | |
---|
| 492 | /* |
---|
| 493 | * Mode register |
---|
| 494 | */ |
---|
| 495 | #define M860_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
---|
| 496 | #define M860_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
---|
| 497 | #define M860_SMCMR_PARITY (1<<9) /* Enable parity */ |
---|
| 498 | #define M860_SMCMR_EVEN (1<<8) /* Even parity */ |
---|
| 499 | #define M860_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
---|
| 500 | #define M860_SMCMR_SM_UART (2<<4) /* UART Mode */ |
---|
| 501 | #define M860_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
---|
| 502 | #define M860_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
---|
| 503 | #define M860_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
---|
| 504 | #define M860_SMCMR_TEN (1<<1) /* Enable transmitter */ |
---|
| 505 | #define M860_SMCMR_REN (1<<0) /* Enable receiver */ |
---|
| 506 | |
---|
| 507 | /* |
---|
| 508 | * Event and mask registers (SMCE, SMCM) |
---|
| 509 | */ |
---|
| 510 | #define M860_SMCE_BRKE (1<<6) |
---|
| 511 | #define M860_SMCE_BRK (1<<4) |
---|
| 512 | #define M860_SMCE_BSY (1<<2) |
---|
| 513 | #define M860_SMCE_TX (1<<1) |
---|
| 514 | #define M860_SMCE_RX (1<<0) |
---|
| 515 | |
---|
| 516 | /* |
---|
| 517 | ************************************************************************* |
---|
| 518 | * Serial Peripheral Interface * |
---|
| 519 | ************************************************************************* |
---|
| 520 | */ |
---|
| 521 | typedef struct m860SPIparms_ { |
---|
| 522 | rtems_unsigned16 rbase; |
---|
| 523 | rtems_unsigned16 tbase; |
---|
| 524 | rtems_unsigned8 rfcr; |
---|
| 525 | rtems_unsigned8 tfcr; |
---|
| 526 | rtems_unsigned16 mrblr; |
---|
| 527 | rtems_unsigned32 _rstate; |
---|
| 528 | rtems_unsigned32 _pad0; |
---|
| 529 | rtems_unsigned16 _rbptr; |
---|
| 530 | rtems_unsigned16 _pad1; |
---|
| 531 | rtems_unsigned32 _pad2; |
---|
| 532 | rtems_unsigned32 _tstate; |
---|
| 533 | rtems_unsigned32 _pad3; |
---|
| 534 | rtems_unsigned16 _tbptr; |
---|
| 535 | rtems_unsigned16 _pad4; |
---|
| 536 | rtems_unsigned32 _pad5; |
---|
| 537 | } m860SPIparms_t; |
---|
| 538 | |
---|
| 539 | /* |
---|
| 540 | * Mode register (SPMODE) |
---|
| 541 | */ |
---|
| 542 | #define M860_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
---|
| 543 | #define M860_SPMODE_CI (1<<13) /* Clock invert */ |
---|
| 544 | #define M860_SPMODE_CP (1<<12) /* Clock phase */ |
---|
| 545 | #define M860_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
---|
| 546 | #define M860_SPMODE_REV (1<<10) /* Reverse data */ |
---|
| 547 | #define M860_SPMODE_MASTER (1<<9) /* SPI is master */ |
---|
| 548 | #define M860_SPMODE_EN (1<<8) /* Enable SPI */ |
---|
| 549 | #define M860_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
---|
| 550 | #define M860_SPMODE_PM(x) (x) /* Prescaler modulus */ |
---|
| 551 | |
---|
| 552 | /* |
---|
| 553 | * Mode register (SPCOM) |
---|
| 554 | */ |
---|
| 555 | #define M860_SPCOM_STR (1<<7) /* Start transmit */ |
---|
| 556 | |
---|
| 557 | /* |
---|
| 558 | * Event and mask registers (SPIE, SPIM) |
---|
| 559 | */ |
---|
| 560 | #define M860_SPIE_MME (1<<5) /* Multi-master error */ |
---|
| 561 | #define M860_SPIE_TXE (1<<4) /* Tx error */ |
---|
| 562 | #define M860_SPIE_BSY (1<<2) /* Busy condition*/ |
---|
| 563 | #define M860_SPIE_TXB (1<<1) /* Tx buffer */ |
---|
| 564 | #define M860_SPIE_RXB (1<<0) /* Rx buffer */ |
---|
| 565 | |
---|
| 566 | /* |
---|
| 567 | ************************************************************************* |
---|
| 568 | * SDMA (SCC, SMC, SPI) Buffer Descriptors * |
---|
| 569 | ************************************************************************* |
---|
| 570 | */ |
---|
| 571 | typedef struct m860BufferDescriptor_ { |
---|
| 572 | rtems_unsigned16 status; |
---|
| 573 | rtems_unsigned16 length; |
---|
| 574 | volatile void *buffer; |
---|
| 575 | } m860BufferDescriptor_t; |
---|
| 576 | |
---|
| 577 | /* |
---|
| 578 | * Bits in receive buffer descriptor status word |
---|
| 579 | */ |
---|
| 580 | #define M860_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
| 581 | #define M860_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
| 582 | #define M860_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
| 583 | #define M860_BD_LAST (1<<11) /* Ethernet, SPI */ |
---|
| 584 | #define M860_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
---|
| 585 | #define M860_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
---|
| 586 | #define M860_BD_ADDRESS (1<<10) /* SCC UART */ |
---|
| 587 | #define M860_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
---|
| 588 | #define M860_BD_MISS (1<<8) /* Ethernet */ |
---|
| 589 | #define M860_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
---|
| 590 | #define M860_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
---|
| 591 | #define M860_BD_LONG (1<<5) /* Ethernet */ |
---|
| 592 | #define M860_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
---|
| 593 | #define M860_BD_NONALIGNED (1<<4) /* Ethernet */ |
---|
| 594 | #define M860_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
---|
| 595 | #define M860_BD_SHORT (1<<3) /* Ethernet */ |
---|
| 596 | #define M860_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
---|
| 597 | #define M860_BD_CRC_ERROR (1<<2) /* Ethernet */ |
---|
| 598 | #define M860_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
| 599 | #define M860_BD_COLLISION (1<<0) /* Ethernet */ |
---|
| 600 | #define M860_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ |
---|
| 601 | #define M860_BD_MASTER_ERROR (1<<0) /* SPI */ |
---|
| 602 | |
---|
| 603 | /* |
---|
| 604 | * Bits in transmit buffer descriptor status word |
---|
| 605 | * Many bits have the same meaning as those in receiver buffer descriptors. |
---|
| 606 | */ |
---|
| 607 | #define M860_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
---|
| 608 | #define M860_BD_PAD (1<<14) /* Ethernet */ |
---|
| 609 | #define M860_BD_CTS_REPORT (1<<11) /* SCC UART */ |
---|
| 610 | #define M860_BD_TX_CRC (1<<10) /* Ethernet */ |
---|
| 611 | #define M860_BD_DEFER (1<<9) /* Ethernet */ |
---|
| 612 | #define M860_BD_HEARTBEAT (1<<8) /* Ethernet */ |
---|
| 613 | #define M860_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
---|
| 614 | #define M860_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
---|
| 615 | #define M860_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
---|
| 616 | #define M860_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
---|
| 617 | #define M860_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
---|
| 618 | #define M860_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
---|
| 619 | #define M860_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
---|
| 620 | #define M860_BD_CTS_LOST (1<<0) /* SCC UART */ |
---|
| 621 | |
---|
| 622 | /* |
---|
| 623 | ************************************************************************* |
---|
| 624 | * IDMA Buffer Descriptors * |
---|
| 625 | ************************************************************************* |
---|
| 626 | */ |
---|
| 627 | typedef struct m860IDMABufferDescriptor_ { |
---|
| 628 | rtems_unsigned16 status; |
---|
| 629 | rtems_unsigned8 dfcr; |
---|
| 630 | rtems_unsigned8 sfcr; |
---|
| 631 | rtems_unsigned32 length; |
---|
| 632 | void *source; |
---|
| 633 | void *destination; |
---|
| 634 | } m860IDMABufferDescriptor_t; |
---|
| 635 | |
---|
| 636 | /* |
---|
| 637 | ************************************************************************* |
---|
| 638 | * RISC Communication Processor Module Command Register (CR) * |
---|
| 639 | ************************************************************************* |
---|
| 640 | */ |
---|
| 641 | #define M860_CR_RST (1<<15) /* Reset communication processor */ |
---|
| 642 | #define M860_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
---|
| 643 | #define M860_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
---|
| 644 | #define M860_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
---|
| 645 | #define M860_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
---|
| 646 | #define M860_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
---|
| 647 | #define M860_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
---|
| 648 | #define M860_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
---|
| 649 | #define M860_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
---|
| 650 | #define M860_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
---|
| 651 | #define M860_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
---|
| 652 | #define M860_CR_OP_SET_TIMER (8<<8) /* Timer */ |
---|
| 653 | #define M860_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
---|
| 654 | #define M860_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
---|
| 655 | #define M860_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
---|
| 656 | #define M860_CR_OP_STOP_IDMA (11<<8) /* IDMA */ |
---|
| 657 | #define M860_CR_OP_START_DSP (12<<8) /* DSP */ |
---|
| 658 | #define M860_CR_OP_INIT_DSP (13<<8) /* DSP */ |
---|
| 659 | |
---|
| 660 | #define M860_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
---|
| 661 | #define M860_CR_CHAN_I2C (1<<4) |
---|
| 662 | #define M860_CR_CHAN_IDMA1 (1<<4) |
---|
| 663 | #define M860_CR_CHAN_SCC2 (4<<4) |
---|
| 664 | #define M860_CR_CHAN_SPI (5<<4) |
---|
| 665 | #define M860_CR_CHAN_IDMA2 (5<<4) |
---|
| 666 | #define M860_CR_CHAN_TIMER (5<<4) |
---|
| 667 | #define M860_CR_CHAN_SCC3 (8<<4) |
---|
| 668 | #define M860_CR_CHAN_SMC1 (9<<4) |
---|
| 669 | #define M860_CR_CHAN_DSP1 (9<<4) |
---|
| 670 | #define M860_CR_CHAN_SCC4 (12<<4) |
---|
| 671 | #define M860_CR_CHAN_SMC2 (13<<4) |
---|
| 672 | #define M860_CR_CHAN_DSP2 (13<<4) |
---|
| 673 | #define M860_CR_FLG (1<<0) /* Command flag */ |
---|
| 674 | |
---|
| 675 | /* |
---|
| 676 | ************************************************************************* |
---|
| 677 | * System Protection Control Register (SYPCR) * |
---|
| 678 | ************************************************************************* |
---|
| 679 | */ |
---|
| 680 | #define M860_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ |
---|
| 681 | #define M860_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
| 682 | #define M860_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
| 683 | #define M860_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
| 684 | #define M860_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
| 685 | #define M860_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
| 686 | #define M860_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
| 687 | |
---|
| 688 | /* |
---|
| 689 | ************************************************************************* |
---|
| 690 | * Memory Control Registers * |
---|
| 691 | ************************************************************************* |
---|
| 692 | */ |
---|
| 693 | #define M860_UPM_AMX_8col (0<<20) /* 8 column DRAM */ |
---|
| 694 | #define M860_UPM_AMX_9col (1<<20) /* 9 column DRAM */ |
---|
| 695 | #define M860_UPM_AMX_10col (2<<20) /* 10 column DRAM */ |
---|
| 696 | #define M860_UPM_AMX_11col (3<<20) /* 11 column DRAM */ |
---|
| 697 | #define M860_UPM_AMX_12col (4<<20) /* 12 column DRAM */ |
---|
| 698 | #define M860_UPM_AMX_13col (5<<20) /* 13 column DRAM */ |
---|
| 699 | #define M860_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ |
---|
| 700 | #define M860_MSR_WPER (1<<7) /* Write protection error */ |
---|
| 701 | #define M860_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ |
---|
| 702 | #define M860_BR_BA(x) ((x)&0xffff8000) /* Base address */ |
---|
| 703 | #define M860_BR_AT(x) ((x)<<12) /* Address type */ |
---|
| 704 | #define M860_BR_PS8 (1<<10) /* 8 bit port */ |
---|
| 705 | #define M860_BR_PS16 (2<<10) /* 16 bit port */ |
---|
| 706 | #define M860_BR_PS32 (0<<10) /* 32 bit port */ |
---|
| 707 | #define M860_BR_PARE (1<<9) /* Parity checking enable */ |
---|
| 708 | #define M860_BR_WP (1<<8) /* Write protect */ |
---|
| 709 | #define M860_BR_MS_GPCM (0<<6) /* GPCM */ |
---|
| 710 | #define M860_BR_MS_UPMA (2<<6) /* UPM A */ |
---|
| 711 | #define M860_BR_MS_UPMB (3<<6) /* UPM B */ |
---|
| 712 | #define M860_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
| 713 | |
---|
| 714 | #define M860_MEMC_OR_32K 0xffff8000 /* Address range */ |
---|
| 715 | #define M860_MEMC_OR_64K 0xffff0000 |
---|
| 716 | #define M860_MEMC_OR_128K 0xfffe0000 |
---|
| 717 | #define M860_MEMC_OR_256K 0xfffc0000 |
---|
| 718 | #define M860_MEMC_OR_512K 0xfff80000 |
---|
| 719 | #define M860_MEMC_OR_1M 0xfff00000 |
---|
| 720 | #define M860_MEMC_OR_2M 0xffe00000 |
---|
| 721 | #define M860_MEMC_OR_4M 0xffc00000 |
---|
| 722 | #define M860_MEMC_OR_8M 0xff800000 |
---|
| 723 | #define M860_MEMC_OR_16M 0xff000000 |
---|
| 724 | #define M860_MEMC_OR_32M 0xfe000000 |
---|
| 725 | #define M860_MEMC_OR_64M 0xfc000000 |
---|
| 726 | #define M860_MEMC_OR_128 0xf8000000 |
---|
| 727 | #define M860_MEMC_OR_256M 0xf0000000 |
---|
| 728 | #define M860_MEMC_OR_512M 0xe0000000 |
---|
| 729 | #define M860_MEMC_OR_1G 0xc0000000 |
---|
| 730 | #define M860_MEMC_OR_2G 0x80000000 |
---|
| 731 | #define M860_MEMC_OR_4G 0x00000000 |
---|
| 732 | #define M860_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ |
---|
| 733 | #define M860_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ |
---|
| 734 | #define M860_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ |
---|
| 735 | #define M860_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ |
---|
| 736 | #define M860_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ |
---|
| 737 | #define M860_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ |
---|
| 738 | #define M860_MEMC_OR_BI (1<8) /* Burst inhibit */ |
---|
| 739 | #define M860_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ |
---|
| 740 | #define M860_MEMC_OR_SETA (1<<3) /* *TA generated externally */ |
---|
| 741 | #define M860_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ |
---|
| 742 | #define M860_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ |
---|
| 743 | |
---|
| 744 | /* |
---|
| 745 | ************************************************************************* |
---|
| 746 | * UPM Registers (MxMR) * |
---|
| 747 | ************************************************************************* |
---|
| 748 | */ |
---|
| 749 | #define M860_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ |
---|
| 750 | #define M860_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ |
---|
| 751 | #define M860_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ |
---|
| 752 | #define M860_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ |
---|
| 753 | #define M860_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ |
---|
| 754 | #define M860_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ |
---|
| 755 | #define M860_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ |
---|
| 756 | #define M860_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ |
---|
| 757 | /* |
---|
| 758 | ************************************************************************* |
---|
| 759 | * Memory Command Register (MCR) * |
---|
| 760 | ************************************************************************* |
---|
| 761 | */ |
---|
| 762 | #define M860_MEMC_MCR_WRITE (0<<30) /* WRITE command */ |
---|
| 763 | #define M860_MEMC_MCR_READ (1<<30) /* READ command */ |
---|
| 764 | #define M860_MEMC_MCR_RUN (2<<30) /* RUN command */ |
---|
| 765 | #define M860_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ |
---|
| 766 | #define M860_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ |
---|
| 767 | #define M860_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ |
---|
| 768 | #define M860_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ |
---|
| 769 | #define M860_MEMC_MCR_MAD(x) (x) /* Machine address */ |
---|
| 770 | |
---|
| 771 | |
---|
| 772 | |
---|
| 773 | /* |
---|
| 774 | ************************************************************************* |
---|
| 775 | * SI Mode Register (SIMODE) * |
---|
| 776 | ************************************************************************* |
---|
| 777 | */ |
---|
| 778 | #define M860_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
---|
| 779 | #define M860_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
---|
| 780 | #define M860_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
---|
| 781 | #define M860_SI_SMC2_BRG2 (1<<28) |
---|
| 782 | #define M860_SI_SMC2_BRG3 (2<<28) |
---|
| 783 | #define M860_SI_SMC2_BRG4 (3<<28) |
---|
| 784 | #define M860_SI_SMC2_CLK5 (0<<28) |
---|
| 785 | #define M860_SI_SMC2_CLK6 (1<<28) |
---|
| 786 | #define M860_SI_SMC2_CLK7 (2<<28) |
---|
| 787 | #define M860_SI_SMC2_CLK8 (3<<28) |
---|
| 788 | #define M860_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
---|
| 789 | #define M860_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
---|
| 790 | #define M860_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
---|
| 791 | #define M860_SI_SMC1_BRG2 (1<<12) |
---|
| 792 | #define M860_SI_SMC1_BRG3 (2<<12) |
---|
| 793 | #define M860_SI_SMC1_BRG4 (3<<12) |
---|
| 794 | #define M860_SI_SMC1_CLK1 (0<<12) |
---|
| 795 | #define M860_SI_SMC1_CLK2 (1<<12) |
---|
| 796 | #define M860_SI_SMC1_CLK3 (2<<12) |
---|
| 797 | #define M860_SI_SMC1_CLK4 (3<<12) |
---|
| 798 | |
---|
| 799 | /* |
---|
| 800 | ************************************************************************* |
---|
| 801 | * SDMA Configuration Register (SDCR) * |
---|
| 802 | ************************************************************************* |
---|
| 803 | */ |
---|
| 804 | #define M860_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ |
---|
| 805 | #define M860_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ |
---|
| 806 | |
---|
| 807 | /* |
---|
| 808 | ************************************************************************* |
---|
| 809 | * SDMA Status Register (SDSR) * |
---|
| 810 | ************************************************************************* |
---|
| 811 | */ |
---|
| 812 | #define M860_SDSR_SBER (1<<7) /* SDMA Channel bus error */ |
---|
| 813 | #define M860_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ |
---|
| 814 | #define M860_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ |
---|
| 815 | |
---|
| 816 | /* |
---|
| 817 | ************************************************************************* |
---|
| 818 | * Baud (sic) Rate Generators * |
---|
| 819 | ************************************************************************* |
---|
| 820 | */ |
---|
| 821 | #define M860_BRG_RST (1<<17) /* Reset generator */ |
---|
| 822 | #define M860_BRG_EN (1<<16) /* Enable generator */ |
---|
| 823 | #define M860_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
---|
| 824 | #define M860_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
---|
| 825 | #define M860_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
---|
| 826 | #define M860_BRG_ATB (1<<13) /* Autobaud */ |
---|
| 827 | #define M860_BRG_115200 (21<<1) /* Assume 40 MHz clock */ |
---|
| 828 | #define M860_BRG_57600 (32<<1) |
---|
| 829 | #define M860_BRG_38400 (64<<1) |
---|
| 830 | #define M860_BRG_19200 (129<<1) |
---|
| 831 | #define M860_BRG_9600 (259<<1) |
---|
| 832 | #define M860_BRG_4800 (520<<1) |
---|
| 833 | #define M860_BRG_2400 (1040<<1) |
---|
| 834 | #define M860_BRG_1200 (2082<<1) |
---|
| 835 | #define M860_BRG_600 ((259<<1) | 1) |
---|
| 836 | #define M860_BRG_300 ((520<<1) | 1) |
---|
| 837 | #define M860_BRG_150 ((1040<<1) | 1) |
---|
| 838 | #define M860_BRG_75 ((2080<<1) | 1) |
---|
| 839 | |
---|
| 840 | #define M860_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ |
---|
| 841 | #define M860_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ |
---|
| 842 | #define M860_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ |
---|
| 843 | #define M860_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ |
---|
| 844 | #define M860_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ |
---|
| 845 | #define M860_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ |
---|
| 846 | #define M860_TGCR_STP1 (1<<1) /* Stop timer */ |
---|
| 847 | #define M860_TGCR_STP2 (1<<5) /* Stop timer */ |
---|
| 848 | #define M860_TGCR_STP3 (1<<9) /* Stop timer */ |
---|
| 849 | #define M860_TGCR_STP4 (1<<13) /* Stop timer */ |
---|
| 850 | #define M860_TGCR_RST1 (1<<0) /* Enable timer */ |
---|
| 851 | #define M860_TGCR_RST2 (1<<4) /* Enable timer */ |
---|
| 852 | #define M860_TGCR_RST3 (1<<8) /* Enable timer */ |
---|
| 853 | #define M860_TGCR_RST4 (1<<12) /* Enable timer */ |
---|
| 854 | #define M860_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ |
---|
| 855 | #define M860_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ |
---|
| 856 | |
---|
| 857 | #define M860_TMR_PS(x) ((x)<<8) /* Timer prescaler */ |
---|
| 858 | #define M860_TMR_CE_RISE (1<<6) /* Capture on rising edge */ |
---|
| 859 | #define M860_TMR_CE_FALL (2<<6) /* Capture on falling edge */ |
---|
| 860 | #define M860_TMR_CE_ANY (3<<6) /* Capture on any edge */ |
---|
| 861 | #define M860_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ |
---|
| 862 | #define M860_TMR_ORI (1<<4) /* Interrupt on reaching reference */ |
---|
| 863 | #define M860_TMR_RESTART (1<<3) /* Restart timer after reference */ |
---|
| 864 | #define M860_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ |
---|
| 865 | #define M860_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ |
---|
| 866 | #define M860_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ |
---|
| 867 | #define M860_TMR_TGATE (1<<0) /* TGATE controls timer */ |
---|
| 868 | |
---|
| 869 | #define M860_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ |
---|
| 870 | #define M860_PISCR_PS (1<<7) /* PIT Interrupt state */ |
---|
| 871 | #define M860_PISCR_PIE (1<<2) /* PIT interrupt enable */ |
---|
| 872 | #define M860_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ |
---|
| 873 | #define M860_PISCR_PTE (1<<0) /* PIT enable */ |
---|
| 874 | |
---|
| 875 | #define M860_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ |
---|
| 876 | #define M860_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ |
---|
| 877 | #define M860_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ |
---|
| 878 | #define M860_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ |
---|
| 879 | #define M860_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ |
---|
| 880 | #define M860_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ |
---|
| 881 | #define M860_TBSCR_TBE (1<<0) /* enable TB and decrementer */ |
---|
| 882 | |
---|
| 883 | #define M860_SIMASK_IRM0 (1<<31) |
---|
| 884 | #define M860_SIMASK_LVM0 (1<<30) |
---|
| 885 | #define M860_SIMASK_IRM1 (1<<29) |
---|
| 886 | #define M860_SIMASK_LVM1 (1<<28) |
---|
| 887 | #define M860_SIMASK_IRM2 (1<<27) |
---|
| 888 | #define M860_SIMASK_LVM2 (1<<26) |
---|
| 889 | #define M860_SIMASK_IRM3 (1<<25) |
---|
| 890 | #define M860_SIMASK_LVM3 (1<<24) |
---|
| 891 | #define M860_SIMASK_IRM4 (1<<23) |
---|
| 892 | #define M860_SIMASK_LVM4 (1<<22) |
---|
| 893 | #define M860_SIMASK_IRM5 (1<<21) |
---|
| 894 | #define M860_SIMASK_LVM5 (1<<20) |
---|
| 895 | #define M860_SIMASK_IRM6 (1<<19) |
---|
| 896 | #define M860_SIMASK_LVM6 (1<<18) |
---|
| 897 | #define M860_SIMASK_IRM7 (1<<17) |
---|
| 898 | #define M860_SIMASK_LVM7 (1<<16) |
---|
| 899 | |
---|
| 900 | #define M860_SIUMCR_EARB (1<<31) |
---|
| 901 | #define M860_SIUMCR_EARP0 (0<<28) |
---|
| 902 | #define M860_SIUMCR_EARP1 (1<<28) |
---|
| 903 | #define M860_SIUMCR_EARP2 (2<<28) |
---|
| 904 | #define M860_SIUMCR_EARP3 (3<<28) |
---|
| 905 | #define M860_SIUMCR_EARP4 (4<<28) |
---|
| 906 | #define M860_SIUMCR_EARP5 (5<<28) |
---|
| 907 | #define M860_SIUMCR_EARP6 (6<<28) |
---|
| 908 | #define M860_SIUMCR_EARP7 (7<<28) |
---|
| 909 | #define M860_SIUMCR_DSHW (1<<23) |
---|
| 910 | #define M860_SIUMCR_DBGC0 (0<<21) |
---|
| 911 | #define M860_SIUMCR_DBGC1 (1<<21) |
---|
| 912 | #define M860_SIUMCR_DBGC2 (2<<21) |
---|
| 913 | #define M860_SIUMCR_DBGC3 (3<<21) |
---|
| 914 | #define M860_SIUMCR_DBPC0 (0<<19) |
---|
| 915 | #define M860_SIUMCR_DBPC1 (1<<19) |
---|
| 916 | #define M860_SIUMCR_DBPC2 (2<<19) |
---|
| 917 | #define M860_SIUMCR_DBPC3 (3<<19) |
---|
| 918 | #define M860_SIUMCR_FRC (1<<17) |
---|
| 919 | #define M860_SIUMCR_DLK (1<<16) |
---|
| 920 | #define M860_SIUMCR_PNCS (1<<15) |
---|
| 921 | #define M860_SIUMCR_OPAR (1<<14) |
---|
| 922 | #define M860_SIUMCR_DPC (1<<13) |
---|
| 923 | #define M860_SIUMCR_MPRE (1<<12) |
---|
| 924 | #define M860_SIUMCR_MLRC0 (0<<10) |
---|
| 925 | #define M860_SIUMCR_MLRC1 (1<<10) |
---|
| 926 | #define M860_SIUMCR_MLRC2 (2<<10) |
---|
| 927 | #define M860_SIUMCR_MLRC3 (3<<10) |
---|
| 928 | #define M860_SIUMCR_AEME (1<<9) |
---|
| 929 | #define M860_SIUMCR_SEME (1<<8) |
---|
| 930 | #define M860_SIUMCR_BSC (1<<7) |
---|
| 931 | #define M860_SIUMCR_GB5E (1<<6) |
---|
| 932 | #define M860_SIUMCR_B2DD (1<<5) |
---|
| 933 | #define M860_SIUMCR_B3DD (1<<4) |
---|
| 934 | /* |
---|
| 935 | ************************************************************************* |
---|
| 936 | * MPC860 DUAL-PORT RAM AND REGISTERS * |
---|
| 937 | ************************************************************************* |
---|
| 938 | */ |
---|
| 939 | typedef struct m860_ { |
---|
| 940 | |
---|
| 941 | /* |
---|
| 942 | * SIU Block |
---|
| 943 | */ |
---|
| 944 | rtems_unsigned32 siumcr; |
---|
| 945 | rtems_unsigned32 sypcr; |
---|
| 946 | rtems_unsigned32 swt; |
---|
| 947 | rtems_unsigned16 _pad0; |
---|
| 948 | rtems_unsigned16 swsr; |
---|
| 949 | rtems_unsigned32 sipend; |
---|
| 950 | rtems_unsigned32 simask; |
---|
| 951 | rtems_unsigned32 siel; |
---|
| 952 | rtems_unsigned32 sivec; |
---|
| 953 | rtems_unsigned32 tesr; |
---|
| 954 | rtems_unsigned32 _pad1[3]; |
---|
| 955 | rtems_unsigned32 sdcr; |
---|
| 956 | rtems_unsigned8 _pad2[0x80-0x34]; |
---|
| 957 | |
---|
| 958 | /* |
---|
| 959 | * PCMCIA Block |
---|
| 960 | */ |
---|
| 961 | rtems_unsigned32 pbr0; |
---|
| 962 | rtems_unsigned32 por0; |
---|
| 963 | rtems_unsigned32 pbr1; |
---|
| 964 | rtems_unsigned32 por1; |
---|
| 965 | rtems_unsigned32 pbr2; |
---|
| 966 | rtems_unsigned32 por2; |
---|
| 967 | rtems_unsigned32 pbr3; |
---|
| 968 | rtems_unsigned32 por3; |
---|
| 969 | rtems_unsigned32 pbr4; |
---|
| 970 | rtems_unsigned32 por4; |
---|
| 971 | rtems_unsigned32 pbr5; |
---|
| 972 | rtems_unsigned32 por5; |
---|
| 973 | rtems_unsigned32 pbr6; |
---|
| 974 | rtems_unsigned32 por6; |
---|
| 975 | rtems_unsigned32 pbr7; |
---|
| 976 | rtems_unsigned32 por7; |
---|
| 977 | rtems_unsigned8 _pad3[0xe0-0xc0]; |
---|
| 978 | rtems_unsigned32 pgcra; |
---|
| 979 | rtems_unsigned32 pgcrb; |
---|
| 980 | rtems_unsigned32 pscr; |
---|
| 981 | rtems_unsigned32 _pad4; |
---|
| 982 | rtems_unsigned32 pipr; |
---|
| 983 | rtems_unsigned32 _pad5; |
---|
| 984 | rtems_unsigned32 per; |
---|
| 985 | rtems_unsigned32 _pad6; |
---|
| 986 | |
---|
| 987 | /* |
---|
| 988 | * MEMC Block |
---|
| 989 | */ |
---|
| 990 | m860MEMCRegisters_t memc[8]; |
---|
| 991 | rtems_unsigned8 _pad7[0x164-0x140]; |
---|
| 992 | rtems_unsigned32 mar; |
---|
| 993 | rtems_unsigned32 mcr; |
---|
| 994 | rtems_unsigned32 _pad8; |
---|
| 995 | rtems_unsigned32 mamr; |
---|
| 996 | rtems_unsigned32 mbmr; |
---|
| 997 | rtems_unsigned16 mstat; |
---|
| 998 | rtems_unsigned16 mptpr; |
---|
| 999 | rtems_unsigned32 mdr; |
---|
| 1000 | rtems_unsigned8 _pad9[0x200-0x180]; |
---|
| 1001 | |
---|
| 1002 | /* |
---|
| 1003 | * System integration timers |
---|
| 1004 | */ |
---|
| 1005 | rtems_unsigned16 tbscr; |
---|
| 1006 | rtems_unsigned16 _pad10; |
---|
| 1007 | rtems_unsigned32 tbreff0; |
---|
| 1008 | rtems_unsigned32 tbreff1; |
---|
| 1009 | rtems_unsigned8 _pad11[0x220-0x20c]; |
---|
| 1010 | rtems_unsigned16 rtcsc; |
---|
| 1011 | rtems_unsigned16 _pad12; |
---|
| 1012 | rtems_unsigned32 rtc; |
---|
| 1013 | rtems_unsigned32 rtsec; |
---|
| 1014 | rtems_unsigned32 rtcal; |
---|
| 1015 | rtems_unsigned32 _pad13[4]; |
---|
| 1016 | rtems_unsigned16 piscr; |
---|
| 1017 | rtems_unsigned16 _pad14; |
---|
| 1018 | rtems_unsigned16 pitc; |
---|
| 1019 | rtems_unsigned16 _pad_14_1; |
---|
| 1020 | rtems_unsigned16 pitr; |
---|
| 1021 | rtems_unsigned16 _pad_14_2; |
---|
| 1022 | rtems_unsigned8 _pad15[0x280-0x24c]; |
---|
| 1023 | |
---|
| 1024 | |
---|
| 1025 | /* |
---|
| 1026 | * Clocks and Reset |
---|
| 1027 | */ |
---|
| 1028 | rtems_unsigned32 sccr; |
---|
| 1029 | rtems_unsigned32 plprcr; |
---|
| 1030 | rtems_unsigned32 rsr; |
---|
| 1031 | rtems_unsigned8 _pad16[0x300-0x28c]; |
---|
| 1032 | |
---|
| 1033 | |
---|
| 1034 | /* |
---|
| 1035 | * System integration timers keys |
---|
| 1036 | */ |
---|
| 1037 | rtems_unsigned32 tbscrk; |
---|
| 1038 | rtems_unsigned32 tbreff0k; |
---|
| 1039 | rtems_unsigned32 tbreff1k; |
---|
| 1040 | rtems_unsigned32 tbk; |
---|
| 1041 | rtems_unsigned32 _pad17[4]; |
---|
| 1042 | rtems_unsigned32 rtcsk; |
---|
| 1043 | rtems_unsigned32 rtck; |
---|
| 1044 | rtems_unsigned32 rtseck; |
---|
| 1045 | rtems_unsigned32 rtcalk; |
---|
| 1046 | rtems_unsigned32 _pad18[4]; |
---|
| 1047 | rtems_unsigned32 piscrk; |
---|
| 1048 | rtems_unsigned32 pitck; |
---|
| 1049 | rtems_unsigned8 _pad19[0x380-0x348]; |
---|
| 1050 | |
---|
| 1051 | /* |
---|
| 1052 | * Clocks and Reset Keys |
---|
| 1053 | */ |
---|
| 1054 | rtems_unsigned32 sccrk; |
---|
| 1055 | rtems_unsigned32 plprck; |
---|
| 1056 | rtems_unsigned32 rsrk; |
---|
| 1057 | rtems_unsigned8 _pad20[0x400-0x38c]; |
---|
| 1058 | rtems_unsigned8 _pad21[0x800-0x400]; |
---|
| 1059 | rtems_unsigned8 _pad22[0x860-0x800]; |
---|
| 1060 | |
---|
| 1061 | |
---|
| 1062 | /* |
---|
| 1063 | * I2C |
---|
| 1064 | */ |
---|
| 1065 | rtems_unsigned8 i2mod; |
---|
| 1066 | rtems_unsigned8 _pad23[3]; |
---|
| 1067 | rtems_unsigned8 i2add; |
---|
| 1068 | rtems_unsigned8 _pad24[3]; |
---|
| 1069 | rtems_unsigned8 i2brg; |
---|
| 1070 | rtems_unsigned8 _pad25[3]; |
---|
| 1071 | rtems_unsigned8 i2com; |
---|
| 1072 | rtems_unsigned8 _pad26[3]; |
---|
| 1073 | rtems_unsigned8 i2cer; |
---|
| 1074 | rtems_unsigned8 _pad27[3]; |
---|
| 1075 | rtems_unsigned8 i2cmr; |
---|
| 1076 | rtems_unsigned8 _pad28[0x900-0x875]; |
---|
| 1077 | |
---|
| 1078 | /* |
---|
| 1079 | * DMA Block |
---|
| 1080 | */ |
---|
| 1081 | rtems_unsigned32 _pad29; |
---|
| 1082 | rtems_unsigned32 sdar; |
---|
| 1083 | rtems_unsigned8 sdsr; |
---|
| 1084 | rtems_unsigned8 _pad30[3]; |
---|
| 1085 | rtems_unsigned8 sdmr; |
---|
| 1086 | rtems_unsigned8 _pad31[3]; |
---|
| 1087 | rtems_unsigned8 idsr1; |
---|
| 1088 | rtems_unsigned8 _pad32[3]; |
---|
| 1089 | rtems_unsigned8 idmr1; |
---|
| 1090 | rtems_unsigned8 _pad33[3]; |
---|
| 1091 | rtems_unsigned8 idsr2; |
---|
| 1092 | rtems_unsigned8 _pad34[3]; |
---|
| 1093 | rtems_unsigned8 idmr2; |
---|
| 1094 | rtems_unsigned8 _pad35[0x930-0x91d]; |
---|
| 1095 | |
---|
| 1096 | |
---|
| 1097 | |
---|
| 1098 | /* |
---|
| 1099 | * CPM Interrupt Control Block |
---|
| 1100 | */ |
---|
| 1101 | rtems_unsigned16 civr; |
---|
| 1102 | rtems_unsigned8 _pad36[14]; |
---|
| 1103 | rtems_unsigned32 cicr; |
---|
| 1104 | rtems_unsigned32 cipr; |
---|
| 1105 | rtems_unsigned32 cimr; |
---|
| 1106 | rtems_unsigned32 cisr; |
---|
| 1107 | |
---|
| 1108 | /* |
---|
| 1109 | * I/O Port Block |
---|
| 1110 | */ |
---|
| 1111 | rtems_unsigned16 padir; |
---|
| 1112 | rtems_unsigned16 papar; |
---|
| 1113 | rtems_unsigned16 paodr; |
---|
| 1114 | rtems_unsigned16 padat; |
---|
| 1115 | rtems_unsigned8 _pad37[8]; |
---|
| 1116 | rtems_unsigned16 pcdir; |
---|
| 1117 | rtems_unsigned16 pcpar; |
---|
| 1118 | rtems_unsigned16 pcso; |
---|
| 1119 | rtems_unsigned16 pcdat; |
---|
| 1120 | rtems_unsigned16 pcint; |
---|
| 1121 | rtems_unsigned8 _pad39[6]; |
---|
| 1122 | rtems_unsigned16 pddir; |
---|
| 1123 | rtems_unsigned16 pdpar; |
---|
| 1124 | rtems_unsigned16 _pad40; |
---|
| 1125 | rtems_unsigned16 pddat; |
---|
| 1126 | rtems_unsigned8 _pad41[8]; |
---|
| 1127 | |
---|
| 1128 | /* |
---|
| 1129 | * CPM Timers Block |
---|
| 1130 | */ |
---|
| 1131 | rtems_unsigned16 tgcr; |
---|
| 1132 | rtems_unsigned8 _pad42[14]; |
---|
| 1133 | rtems_unsigned16 tmr1; |
---|
| 1134 | rtems_unsigned16 tmr2; |
---|
| 1135 | rtems_unsigned16 trr1; |
---|
| 1136 | rtems_unsigned16 trr2; |
---|
| 1137 | rtems_unsigned16 tcr1; |
---|
| 1138 | rtems_unsigned16 tcr2; |
---|
| 1139 | rtems_unsigned16 tcn1; |
---|
| 1140 | rtems_unsigned16 tcn2; |
---|
| 1141 | rtems_unsigned16 tmr3; |
---|
| 1142 | rtems_unsigned16 tmr4; |
---|
| 1143 | rtems_unsigned16 trr3; |
---|
| 1144 | rtems_unsigned16 trr4; |
---|
| 1145 | rtems_unsigned16 tcr3; |
---|
| 1146 | rtems_unsigned16 tcr4; |
---|
| 1147 | rtems_unsigned16 tcn3; |
---|
| 1148 | rtems_unsigned16 tcn4; |
---|
| 1149 | rtems_unsigned16 ter1; |
---|
| 1150 | rtems_unsigned16 ter2; |
---|
| 1151 | rtems_unsigned16 ter3; |
---|
| 1152 | rtems_unsigned16 ter4; |
---|
| 1153 | rtems_unsigned8 _pad43[8]; |
---|
| 1154 | |
---|
| 1155 | |
---|
| 1156 | |
---|
| 1157 | /* |
---|
| 1158 | * CPM Block |
---|
| 1159 | */ |
---|
| 1160 | rtems_unsigned16 cpcr; |
---|
| 1161 | rtems_unsigned16 _pad44; |
---|
| 1162 | rtems_unsigned16 rccr; |
---|
| 1163 | rtems_unsigned8 _pad45; |
---|
| 1164 | rtems_unsigned8 rmds; |
---|
| 1165 | rtems_unsigned32 rmdr; |
---|
| 1166 | rtems_unsigned16 rctr1; |
---|
| 1167 | rtems_unsigned16 rctr2; |
---|
| 1168 | rtems_unsigned16 rctr3; |
---|
| 1169 | rtems_unsigned16 rctr4; |
---|
| 1170 | rtems_unsigned16 _pad46; |
---|
| 1171 | rtems_unsigned16 rter; |
---|
| 1172 | rtems_unsigned16 _pad47; |
---|
| 1173 | rtems_unsigned16 rtmr; |
---|
| 1174 | rtems_unsigned8 _pad48[0x9f0-0x9dc]; |
---|
| 1175 | |
---|
| 1176 | /* |
---|
| 1177 | * BRG Block |
---|
| 1178 | */ |
---|
| 1179 | rtems_unsigned32 brgc1; |
---|
| 1180 | rtems_unsigned32 brgc2; |
---|
| 1181 | rtems_unsigned32 brgc3; |
---|
| 1182 | rtems_unsigned32 brgc4; |
---|
| 1183 | |
---|
| 1184 | /* |
---|
| 1185 | * SCC Block |
---|
| 1186 | */ |
---|
| 1187 | m860SCCRegisters_t scc1; |
---|
| 1188 | m860SCCRegisters_t scc2; |
---|
| 1189 | m860SCCRegisters_t scc3; |
---|
| 1190 | m860SCCRegisters_t scc4; |
---|
| 1191 | |
---|
| 1192 | /* |
---|
| 1193 | * SMC Block |
---|
| 1194 | */ |
---|
| 1195 | m860SMCRegisters_t smc1; |
---|
| 1196 | m860SMCRegisters_t smc2; |
---|
| 1197 | |
---|
| 1198 | /* |
---|
| 1199 | * SPI Block |
---|
| 1200 | */ |
---|
| 1201 | rtems_unsigned16 spmode; |
---|
| 1202 | rtems_unsigned16 _pad49[2]; |
---|
| 1203 | rtems_unsigned8 spie; |
---|
| 1204 | rtems_unsigned8 _pad50; |
---|
| 1205 | rtems_unsigned16 _pad51; |
---|
| 1206 | rtems_unsigned8 spim; |
---|
| 1207 | rtems_unsigned8 _pad52[2]; |
---|
| 1208 | rtems_unsigned8 spcom; |
---|
| 1209 | rtems_unsigned16 _pad53[2]; |
---|
| 1210 | |
---|
| 1211 | /* |
---|
| 1212 | * PIP Block |
---|
| 1213 | */ |
---|
| 1214 | rtems_unsigned16 pipc; |
---|
| 1215 | rtems_unsigned16 _pad54; |
---|
| 1216 | rtems_unsigned16 ptpr; |
---|
| 1217 | rtems_unsigned32 pbdir; |
---|
| 1218 | rtems_unsigned32 pbpar; |
---|
| 1219 | rtems_unsigned16 _pad55; |
---|
| 1220 | rtems_unsigned16 pbodr; |
---|
| 1221 | rtems_unsigned32 pbdat; |
---|
| 1222 | rtems_unsigned32 _pad56[6]; |
---|
| 1223 | |
---|
| 1224 | /* |
---|
| 1225 | * SI Block |
---|
| 1226 | */ |
---|
| 1227 | rtems_unsigned32 simode; |
---|
| 1228 | rtems_unsigned8 sigmr; |
---|
| 1229 | rtems_unsigned8 _pad57; |
---|
| 1230 | rtems_unsigned8 sistr; |
---|
| 1231 | rtems_unsigned8 sicmr; |
---|
| 1232 | rtems_unsigned32 _pad58; |
---|
| 1233 | rtems_unsigned32 sicr; |
---|
| 1234 | rtems_unsigned16 sirp[2]; |
---|
| 1235 | rtems_unsigned32 _pad59[3]; |
---|
| 1236 | rtems_unsigned8 _pad60[0xc00-0xb00]; |
---|
| 1237 | rtems_unsigned8 siram[512]; |
---|
| 1238 | |
---|
| 1239 | /* |
---|
| 1240 | * This is only used on the MPC860T - for the Fast Ethernet Controller (FEC) |
---|
| 1241 | */ |
---|
| 1242 | m860FECRegisters_t fec; |
---|
| 1243 | |
---|
| 1244 | rtems_unsigned8 _pad62[0x2000-0x1000]; |
---|
| 1245 | /* |
---|
| 1246 | * Dual-port RAM |
---|
| 1247 | */ |
---|
| 1248 | rtems_unsigned8 dpram0[0x200]; /* BD/DATA/UCODE */ |
---|
| 1249 | rtems_unsigned8 dpram1[0x200]; /* BD/DATA/UCODE */ |
---|
| 1250 | rtems_unsigned8 dpram2[0x400]; /* BD/DATA/UCODE */ |
---|
| 1251 | rtems_unsigned8 dpram3[0x600]; /* BD/DATA*/ |
---|
| 1252 | rtems_unsigned8 dpram4[0x200]; /* BD/DATA/UCODE */ |
---|
| 1253 | rtems_unsigned8 _pad63[0x3c00-0x3000]; |
---|
| 1254 | |
---|
| 1255 | /* When using SCC1 for ethernet, we lose the use of I2C since |
---|
| 1256 | * their parameters would overlap. Motorola has a microcode |
---|
| 1257 | * patch to move parameters around so that both can be used |
---|
| 1258 | * together. It is available on their web site somewhere |
---|
| 1259 | * under http://www.mot.com/mpc860. If ethernet is used on |
---|
| 1260 | * one (or more) of the other SCCs, then other CPM features |
---|
| 1261 | * will be unavailable: |
---|
| 1262 | * SCC2 -> lose SPI |
---|
| 1263 | * SCC3 -> lose SMC1 |
---|
| 1264 | * SCC4 -> lose SMC2 |
---|
| 1265 | */ |
---|
| 1266 | m860SCCENparms_t scc1p; |
---|
| 1267 | rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m860SCCENparms_t)]; |
---|
| 1268 | m860MiscParms_t miscp; |
---|
| 1269 | rtems_unsigned8 _rsv2[0xcc0-0xCB0-sizeof(m860MiscParms_t)]; |
---|
| 1270 | m860IDMAparms_t idma1p; |
---|
| 1271 | rtems_unsigned8 _rsv3[0xd00-0xcc0-sizeof(m860IDMAparms_t)]; |
---|
| 1272 | |
---|
| 1273 | m860SCCparms_t scc2p; |
---|
| 1274 | rtems_unsigned8 _rsv4[0xD80-0xD00-sizeof(m860SCCparms_t)]; |
---|
| 1275 | m860SPIparms_t spip; |
---|
| 1276 | rtems_unsigned8 _rsv5[0xDB0-0xD80-sizeof(m860SPIparms_t)]; |
---|
| 1277 | m860TimerParms_t tmp; |
---|
| 1278 | rtems_unsigned8 _rsv6[0xDC0-0xDB0-sizeof(m860TimerParms_t)]; |
---|
| 1279 | m860IDMAparms_t idma2p; |
---|
| 1280 | rtems_unsigned8 _rsv7[0xE00-0xDC0-sizeof(m860IDMAparms_t)]; |
---|
| 1281 | |
---|
| 1282 | m860SCCparms_t scc3p; |
---|
| 1283 | rtems_unsigned8 _rsv8[0xE80-0xE00-sizeof(m860SCCparms_t)]; |
---|
| 1284 | m860SMCparms_t smc1p; |
---|
| 1285 | rtems_unsigned8 _rsv9[0xEC0-0xE80-sizeof(m860SMCparms_t)]; |
---|
| 1286 | m860DSPparms_t dsp1p; |
---|
| 1287 | rtems_unsigned8 _rsv10[0xF00-0xEC0-sizeof(m860DSPparms_t)]; |
---|
| 1288 | |
---|
| 1289 | m860SCCparms_t scc4p; |
---|
| 1290 | rtems_unsigned8 _rsv11[0xF80-0xF00-sizeof(m860SCCparms_t)]; |
---|
| 1291 | m860SMCparms_t smc2p; |
---|
| 1292 | rtems_unsigned8 _rsv12[0xFC0-0xF80-sizeof(m860SMCparms_t)]; |
---|
| 1293 | m860DSPparms_t dsp2p; |
---|
| 1294 | rtems_unsigned8 _rsv13[0x1000-0xFC0-sizeof(m860DSPparms_t)]; |
---|
| 1295 | } m860_t; |
---|
| 1296 | |
---|
| 1297 | extern volatile m860_t m860; |
---|
| 1298 | #endif /* ASM */ |
---|
| 1299 | |
---|
| 1300 | #endif /* __MPC860_h */ |
---|