1 | /* |
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2 | * General Serial I/O functions. |
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3 | * |
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4 | * This file contains the functions for performing serial I/O. |
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5 | * The actual system calls (console_*) should be in the BSP part |
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6 | * of the source tree. That way different BSPs can use whichever |
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7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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8 | * this file, and it caused problems with one BSP using SCC2 |
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9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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10 | * |
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11 | * On-chip resources used: |
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12 | * resource minor note |
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13 | * SMC1 0 |
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14 | * SMC2 1 |
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15 | * SCC1 2 (shared with ethernet driver) |
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16 | * SCC2 3 |
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17 | * SCC3 4 |
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18 | * SCC4 5 |
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19 | * BRG1 |
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20 | * BRG2 |
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21 | * BRG3 |
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22 | * BRG4 |
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23 | * Author: Jay Monkman (jmonkman@frasca.com) |
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24 | * Copyright (C) 1998 by Frasca International, Inc. |
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25 | * |
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26 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: |
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27 | * |
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28 | * Author: |
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29 | * W. Eric Norum |
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30 | * Saskatchewan Accelerator Laboratory |
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31 | * University of Saskatchewan |
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32 | * Saskatoon, Saskatchewan, CANADA |
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33 | * eric@skatter.usask.ca |
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34 | * |
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35 | * COPYRIGHT (c) 1989-1998. |
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36 | * On-Line Applications Research Corporation (OAR). |
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37 | * Copyright assigned to U.S. Government, 1994. |
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38 | * |
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39 | * The license and distribution terms for this file may be |
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40 | * found in the file LICENSE in this distribution or at |
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41 | * |
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42 | * http://www.OARcorp.com/rtems/license.html. |
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43 | * |
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44 | * $Id$ |
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45 | */ |
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46 | |
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47 | #include <bsp.h> |
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48 | #include <rtems/libio.h> |
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49 | #include <mpc860.h> |
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50 | #include <mpc860/console.h> |
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51 | #include <stdlib.h> |
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52 | #include <unistd.h> |
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53 | #include <termios.h> |
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54 | |
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55 | #define NIFACES 6 /* number of console devices (serial ports) */ |
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56 | |
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57 | extern rtems_cpu_table Cpu_table; /* owned by BSP */ |
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58 | |
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59 | static Buf_t *rxBufList[NIFACES]; |
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60 | static Buf_t *rxBufListTail[NIFACES]; |
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61 | |
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62 | /* |
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63 | * Interrupt-driven input buffer |
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64 | */ |
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65 | #define RXBUFSIZE 16 |
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66 | |
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67 | |
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68 | /* |
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69 | * I/O buffers and pointers to buffer descriptors |
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70 | */ |
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71 | static volatile char txBuf[NIFACES]; |
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72 | |
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73 | static volatile m860BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; |
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74 | |
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75 | /* |
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76 | * Device-specific routines |
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77 | */ |
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78 | static int m860_get_brg_cd(int); |
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79 | unsigned char m860_get_brg_clk(int); |
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80 | void m860_console_reserve_resources(rtems_configuration_table *); |
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81 | unsigned char m860_get_brg_clk(int); |
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82 | |
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83 | |
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84 | /* |
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85 | * Compute baud-rate-generator configuration register value |
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86 | */ |
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87 | static int |
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88 | m860_get_brg_cd (int baud) |
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89 | { |
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90 | int divisor; |
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91 | int div16 = 0; |
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92 | |
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93 | divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud; |
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94 | if (divisor > 4096) { |
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95 | div16 = 1; |
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96 | divisor = (divisor + 8) / 16; |
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97 | } |
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98 | return M860_BRG_EN | M860_BRG_EXTC_BRGCLK | |
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99 | ((divisor - 1) << 1) | div16; |
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100 | } |
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101 | |
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102 | |
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103 | /* this function will fail if more that 4 baud rates have been selected */ |
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104 | /* at any time since the OS started. It needs to be fixed. FIXME */ |
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105 | unsigned char m860_get_brg_clk(int baud) |
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106 | { |
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107 | static short brg_spd[4]; |
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108 | static char brg_used[4]; |
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109 | int i; |
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110 | |
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111 | /* first try to find a BRG that is already at the right speed */ |
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112 | for (i=0; i<4; i++) { |
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113 | if (brg_spd[i] == baud) { |
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114 | break; |
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115 | } |
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116 | } |
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117 | |
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118 | if (i==4) { /* I guess we didn't find one */ |
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119 | for (i=0; i<4; i++) { |
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120 | if (brg_used[i] == 0) { |
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121 | break; |
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122 | } |
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123 | } |
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124 | } |
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125 | if (i != 4) { |
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126 | brg_used[i]++; |
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127 | brg_spd[i]=baud; |
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128 | switch (i) { |
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129 | case 0: |
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130 | m860.brgc1 = M860_BRG_RST; |
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131 | m860.brgc1 = m860_get_brg_cd(baud); |
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132 | break; |
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133 | case 1: |
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134 | m860.brgc2 = M860_BRG_RST; |
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135 | m860.brgc2 = m860_get_brg_cd(baud); |
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136 | break; |
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137 | case 2: |
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138 | m860.brgc3 = M860_BRG_RST; |
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139 | m860.brgc3 = m860_get_brg_cd(baud); |
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140 | break; |
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141 | case 3: |
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142 | m860.brgc4 = M860_BRG_RST; |
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143 | m860.brgc4 = m860_get_brg_cd(baud); |
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144 | break; |
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145 | } |
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146 | return i; |
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147 | } |
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148 | |
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149 | else |
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150 | return 0xff; |
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151 | } |
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152 | |
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153 | /* |
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154 | * Hardware-dependent portion of tcsetattr(). |
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155 | */ |
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156 | int |
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157 | m860_smc_set_attributes (int minor, const struct termios *t) |
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158 | { |
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159 | /* |
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160 | * minor must be 0 or 1 |
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161 | */ |
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162 | int baud; |
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163 | int brg; |
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164 | switch (t->c_cflag & CBAUD) { |
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165 | default: baud = -1; break; |
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166 | case B50: baud = 50; break; |
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167 | case B75: baud = 75; break; |
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168 | case B110: baud = 110; break; |
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169 | case B134: baud = 134; break; |
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170 | case B150: baud = 150; break; |
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171 | case B200: baud = 200; break; |
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172 | case B300: baud = 300; break; |
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173 | case B600: baud = 600; break; |
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174 | case B1200: baud = 1200; break; |
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175 | case B1800: baud = 1800; break; |
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176 | case B2400: baud = 2400; break; |
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177 | case B4800: baud = 4800; break; |
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178 | case B9600: baud = 9600; break; |
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179 | case B19200: baud = 19200; break; |
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180 | case B38400: baud = 38400; break; |
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181 | case B57600: baud = 57600; break; |
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182 | case B115200: baud = 115200; break; |
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183 | case B230400: baud = 230400; break; |
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184 | case B460800: baud = 460800; break; |
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185 | } |
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186 | if (baud > 0) { |
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187 | brg = m860_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ |
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188 | /* at least 2 ports will be the same */ |
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189 | m860.simode |= brg << (12 + ((minor) * 16)); |
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190 | } |
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191 | return 0; |
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192 | } |
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193 | |
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194 | int |
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195 | m860_scc_set_attributes (int minor, const struct termios *t) |
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196 | { |
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197 | /* |
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198 | * minor must be 2, 3, 4 or 5 |
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199 | */ |
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200 | int baud; |
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201 | int brg; |
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202 | switch (t->c_cflag & CBAUD) { |
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203 | default: baud = -1; break; |
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204 | case B50: baud = 50; break; |
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205 | case B75: baud = 75; break; |
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206 | case B110: baud = 110; break; |
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207 | case B134: baud = 134; break; |
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208 | case B150: baud = 150; break; |
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209 | case B200: baud = 200; break; |
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210 | case B300: baud = 300; break; |
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211 | case B600: baud = 600; break; |
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212 | case B1200: baud = 1200; break; |
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213 | case B1800: baud = 1800; break; |
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214 | case B2400: baud = 2400; break; |
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215 | case B4800: baud = 4800; break; |
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216 | case B9600: baud = 9600; break; |
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217 | case B19200: baud = 19200; break; |
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218 | case B38400: baud = 38400; break; |
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219 | case B57600: baud = 57600; break; |
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220 | case B115200: baud = 115200; break; |
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221 | case B230400: baud = 230400; break; |
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222 | case B460800: baud = 460800; break; |
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223 | } |
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224 | if (baud > 0) { |
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225 | brg = m860_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ |
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226 | /* at least 2 ports will be the same */ |
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227 | m860.sicr |= (brg << (3 + ((minor-2) * 8))) | |
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228 | (brg << ((minor-2) * 8)); |
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229 | } |
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230 | return 0; |
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231 | } |
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232 | |
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233 | void |
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234 | m860_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ |
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235 | { |
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236 | unsigned char brg; |
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237 | volatile m860SCCparms_t *sccparms; |
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238 | volatile m860SCCRegisters_t *sccregs; |
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239 | |
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240 | /* |
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241 | * Allocate buffer descriptors |
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242 | */ |
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243 | RxBd[port+1] = M860AllocateBufferDescriptors(1); |
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244 | TxBd[port+1] = M860AllocateBufferDescriptors(1); |
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245 | |
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246 | /* |
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247 | * Configure ports A and B to enable TXDx and RXDx pins |
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248 | */ |
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249 | m860.papar |= (0xC << ((port-2) * 2)); |
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250 | m860.padir &= ~(0xC << ((port-2) * 2)); |
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251 | m860.pbdir |= (0x04 << (port-2)); |
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252 | m860.paodr &= ~(0x8 << ((port-2) * 2)); |
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253 | m860.pbdat &= ~(0x04 << (port-2)); |
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254 | |
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255 | /* SCC2 is the only one with handshaking lines */ |
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256 | /* |
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257 | if (port == 2) { |
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258 | m860.pcpar |= (0x02); |
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259 | m860.pcpar &= ~(0xc0); |
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260 | m860.pcdir &= ~(0xc2); |
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261 | m860.pcso |= (0xc0); |
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262 | } |
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263 | */ |
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264 | |
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265 | brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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266 | /* at least 2 ports will be the same */ |
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267 | |
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268 | /* |
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269 | * Set up SDMA |
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270 | */ |
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271 | m860.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC860UM/AD */ |
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272 | |
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273 | |
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274 | m860.sicr &= ~(0xff << ((port-1) * 8)); |
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275 | m860.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); |
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276 | |
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277 | /* |
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278 | * Set up SMC1 parameter RAM common to all protocols |
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279 | */ |
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280 | if (port == 1) { |
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281 | sccparms = (m860SCCparms_t*)&m860.scc1p; |
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282 | sccregs = &m860.scc1; |
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283 | } |
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284 | else if (port == 2) { |
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285 | sccparms = &m860.scc2p; |
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286 | sccregs = &m860.scc2; |
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287 | } |
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288 | else if (port == 3) { |
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289 | sccparms = &m860.scc3p; |
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290 | sccregs = &m860.scc3; |
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291 | } |
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292 | else { |
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293 | sccparms = &m860.scc4p; |
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294 | sccregs = &m860.scc4; |
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295 | } |
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296 | |
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297 | sccparms->rbase = (char *)RxBd[port+1] - (char *)&m860; |
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298 | sccparms->tbase = (char *)TxBd[port+1] - (char *)&m860; |
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299 | |
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300 | if (port == 1) |
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301 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1); |
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302 | else if (port == 2) |
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303 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC2); |
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304 | else if (port == 3) |
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305 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC3); |
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306 | else if (port == 4) |
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307 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC4); |
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308 | |
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309 | sccparms->rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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310 | sccparms->tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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311 | sccparms->mrblr = RXBUFSIZE; |
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312 | |
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313 | sccparms->un.uart.max_idl = 10; |
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314 | sccparms->un.uart.brklen = 0; |
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315 | sccparms->un.uart.brkec = 0; |
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316 | sccparms->un.uart.brkcr = 1; |
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317 | |
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318 | sccparms->un.uart.parec = 0; |
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319 | sccparms->un.uart.frmec = 0; |
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320 | sccparms->un.uart.nosec = 0; |
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321 | |
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322 | sccparms->un.uart.uaddr[0] = 0; |
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323 | sccparms->un.uart.uaddr[1] = 0; |
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324 | sccparms->un.uart.toseq = 0; |
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325 | |
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326 | sccparms->un.uart.character[0] = 0x8000; |
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327 | sccparms->un.uart.character[1] = 0x8000; |
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328 | sccparms->un.uart.character[2] = 0x8000; |
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329 | sccparms->un.uart.character[3] = 0x8000; |
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330 | sccparms->un.uart.character[4] = 0x8000; |
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331 | sccparms->un.uart.character[5] = 0x8000; |
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332 | sccparms->un.uart.character[6] = 0x8000; |
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333 | sccparms->un.uart.character[7] = 0x8000; |
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334 | |
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335 | sccparms->un.uart.rccm = 0xc0ff; |
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336 | |
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337 | /* |
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338 | * Set up the Receive Buffer Descriptor |
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339 | */ |
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340 | RxBd[port+1]->status = M860_BD_EMPTY | M860_BD_WRAP | |
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341 | M860_BD_INTERRUPT; |
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342 | RxBd[port+1]->length = 0; |
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343 | RxBd[port+1]->buffer = malloc(RXBUFSIZE); |
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344 | |
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345 | /* |
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346 | * Setup the Transmit Buffer Descriptor |
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347 | */ |
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348 | TxBd[port+1]->status = M860_BD_WRAP; |
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349 | |
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350 | /* |
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351 | * Set up SCCx general and protocol-specific mode registers |
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352 | */ |
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353 | sccregs->scce = 0xffff; |
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354 | sccregs->sccm = 0x0000; |
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355 | sccregs->gsmr_h = 0x00000020; |
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356 | sccregs->gsmr_l = 0x00028004; |
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357 | sccregs->psmr = 0x3000; |
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358 | sccregs->gsmr_l = 0x00028034; |
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359 | } |
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360 | |
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361 | void |
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362 | m860_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ |
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363 | { |
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364 | unsigned char brg; |
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365 | |
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366 | /* |
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367 | * Allocate buffer descriptors |
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368 | */ |
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369 | RxBd[port-1] = M860AllocateBufferDescriptors (1); |
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370 | TxBd[port-1] = M860AllocateBufferDescriptors (1); |
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371 | |
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372 | /* |
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373 | * Configure port B pins to enable SMTXDx and SMRXDx pins |
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374 | */ |
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375 | m860.pbpar |= (0xC0 << ((port-1) * 4)); |
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376 | m860.pbdir &= ~(0xC0 << ((port-1) * 4)); |
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377 | m860.pbdir |= (0x01 << (port-1)); |
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378 | m860.pbodr &= ~(0xC0 << ((port-1) * 4)); |
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379 | m860.pbdat &= ~(0x01 << (port-1)); |
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380 | |
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381 | /* |
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382 | * Set up BRG1 (9,600 baud) |
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383 | */ |
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384 | brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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385 | /* at least 2 ports will be the same */ |
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386 | |
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387 | /* |
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388 | * Put SMC in NMSI mode, connect SMC to BRG |
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389 | */ |
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390 | m860.simode &= ~0x7000 << ((port-1) * 8); |
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391 | m860.simode |= brg << (12 + ((port-1) * 8)); |
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392 | |
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393 | /* |
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394 | * Set up SMC1 parameter RAM common to all protocols |
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395 | */ |
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396 | if (port == 1) { |
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397 | m860.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m860; |
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398 | m860.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m860; |
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399 | m860.smc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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400 | m860.smc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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401 | m860.smc1p.mrblr = RXBUFSIZE; |
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402 | |
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403 | /* |
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404 | * Set up SMC1 parameter RAM UART-specific parameters |
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405 | */ |
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406 | m860.smc1p.un.uart.max_idl = 10; |
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407 | m860.smc1p.un.uart.brklen = 0; |
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408 | m860.smc1p.un.uart.brkec = 0; |
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409 | m860.smc1p.un.uart.brkcr = 0; |
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410 | |
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411 | } |
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412 | else { |
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413 | m860.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m860; |
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414 | m860.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m860; |
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415 | m860.smc2p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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416 | m860.smc2p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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417 | m860.smc2p.mrblr = RXBUFSIZE; |
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418 | |
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419 | /* |
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420 | * Set up SMC2 parameter RAM UART-specific parameters |
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421 | */ |
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422 | m860.smc2p.un.uart.max_idl = 10; |
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423 | m860.smc2p.un.uart.brklen = 0; |
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424 | m860.smc2p.un.uart.brkec = 0; |
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425 | m860.smc2p.un.uart.brkcr = 0; |
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426 | } |
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427 | |
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428 | /* |
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429 | * Set up the Receive Buffer Descriptor |
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430 | */ |
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431 | RxBd[port-1]->status = M860_BD_EMPTY | M860_BD_WRAP | |
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432 | M860_BD_INTERRUPT; |
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433 | RxBd[port-1]->length = 0; |
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434 | RxBd[port+3]->buffer = malloc(RXBUFSIZE); |
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435 | |
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436 | /* |
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437 | * Setup the Transmit Buffer Descriptor |
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438 | */ |
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439 | TxBd[port-1]->status = M860_BD_WRAP; |
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440 | |
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441 | /* |
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442 | * Set up SMCx general and protocol-specific mode registers |
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443 | */ |
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444 | if (port == 1) { |
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445 | m860.smc1.smce = ~0; /* Clear any pending events */ |
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446 | m860.smc1.smcm = 0; /* Mask all interrupt/event sources */ |
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447 | m860.smc1.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; |
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448 | |
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449 | /* |
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450 | * Send "Init parameters" command |
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451 | */ |
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452 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC1); |
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453 | |
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454 | /* |
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455 | * Enable receiver and transmitter |
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456 | */ |
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457 | m860.smc1.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; |
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458 | } |
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459 | else { |
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460 | m860.smc2.smce = ~0; /* Clear any pending events */ |
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461 | m860.smc2.smcm = 0; /* Mask all interrupt/event sources */ |
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462 | m860.smc2.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; |
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463 | |
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464 | /* |
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465 | * Send "Init parameters" command |
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466 | */ |
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467 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC2); |
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468 | |
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469 | /* |
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470 | * Enable receiver and transmitter |
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471 | */ |
---|
472 | m860.smc2.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; |
---|
473 | } |
---|
474 | } |
---|
475 | |
---|
476 | int |
---|
477 | m860_char_poll_read (int minor) |
---|
478 | { |
---|
479 | unsigned char c; |
---|
480 | rtems_unsigned32 level; |
---|
481 | |
---|
482 | _CPU_ISR_Disable(level); |
---|
483 | if (RxBd[minor]->status & M860_BD_EMPTY) { |
---|
484 | _CPU_ISR_Enable(level); |
---|
485 | return -1; |
---|
486 | } |
---|
487 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
488 | RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; |
---|
489 | _CPU_ISR_Enable(level); |
---|
490 | return c; |
---|
491 | } |
---|
492 | |
---|
493 | int |
---|
494 | m860_char_poll_write (int minor, const char *buf, int len) |
---|
495 | { |
---|
496 | while (len--) { |
---|
497 | while (TxBd[minor]->status & M860_BD_READY) |
---|
498 | continue; |
---|
499 | txBuf[minor] = *buf++; |
---|
500 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
501 | TxBd[minor]->length = 1; |
---|
502 | TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; |
---|
503 | } |
---|
504 | return 0; |
---|
505 | } |
---|
506 | |
---|
507 | /* |
---|
508 | * Interrupt handler |
---|
509 | */ |
---|
510 | rtems_isr |
---|
511 | m860_scc1_console_interrupt_handler (rtems_vector_number v) |
---|
512 | { |
---|
513 | /* |
---|
514 | * Buffer received? |
---|
515 | */ |
---|
516 | if ((m860.scc1.sccm & 0x1) && (m860.scc1.scce & 0x1)) { |
---|
517 | m860.scc1.scce = 0x1; |
---|
518 | /* m860.scc1.sccm &= ~0x1;*/ |
---|
519 | |
---|
520 | while ((RxBd[SCC1_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
521 | rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
522 | if (rxBufListTail[SCC1_MINOR]->next) { |
---|
523 | rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; |
---|
524 | rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; |
---|
525 | rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; |
---|
526 | rxBufListTail[SCC1_MINOR]->pos = 0; |
---|
527 | rxBufListTail[SCC1_MINOR]->next = 0; |
---|
528 | |
---|
529 | RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
530 | } |
---|
531 | RxBd[SCC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
532 | M860_BD_INTERRUPT; |
---|
533 | } |
---|
534 | } |
---|
535 | |
---|
536 | /* |
---|
537 | * Buffer transmitted? |
---|
538 | */ |
---|
539 | #if 0 |
---|
540 | if (m860.smc1.smce & 0x2) { |
---|
541 | m860.smc1.smce = 0x2; |
---|
542 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
543 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
544 | } |
---|
545 | #endif |
---|
546 | m860.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ |
---|
547 | } |
---|
548 | |
---|
549 | rtems_isr |
---|
550 | m860_scc2_console_interrupt_handler (rtems_vector_number v) |
---|
551 | { |
---|
552 | /* |
---|
553 | * Buffer received? |
---|
554 | */ |
---|
555 | if ((m860.scc2.sccm & 0x1) && (m860.scc2.scce & 0x1)) { |
---|
556 | m860.scc2.scce = 0x1; |
---|
557 | /* m860.scc2.sccm &= ~0x1;*/ |
---|
558 | |
---|
559 | while ((RxBd[SCC2_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
560 | rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
561 | if (rxBufListTail[SCC2_MINOR]->next) { |
---|
562 | rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; |
---|
563 | rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; |
---|
564 | rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; |
---|
565 | rxBufListTail[SCC2_MINOR]->pos = 0; |
---|
566 | rxBufListTail[SCC2_MINOR]->next = 0; |
---|
567 | |
---|
568 | RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
569 | } |
---|
570 | RxBd[SCC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
571 | M860_BD_INTERRUPT; |
---|
572 | } |
---|
573 | } |
---|
574 | |
---|
575 | /* |
---|
576 | * Buffer transmitted? |
---|
577 | */ |
---|
578 | #if 0 |
---|
579 | if (m860.smc1.smce & 0x2) { |
---|
580 | m860.smc1.smce = 0x2; |
---|
581 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
582 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
583 | } |
---|
584 | #endif |
---|
585 | m860.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ |
---|
586 | } |
---|
587 | |
---|
588 | rtems_isr |
---|
589 | m860_scc3_console_interrupt_handler (rtems_vector_number v) |
---|
590 | { |
---|
591 | /* |
---|
592 | * Buffer received? |
---|
593 | */ |
---|
594 | if ((m860.scc3.sccm & 0x1) && (m860.scc3.scce & 0x1)) { |
---|
595 | m860.scc3.scce = 0x1; |
---|
596 | /* m860.scc3.sccm &= ~0x1;*/ |
---|
597 | |
---|
598 | while ((RxBd[SCC3_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
599 | rxBufListTail[SCC3_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
600 | if (rxBufListTail[SCC3_MINOR]->next) { |
---|
601 | rxBufListTail[SCC3_MINOR] = rxBufListTail[SCC3_MINOR]->next; |
---|
602 | rxBufListTail[SCC3_MINOR]->buf = RxBd[SCC3_MINOR]->buffer; |
---|
603 | rxBufListTail[SCC3_MINOR]->len = RxBd[SCC3_MINOR]->length; |
---|
604 | rxBufListTail[SCC3_MINOR]->pos = 0; |
---|
605 | rxBufListTail[SCC3_MINOR]->next = 0; |
---|
606 | |
---|
607 | RxBd[SCC3_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
608 | } |
---|
609 | RxBd[SCC3_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
610 | M860_BD_INTERRUPT; |
---|
611 | } |
---|
612 | } |
---|
613 | |
---|
614 | /* |
---|
615 | * Buffer transmitted? |
---|
616 | */ |
---|
617 | #if 0 |
---|
618 | if (m860.smc1.smce & 0x2) { |
---|
619 | m860.smc1.smce = 0x2; |
---|
620 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
621 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
622 | } |
---|
623 | #endif |
---|
624 | m860.cisr = 1UL << 28; /* Clear SCC3 interrupt-in-service bit */ |
---|
625 | } |
---|
626 | |
---|
627 | rtems_isr |
---|
628 | m860_scc4_console_interrupt_handler (rtems_vector_number v) |
---|
629 | { |
---|
630 | /* |
---|
631 | * Buffer received? |
---|
632 | */ |
---|
633 | if ((m860.scc4.sccm & 0x1) && (m860.scc4.scce & 0x1)) { |
---|
634 | m860.scc4.scce = 0x1; |
---|
635 | /* m860.scc4.sccm &= ~0x1;*/ |
---|
636 | |
---|
637 | while ((RxBd[SCC4_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
638 | rxBufListTail[SCC4_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
639 | if (rxBufListTail[SCC4_MINOR]->next) { |
---|
640 | rxBufListTail[SCC4_MINOR] = rxBufListTail[SCC4_MINOR]->next; |
---|
641 | rxBufListTail[SCC4_MINOR]->buf = RxBd[SCC4_MINOR]->buffer; |
---|
642 | rxBufListTail[SCC4_MINOR]->len = RxBd[SCC4_MINOR]->length; |
---|
643 | rxBufListTail[SCC4_MINOR]->pos = 0; |
---|
644 | rxBufListTail[SCC4_MINOR]->next = 0; |
---|
645 | |
---|
646 | RxBd[SCC4_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
647 | } |
---|
648 | RxBd[SCC4_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
649 | M860_BD_INTERRUPT; |
---|
650 | } |
---|
651 | } |
---|
652 | |
---|
653 | /* |
---|
654 | * Buffer transmitted? |
---|
655 | */ |
---|
656 | #if 0 |
---|
657 | if (m860.smc1.smce & 0x2) { |
---|
658 | m860.smc1.smce = 0x2; |
---|
659 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
660 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
661 | } |
---|
662 | #endif |
---|
663 | m860.cisr = 1UL << 27; /* Clear SCC4 interrupt-in-service bit */ |
---|
664 | } |
---|
665 | |
---|
666 | rtems_isr |
---|
667 | m860_smc1_console_interrupt_handler (rtems_vector_number v) |
---|
668 | { |
---|
669 | /* |
---|
670 | * Buffer received? |
---|
671 | */ |
---|
672 | if (m860.smc1.smce & 0x1) { |
---|
673 | m860.smc1.smce = 0x1; |
---|
674 | /* m860.scc2.sccm &= ~0x1;*/ |
---|
675 | |
---|
676 | while ((RxBd[SMC1_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
677 | rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
678 | if (rxBufListTail[SMC1_MINOR]->next) { |
---|
679 | rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; |
---|
680 | rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; |
---|
681 | rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; |
---|
682 | rxBufListTail[SMC1_MINOR]->pos = 0; |
---|
683 | rxBufListTail[SMC1_MINOR]->next = 0; |
---|
684 | |
---|
685 | RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
686 | } |
---|
687 | RxBd[SMC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
688 | M860_BD_INTERRUPT; |
---|
689 | } |
---|
690 | } |
---|
691 | |
---|
692 | /* |
---|
693 | * Buffer transmitted? |
---|
694 | */ |
---|
695 | #if 0 |
---|
696 | if (m860.smc1.smce & 0x2) { |
---|
697 | m860.smc1.smce = 0x2; |
---|
698 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
699 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
700 | } |
---|
701 | #endif |
---|
702 | m860.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ |
---|
703 | } |
---|
704 | |
---|
705 | rtems_isr |
---|
706 | m860_smc2_console_interrupt_handler (rtems_vector_number v) |
---|
707 | { |
---|
708 | /* |
---|
709 | * Buffer received? |
---|
710 | */ |
---|
711 | if (m860.smc2.smce & 0x1) { |
---|
712 | m860.smc2.smce = 0x1; |
---|
713 | |
---|
714 | while ((RxBd[SMC2_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
715 | rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
716 | if (rxBufListTail[SMC2_MINOR]->next) { |
---|
717 | rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; |
---|
718 | rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; |
---|
719 | rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; |
---|
720 | rxBufListTail[SMC2_MINOR]->pos = 0; |
---|
721 | rxBufListTail[SMC2_MINOR]->next = 0; |
---|
722 | |
---|
723 | RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
724 | } |
---|
725 | RxBd[SMC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
726 | M860_BD_INTERRUPT; |
---|
727 | } |
---|
728 | } |
---|
729 | |
---|
730 | /* |
---|
731 | * Buffer transmitted? |
---|
732 | */ |
---|
733 | #if 0 |
---|
734 | if (m860.smc1.smce & 0x2) { |
---|
735 | m860.smc1.smce = 0x2; |
---|
736 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
737 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
738 | } |
---|
739 | #endif |
---|
740 | m860.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ |
---|
741 | } |
---|
742 | |
---|
743 | |
---|
744 | int |
---|
745 | m860_buf_poll_read (int minor, char **buf) |
---|
746 | { |
---|
747 | int len; |
---|
748 | |
---|
749 | if (RxBd[minor]->status & M860_BD_EMPTY) |
---|
750 | return -1; |
---|
751 | |
---|
752 | RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ |
---|
753 | len = RxBd[minor]->length; |
---|
754 | RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; |
---|
755 | |
---|
756 | return len; |
---|
757 | } |
---|
758 | |
---|
759 | int |
---|
760 | m860_buf_poll_write (int minor, char *buf, int len) |
---|
761 | { |
---|
762 | static char *last_buf[6]; |
---|
763 | |
---|
764 | while (TxBd[minor]->status & M860_BD_READY) |
---|
765 | continue; |
---|
766 | if (last_buf[minor]) |
---|
767 | free(last_buf[minor]); |
---|
768 | last_buf[minor] = buf; |
---|
769 | TxBd[minor]->buffer = buf; |
---|
770 | TxBd[minor]->length = len; |
---|
771 | TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; |
---|
772 | return 0; |
---|
773 | } |
---|
774 | |
---|
775 | /* |
---|
776 | * This is needed in case we use TERMIOS |
---|
777 | */ |
---|
778 | void m860_console_reserve_resources(rtems_configuration_table *configuration) |
---|
779 | { |
---|
780 | rtems_termios_reserve_resources (configuration, 1); |
---|
781 | } |
---|
782 | |
---|
783 | void m860_console_initialize(void) |
---|
784 | { |
---|
785 | int i; |
---|
786 | |
---|
787 | for (i=0; i < NIFACES; i++) { |
---|
788 | rxBufList[i] = malloc(sizeof(Buf_t)); |
---|
789 | rxBufListTail[i] = rxBufList[i]; |
---|
790 | rxBufList[i]->buf = 0; |
---|
791 | rxBufList[i]->len = 0; |
---|
792 | rxBufList[i]->pos = 0; |
---|
793 | rxBufList[i]->next = 0; |
---|
794 | } |
---|
795 | } |
---|
796 | |
---|
797 | rtems_device_driver m860_console_read(rtems_device_major_number major, |
---|
798 | rtems_device_minor_number minor, |
---|
799 | void *arg) |
---|
800 | { |
---|
801 | rtems_libio_rw_args_t *rw_args; |
---|
802 | char *buffer; |
---|
803 | int maximum; |
---|
804 | int count; |
---|
805 | Buf_t *tmp_buf; |
---|
806 | rtems_unsigned32 level; |
---|
807 | |
---|
808 | /* |
---|
809 | * Set up interrupts |
---|
810 | * FIXME: DANGER: WARNING: |
---|
811 | * CICR and SIMASK must be set in any module that uses |
---|
812 | * the CPM. Currently those are console-generic.c and |
---|
813 | * network.c. If the registers are not set the same |
---|
814 | * in both places, strange things may happen. |
---|
815 | * If they are only set in one place, then an application |
---|
816 | * that used the other module won't work correctly. |
---|
817 | * Put this comment in each module that sets these 2 registers |
---|
818 | */ |
---|
819 | m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
820 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
821 | m860.simask |= M860_SIMASK_LVM1; |
---|
822 | |
---|
823 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
824 | buffer = rw_args->buffer; |
---|
825 | maximum = rw_args->count; |
---|
826 | count = 0; |
---|
827 | |
---|
828 | while (count == 0) { |
---|
829 | if (rxBufList[minor]->len) { |
---|
830 | while ((count < maximum) && |
---|
831 | (rxBufList[minor]->pos < rxBufList[minor]->len)) { |
---|
832 | buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; |
---|
833 | } |
---|
834 | _CPU_ISR_Disable(level); |
---|
835 | if (rxBufList[minor]->pos == rxBufList[minor]->len) { |
---|
836 | if (rxBufList[minor]->next) { |
---|
837 | tmp_buf=rxBufList[minor]->next; |
---|
838 | free ((void *) rxBufList[minor]->buf); |
---|
839 | free ((void *) rxBufList[minor]); |
---|
840 | rxBufList[minor]=tmp_buf; |
---|
841 | } |
---|
842 | else { |
---|
843 | free(rxBufList[minor]->buf); |
---|
844 | rxBufList[minor]->buf=0; |
---|
845 | rxBufList[minor]->len=0; |
---|
846 | rxBufList[minor]->pos=0; |
---|
847 | } |
---|
848 | } |
---|
849 | _CPU_ISR_Enable(level); |
---|
850 | } |
---|
851 | else |
---|
852 | if(rxBufList[minor]->next && !rxBufList[minor]->len) { |
---|
853 | tmp_buf = rxBufList[minor]; |
---|
854 | rxBufList[minor] = rxBufList[minor]->next; |
---|
855 | free(tmp_buf); |
---|
856 | } |
---|
857 | /* sleep(1);*/ |
---|
858 | } |
---|
859 | rw_args->bytes_moved = count; |
---|
860 | return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; |
---|
861 | } |
---|
862 | |
---|
863 | rtems_device_driver m860_console_write(rtems_device_major_number major, |
---|
864 | rtems_device_minor_number minor, |
---|
865 | void *arg) |
---|
866 | { |
---|
867 | int count; |
---|
868 | int maximum; |
---|
869 | rtems_libio_rw_args_t *rw_args; |
---|
870 | char *in_buffer; |
---|
871 | char *out_buffer; |
---|
872 | int n; |
---|
873 | |
---|
874 | /* |
---|
875 | * Set up interrupts |
---|
876 | * FIXME: DANGER: WARNING: |
---|
877 | * CICR and SIMASK must be set in any module that uses |
---|
878 | * the CPM. Currently those are console-generic.c and |
---|
879 | * network.c. If the registers are not set the same |
---|
880 | * in both places, strange things may happen. |
---|
881 | * If they are only set in one place, then an application |
---|
882 | * that used the other module won't work correctly. |
---|
883 | * Put this comment in each module that sets these 2 registers |
---|
884 | */ |
---|
885 | #if 0 |
---|
886 | m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
887 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
888 | m860.simask |= M860_SIMASK_LVM1; |
---|
889 | #endif |
---|
890 | |
---|
891 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
892 | |
---|
893 | in_buffer = rw_args->buffer; |
---|
894 | maximum = rw_args->count; |
---|
895 | |
---|
896 | out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ |
---|
897 | /* be too small */ |
---|
898 | |
---|
899 | if (!out_buffer) { |
---|
900 | rw_args->bytes_moved = 0; |
---|
901 | return RTEMS_NO_MEMORY; |
---|
902 | } |
---|
903 | n=0; |
---|
904 | for (count = 0; count < maximum; count++) { |
---|
905 | if ( in_buffer[ count ] == '\n') { |
---|
906 | out_buffer[count + n] = '\r'; |
---|
907 | n++; |
---|
908 | } |
---|
909 | out_buffer[count + n] = in_buffer[count]; |
---|
910 | } |
---|
911 | m860_buf_poll_write(minor, out_buffer, maximum+n); |
---|
912 | rw_args->bytes_moved = maximum; |
---|
913 | return RTEMS_SUCCESSFUL; |
---|
914 | } |
---|
915 | |
---|
916 | |
---|
917 | /* |
---|
918 | * How to use the console. |
---|
919 | * In your BSP, have the following functions: |
---|
920 | * |
---|
921 | * rtems_device_driver console_initialize(rtems_device_major_number major, |
---|
922 | * rtems_device_minor_number minor, |
---|
923 | * void *arg) |
---|
924 | * rtems_device_driver console_open(rtems_device_major_number major, |
---|
925 | * rtems_device_minor_number minor, |
---|
926 | * void *arg) |
---|
927 | * rtems_device_driver console_close(rtems_device_major_number major, |
---|
928 | * rtems_device_minor_number minor, |
---|
929 | * void *arg) |
---|
930 | * rtems_device_driver console_read(rtems_device_major_number major, |
---|
931 | * rtems_device_minor_number minor, |
---|
932 | * void *arg) |
---|
933 | * rtems_device_driver console_write(rtems_device_major_number major, |
---|
934 | * rtems_device_minor_number minor, |
---|
935 | * void *arg) |
---|
936 | * rtems_device_driver console_control(rtems_device_major_number major, |
---|
937 | * rtems_device_minor_number minor, |
---|
938 | * void *arg) |
---|
939 | * |
---|
940 | */ |
---|