[ee733965] | 1 | /* |
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| 2 | * General Serial I/O functions. |
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| 3 | * |
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| 4 | * This file contains the functions for performing serial I/O. |
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| 5 | * The actual system calls (console_*) should be in the BSP part |
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| 6 | * of the source tree. That way different BSPs can use whichever |
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| 7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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| 8 | * this file, and it caused problems with one BSP using SCC2 |
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| 9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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| 10 | * |
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| 11 | * On-chip resources used: |
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| 12 | * resource minor note |
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| 13 | * SMC1 0 |
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| 14 | * SMC2 1 |
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| 15 | * SCC1 2 (shared with ethernet driver) |
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| 16 | * SCC2 3 |
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| 17 | * SCC3 4 |
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| 18 | * SCC4 5 |
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| 19 | * BRG1 |
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| 20 | * BRG2 |
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| 21 | * BRG3 |
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| 22 | * BRG4 |
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| 23 | * Author: Jay Monkman (jmonkman@frasca.com) |
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| 24 | * Copyright (C) 1998 by Frasca International, Inc. |
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| 25 | * |
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| 26 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: |
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| 27 | * |
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| 28 | * Author: |
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| 29 | * W. Eric Norum |
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| 30 | * Saskatchewan Accelerator Laboratory |
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| 31 | * University of Saskatchewan |
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| 32 | * Saskatoon, Saskatchewan, CANADA |
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| 33 | * eric@skatter.usask.ca |
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| 34 | * |
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[08311cc3] | 35 | * COPYRIGHT (c) 1989-1999. |
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[ee733965] | 36 | * On-Line Applications Research Corporation (OAR). |
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| 37 | * |
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| 38 | * The license and distribution terms for this file may be |
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| 39 | * found in the file LICENSE in this distribution or at |
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| 40 | * |
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| 41 | * http://www.OARcorp.com/rtems/license.html. |
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| 42 | * |
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| 43 | * $Id$ |
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| 44 | */ |
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| 45 | |
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[f817b02] | 46 | #include <rtems.h> |
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[ee733965] | 47 | #include <rtems/libio.h> |
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| 48 | #include <mpc860.h> |
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| 49 | #include <mpc860/console.h> |
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| 50 | #include <stdlib.h> |
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| 51 | #include <unistd.h> |
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| 52 | #include <termios.h> |
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| 53 | |
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| 54 | #define NIFACES 6 /* number of console devices (serial ports) */ |
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| 55 | |
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| 56 | static Buf_t *rxBufList[NIFACES]; |
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| 57 | static Buf_t *rxBufListTail[NIFACES]; |
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| 58 | |
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| 59 | /* |
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| 60 | * Interrupt-driven input buffer |
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| 61 | */ |
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| 62 | #define RXBUFSIZE 16 |
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| 63 | |
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| 64 | |
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| 65 | /* |
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| 66 | * I/O buffers and pointers to buffer descriptors |
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| 67 | */ |
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| 68 | static volatile char txBuf[NIFACES]; |
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| 69 | |
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| 70 | static volatile m860BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; |
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| 71 | |
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| 72 | /* |
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| 73 | * Device-specific routines |
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| 74 | */ |
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| 75 | static int m860_get_brg_cd(int); |
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| 76 | unsigned char m860_get_brg_clk(int); |
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| 77 | void m860_console_reserve_resources(rtems_configuration_table *); |
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| 78 | unsigned char m860_get_brg_clk(int); |
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| 79 | |
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| 80 | |
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| 81 | /* |
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| 82 | * Compute baud-rate-generator configuration register value |
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| 83 | */ |
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| 84 | static int |
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| 85 | m860_get_brg_cd (int baud) |
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| 86 | { |
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| 87 | int divisor; |
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| 88 | int div16 = 0; |
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| 89 | |
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[458bd34] | 90 | divisor = ((rtems_cpu_configuration_get_clock_speed() / 16) + |
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| 91 | (baud / 2)) / baud; |
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[ee733965] | 92 | if (divisor > 4096) { |
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| 93 | div16 = 1; |
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| 94 | divisor = (divisor + 8) / 16; |
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| 95 | } |
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| 96 | return M860_BRG_EN | M860_BRG_EXTC_BRGCLK | |
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| 97 | ((divisor - 1) << 1) | div16; |
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| 98 | } |
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| 99 | |
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| 100 | |
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| 101 | /* this function will fail if more that 4 baud rates have been selected */ |
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| 102 | /* at any time since the OS started. It needs to be fixed. FIXME */ |
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| 103 | unsigned char m860_get_brg_clk(int baud) |
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| 104 | { |
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| 105 | static short brg_spd[4]; |
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| 106 | static char brg_used[4]; |
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| 107 | int i; |
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| 108 | |
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| 109 | /* first try to find a BRG that is already at the right speed */ |
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| 110 | for (i=0; i<4; i++) { |
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| 111 | if (brg_spd[i] == baud) { |
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| 112 | break; |
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| 113 | } |
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| 114 | } |
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| 115 | |
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| 116 | if (i==4) { /* I guess we didn't find one */ |
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| 117 | for (i=0; i<4; i++) { |
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| 118 | if (brg_used[i] == 0) { |
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| 119 | break; |
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| 120 | } |
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| 121 | } |
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| 122 | } |
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| 123 | if (i != 4) { |
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| 124 | brg_used[i]++; |
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| 125 | brg_spd[i]=baud; |
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| 126 | switch (i) { |
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| 127 | case 0: |
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| 128 | m860.brgc1 = M860_BRG_RST; |
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| 129 | m860.brgc1 = m860_get_brg_cd(baud); |
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| 130 | break; |
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| 131 | case 1: |
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| 132 | m860.brgc2 = M860_BRG_RST; |
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| 133 | m860.brgc2 = m860_get_brg_cd(baud); |
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| 134 | break; |
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| 135 | case 2: |
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| 136 | m860.brgc3 = M860_BRG_RST; |
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| 137 | m860.brgc3 = m860_get_brg_cd(baud); |
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| 138 | break; |
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| 139 | case 3: |
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| 140 | m860.brgc4 = M860_BRG_RST; |
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| 141 | m860.brgc4 = m860_get_brg_cd(baud); |
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| 142 | break; |
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| 143 | } |
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| 144 | return i; |
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| 145 | } |
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| 146 | |
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| 147 | else |
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| 148 | return 0xff; |
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| 149 | } |
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| 150 | |
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| 151 | /* |
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| 152 | * Hardware-dependent portion of tcsetattr(). |
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| 153 | */ |
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| 154 | int |
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| 155 | m860_smc_set_attributes (int minor, const struct termios *t) |
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| 156 | { |
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| 157 | /* |
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| 158 | * minor must be 0 or 1 |
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| 159 | */ |
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| 160 | int baud; |
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| 161 | int brg; |
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| 162 | switch (t->c_cflag & CBAUD) { |
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| 163 | default: baud = -1; break; |
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| 164 | case B50: baud = 50; break; |
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| 165 | case B75: baud = 75; break; |
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| 166 | case B110: baud = 110; break; |
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| 167 | case B134: baud = 134; break; |
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| 168 | case B150: baud = 150; break; |
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| 169 | case B200: baud = 200; break; |
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| 170 | case B300: baud = 300; break; |
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| 171 | case B600: baud = 600; break; |
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| 172 | case B1200: baud = 1200; break; |
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| 173 | case B1800: baud = 1800; break; |
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| 174 | case B2400: baud = 2400; break; |
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| 175 | case B4800: baud = 4800; break; |
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| 176 | case B9600: baud = 9600; break; |
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| 177 | case B19200: baud = 19200; break; |
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| 178 | case B38400: baud = 38400; break; |
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| 179 | case B57600: baud = 57600; break; |
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| 180 | case B115200: baud = 115200; break; |
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| 181 | case B230400: baud = 230400; break; |
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| 182 | case B460800: baud = 460800; break; |
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| 183 | } |
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| 184 | if (baud > 0) { |
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| 185 | brg = m860_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ |
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| 186 | /* at least 2 ports will be the same */ |
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| 187 | m860.simode |= brg << (12 + ((minor) * 16)); |
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| 188 | } |
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| 189 | return 0; |
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| 190 | } |
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| 191 | |
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| 192 | int |
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| 193 | m860_scc_set_attributes (int minor, const struct termios *t) |
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| 194 | { |
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| 195 | /* |
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| 196 | * minor must be 2, 3, 4 or 5 |
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| 197 | */ |
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| 198 | int baud; |
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| 199 | int brg; |
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| 200 | switch (t->c_cflag & CBAUD) { |
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| 201 | default: baud = -1; break; |
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| 202 | case B50: baud = 50; break; |
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| 203 | case B75: baud = 75; break; |
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| 204 | case B110: baud = 110; break; |
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| 205 | case B134: baud = 134; break; |
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| 206 | case B150: baud = 150; break; |
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| 207 | case B200: baud = 200; break; |
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| 208 | case B300: baud = 300; break; |
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| 209 | case B600: baud = 600; break; |
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| 210 | case B1200: baud = 1200; break; |
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| 211 | case B1800: baud = 1800; break; |
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| 212 | case B2400: baud = 2400; break; |
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| 213 | case B4800: baud = 4800; break; |
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| 214 | case B9600: baud = 9600; break; |
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| 215 | case B19200: baud = 19200; break; |
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| 216 | case B38400: baud = 38400; break; |
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| 217 | case B57600: baud = 57600; break; |
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| 218 | case B115200: baud = 115200; break; |
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| 219 | case B230400: baud = 230400; break; |
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| 220 | case B460800: baud = 460800; break; |
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| 221 | } |
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| 222 | if (baud > 0) { |
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| 223 | brg = m860_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ |
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| 224 | /* at least 2 ports will be the same */ |
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| 225 | m860.sicr |= (brg << (3 + ((minor-2) * 8))) | |
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| 226 | (brg << ((minor-2) * 8)); |
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| 227 | } |
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| 228 | return 0; |
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| 229 | } |
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| 230 | |
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| 231 | void |
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| 232 | m860_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ |
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| 233 | { |
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| 234 | unsigned char brg; |
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| 235 | volatile m860SCCparms_t *sccparms; |
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| 236 | volatile m860SCCRegisters_t *sccregs; |
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| 237 | |
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| 238 | /* |
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| 239 | * Allocate buffer descriptors |
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| 240 | */ |
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| 241 | RxBd[port+1] = M860AllocateBufferDescriptors(1); |
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| 242 | TxBd[port+1] = M860AllocateBufferDescriptors(1); |
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| 243 | |
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| 244 | /* |
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| 245 | * Configure ports A and B to enable TXDx and RXDx pins |
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| 246 | */ |
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| 247 | m860.papar |= (0xC << ((port-2) * 2)); |
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| 248 | m860.padir &= ~(0xC << ((port-2) * 2)); |
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| 249 | m860.pbdir |= (0x04 << (port-2)); |
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| 250 | m860.paodr &= ~(0x8 << ((port-2) * 2)); |
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| 251 | m860.pbdat &= ~(0x04 << (port-2)); |
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| 252 | |
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| 253 | /* SCC2 is the only one with handshaking lines */ |
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| 254 | /* |
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| 255 | if (port == 2) { |
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| 256 | m860.pcpar |= (0x02); |
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| 257 | m860.pcpar &= ~(0xc0); |
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| 258 | m860.pcdir &= ~(0xc2); |
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| 259 | m860.pcso |= (0xc0); |
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| 260 | } |
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| 261 | */ |
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| 262 | |
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| 263 | brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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| 264 | /* at least 2 ports will be the same */ |
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| 265 | |
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| 266 | /* |
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| 267 | * Set up SDMA |
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| 268 | */ |
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| 269 | m860.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC860UM/AD */ |
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| 270 | |
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| 271 | |
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| 272 | m860.sicr &= ~(0xff << ((port-1) * 8)); |
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| 273 | m860.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); |
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| 274 | |
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| 275 | /* |
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| 276 | * Set up SMC1 parameter RAM common to all protocols |
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| 277 | */ |
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| 278 | if (port == 1) { |
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| 279 | sccparms = (m860SCCparms_t*)&m860.scc1p; |
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| 280 | sccregs = &m860.scc1; |
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| 281 | } |
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| 282 | else if (port == 2) { |
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| 283 | sccparms = &m860.scc2p; |
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| 284 | sccregs = &m860.scc2; |
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| 285 | } |
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| 286 | else if (port == 3) { |
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| 287 | sccparms = &m860.scc3p; |
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| 288 | sccregs = &m860.scc3; |
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| 289 | } |
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| 290 | else { |
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| 291 | sccparms = &m860.scc4p; |
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| 292 | sccregs = &m860.scc4; |
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| 293 | } |
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| 294 | |
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| 295 | sccparms->rbase = (char *)RxBd[port+1] - (char *)&m860; |
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| 296 | sccparms->tbase = (char *)TxBd[port+1] - (char *)&m860; |
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| 297 | |
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| 298 | if (port == 1) |
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| 299 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1); |
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| 300 | else if (port == 2) |
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| 301 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC2); |
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| 302 | else if (port == 3) |
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| 303 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC3); |
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| 304 | else if (port == 4) |
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| 305 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC4); |
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| 306 | |
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| 307 | sccparms->rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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| 308 | sccparms->tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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| 309 | sccparms->mrblr = RXBUFSIZE; |
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| 310 | |
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| 311 | sccparms->un.uart.max_idl = 10; |
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| 312 | sccparms->un.uart.brklen = 0; |
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| 313 | sccparms->un.uart.brkec = 0; |
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| 314 | sccparms->un.uart.brkcr = 1; |
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| 315 | |
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| 316 | sccparms->un.uart.parec = 0; |
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| 317 | sccparms->un.uart.frmec = 0; |
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| 318 | sccparms->un.uart.nosec = 0; |
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| 319 | |
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| 320 | sccparms->un.uart.uaddr[0] = 0; |
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| 321 | sccparms->un.uart.uaddr[1] = 0; |
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| 322 | sccparms->un.uart.toseq = 0; |
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| 323 | |
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| 324 | sccparms->un.uart.character[0] = 0x8000; |
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| 325 | sccparms->un.uart.character[1] = 0x8000; |
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| 326 | sccparms->un.uart.character[2] = 0x8000; |
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| 327 | sccparms->un.uart.character[3] = 0x8000; |
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| 328 | sccparms->un.uart.character[4] = 0x8000; |
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| 329 | sccparms->un.uart.character[5] = 0x8000; |
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| 330 | sccparms->un.uart.character[6] = 0x8000; |
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| 331 | sccparms->un.uart.character[7] = 0x8000; |
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| 332 | |
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| 333 | sccparms->un.uart.rccm = 0xc0ff; |
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| 334 | |
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| 335 | /* |
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| 336 | * Set up the Receive Buffer Descriptor |
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| 337 | */ |
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| 338 | RxBd[port+1]->status = M860_BD_EMPTY | M860_BD_WRAP | |
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| 339 | M860_BD_INTERRUPT; |
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| 340 | RxBd[port+1]->length = 0; |
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| 341 | RxBd[port+1]->buffer = malloc(RXBUFSIZE); |
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| 342 | |
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| 343 | /* |
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| 344 | * Setup the Transmit Buffer Descriptor |
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| 345 | */ |
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| 346 | TxBd[port+1]->status = M860_BD_WRAP; |
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| 347 | |
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| 348 | /* |
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| 349 | * Set up SCCx general and protocol-specific mode registers |
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| 350 | */ |
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| 351 | sccregs->scce = 0xffff; |
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| 352 | sccregs->sccm = 0x0000; |
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| 353 | sccregs->gsmr_h = 0x00000020; |
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| 354 | sccregs->gsmr_l = 0x00028004; |
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| 355 | sccregs->psmr = 0x3000; |
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| 356 | sccregs->gsmr_l = 0x00028034; |
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| 357 | } |
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| 358 | |
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| 359 | void |
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| 360 | m860_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ |
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| 361 | { |
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| 362 | unsigned char brg; |
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| 363 | |
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| 364 | /* |
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| 365 | * Allocate buffer descriptors |
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| 366 | */ |
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| 367 | RxBd[port-1] = M860AllocateBufferDescriptors (1); |
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| 368 | TxBd[port-1] = M860AllocateBufferDescriptors (1); |
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| 369 | |
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| 370 | /* |
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| 371 | * Configure port B pins to enable SMTXDx and SMRXDx pins |
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| 372 | */ |
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| 373 | m860.pbpar |= (0xC0 << ((port-1) * 4)); |
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| 374 | m860.pbdir &= ~(0xC0 << ((port-1) * 4)); |
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| 375 | m860.pbdir |= (0x01 << (port-1)); |
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| 376 | m860.pbodr &= ~(0xC0 << ((port-1) * 4)); |
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| 377 | m860.pbdat &= ~(0x01 << (port-1)); |
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| 378 | |
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| 379 | /* |
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| 380 | * Set up BRG1 (9,600 baud) |
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| 381 | */ |
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| 382 | brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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| 383 | /* at least 2 ports will be the same */ |
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| 384 | |
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| 385 | /* |
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| 386 | * Put SMC in NMSI mode, connect SMC to BRG |
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| 387 | */ |
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| 388 | m860.simode &= ~0x7000 << ((port-1) * 8); |
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| 389 | m860.simode |= brg << (12 + ((port-1) * 8)); |
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| 390 | |
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| 391 | /* |
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| 392 | * Set up SMC1 parameter RAM common to all protocols |
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| 393 | */ |
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| 394 | if (port == 1) { |
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| 395 | m860.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m860; |
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| 396 | m860.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m860; |
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| 397 | m860.smc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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| 398 | m860.smc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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| 399 | m860.smc1p.mrblr = RXBUFSIZE; |
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| 400 | |
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| 401 | /* |
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| 402 | * Set up SMC1 parameter RAM UART-specific parameters |
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| 403 | */ |
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| 404 | m860.smc1p.un.uart.max_idl = 10; |
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| 405 | m860.smc1p.un.uart.brklen = 0; |
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| 406 | m860.smc1p.un.uart.brkec = 0; |
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| 407 | m860.smc1p.un.uart.brkcr = 0; |
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| 408 | |
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| 409 | } |
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| 410 | else { |
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| 411 | m860.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m860; |
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| 412 | m860.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m860; |
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| 413 | m860.smc2p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); |
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| 414 | m860.smc2p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); |
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| 415 | m860.smc2p.mrblr = RXBUFSIZE; |
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| 416 | |
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| 417 | /* |
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| 418 | * Set up SMC2 parameter RAM UART-specific parameters |
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| 419 | */ |
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| 420 | m860.smc2p.un.uart.max_idl = 10; |
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| 421 | m860.smc2p.un.uart.brklen = 0; |
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| 422 | m860.smc2p.un.uart.brkec = 0; |
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| 423 | m860.smc2p.un.uart.brkcr = 0; |
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| 424 | } |
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| 425 | |
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| 426 | /* |
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| 427 | * Set up the Receive Buffer Descriptor |
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| 428 | */ |
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| 429 | RxBd[port-1]->status = M860_BD_EMPTY | M860_BD_WRAP | |
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| 430 | M860_BD_INTERRUPT; |
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| 431 | RxBd[port-1]->length = 0; |
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[63b96b9] | 432 | RxBd[port-1]->buffer = malloc(RXBUFSIZE); |
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[ee733965] | 433 | |
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| 434 | /* |
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| 435 | * Setup the Transmit Buffer Descriptor |
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| 436 | */ |
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| 437 | TxBd[port-1]->status = M860_BD_WRAP; |
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| 438 | |
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| 439 | /* |
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| 440 | * Set up SMCx general and protocol-specific mode registers |
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| 441 | */ |
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| 442 | if (port == 1) { |
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| 443 | m860.smc1.smce = ~0; /* Clear any pending events */ |
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| 444 | m860.smc1.smcm = 0; /* Mask all interrupt/event sources */ |
---|
| 445 | m860.smc1.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; |
---|
| 446 | |
---|
| 447 | /* |
---|
| 448 | * Send "Init parameters" command |
---|
| 449 | */ |
---|
| 450 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC1); |
---|
| 451 | |
---|
| 452 | /* |
---|
| 453 | * Enable receiver and transmitter |
---|
| 454 | */ |
---|
| 455 | m860.smc1.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; |
---|
| 456 | } |
---|
| 457 | else { |
---|
| 458 | m860.smc2.smce = ~0; /* Clear any pending events */ |
---|
| 459 | m860.smc2.smcm = 0; /* Mask all interrupt/event sources */ |
---|
| 460 | m860.smc2.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; |
---|
| 461 | |
---|
| 462 | /* |
---|
| 463 | * Send "Init parameters" command |
---|
| 464 | */ |
---|
| 465 | M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC2); |
---|
| 466 | |
---|
| 467 | /* |
---|
| 468 | * Enable receiver and transmitter |
---|
| 469 | */ |
---|
| 470 | m860.smc2.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; |
---|
| 471 | } |
---|
| 472 | } |
---|
| 473 | |
---|
| 474 | int |
---|
| 475 | m860_char_poll_read (int minor) |
---|
| 476 | { |
---|
| 477 | unsigned char c; |
---|
| 478 | rtems_unsigned32 level; |
---|
| 479 | |
---|
| 480 | _CPU_ISR_Disable(level); |
---|
| 481 | if (RxBd[minor]->status & M860_BD_EMPTY) { |
---|
| 482 | _CPU_ISR_Enable(level); |
---|
| 483 | return -1; |
---|
| 484 | } |
---|
| 485 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
| 486 | RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; |
---|
| 487 | _CPU_ISR_Enable(level); |
---|
| 488 | return c; |
---|
| 489 | } |
---|
| 490 | |
---|
| 491 | int |
---|
| 492 | m860_char_poll_write (int minor, const char *buf, int len) |
---|
| 493 | { |
---|
| 494 | while (len--) { |
---|
| 495 | while (TxBd[minor]->status & M860_BD_READY) |
---|
| 496 | continue; |
---|
| 497 | txBuf[minor] = *buf++; |
---|
| 498 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
| 499 | TxBd[minor]->length = 1; |
---|
| 500 | TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; |
---|
| 501 | } |
---|
| 502 | return 0; |
---|
| 503 | } |
---|
| 504 | |
---|
| 505 | /* |
---|
| 506 | * Interrupt handler |
---|
| 507 | */ |
---|
| 508 | rtems_isr |
---|
| 509 | m860_scc1_console_interrupt_handler (rtems_vector_number v) |
---|
| 510 | { |
---|
| 511 | /* |
---|
| 512 | * Buffer received? |
---|
| 513 | */ |
---|
| 514 | if ((m860.scc1.sccm & 0x1) && (m860.scc1.scce & 0x1)) { |
---|
| 515 | m860.scc1.scce = 0x1; |
---|
| 516 | /* m860.scc1.sccm &= ~0x1;*/ |
---|
| 517 | |
---|
| 518 | while ((RxBd[SCC1_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 519 | rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 520 | if (rxBufListTail[SCC1_MINOR]->next) { |
---|
| 521 | rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; |
---|
| 522 | rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; |
---|
| 523 | rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; |
---|
| 524 | rxBufListTail[SCC1_MINOR]->pos = 0; |
---|
| 525 | rxBufListTail[SCC1_MINOR]->next = 0; |
---|
| 526 | |
---|
| 527 | RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 528 | } |
---|
| 529 | RxBd[SCC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 530 | M860_BD_INTERRUPT; |
---|
| 531 | } |
---|
| 532 | } |
---|
| 533 | |
---|
| 534 | /* |
---|
| 535 | * Buffer transmitted? |
---|
| 536 | */ |
---|
| 537 | #if 0 |
---|
| 538 | if (m860.smc1.smce & 0x2) { |
---|
| 539 | m860.smc1.smce = 0x2; |
---|
| 540 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 541 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 542 | } |
---|
| 543 | #endif |
---|
| 544 | m860.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ |
---|
| 545 | } |
---|
| 546 | |
---|
| 547 | rtems_isr |
---|
| 548 | m860_scc2_console_interrupt_handler (rtems_vector_number v) |
---|
| 549 | { |
---|
| 550 | /* |
---|
| 551 | * Buffer received? |
---|
| 552 | */ |
---|
| 553 | if ((m860.scc2.sccm & 0x1) && (m860.scc2.scce & 0x1)) { |
---|
| 554 | m860.scc2.scce = 0x1; |
---|
| 555 | /* m860.scc2.sccm &= ~0x1;*/ |
---|
| 556 | |
---|
| 557 | while ((RxBd[SCC2_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 558 | rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 559 | if (rxBufListTail[SCC2_MINOR]->next) { |
---|
| 560 | rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; |
---|
| 561 | rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; |
---|
| 562 | rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; |
---|
| 563 | rxBufListTail[SCC2_MINOR]->pos = 0; |
---|
| 564 | rxBufListTail[SCC2_MINOR]->next = 0; |
---|
| 565 | |
---|
| 566 | RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 567 | } |
---|
| 568 | RxBd[SCC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 569 | M860_BD_INTERRUPT; |
---|
| 570 | } |
---|
| 571 | } |
---|
| 572 | |
---|
| 573 | /* |
---|
| 574 | * Buffer transmitted? |
---|
| 575 | */ |
---|
| 576 | #if 0 |
---|
| 577 | if (m860.smc1.smce & 0x2) { |
---|
| 578 | m860.smc1.smce = 0x2; |
---|
| 579 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 580 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 581 | } |
---|
| 582 | #endif |
---|
| 583 | m860.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ |
---|
| 584 | } |
---|
| 585 | |
---|
| 586 | rtems_isr |
---|
| 587 | m860_scc3_console_interrupt_handler (rtems_vector_number v) |
---|
| 588 | { |
---|
| 589 | /* |
---|
| 590 | * Buffer received? |
---|
| 591 | */ |
---|
| 592 | if ((m860.scc3.sccm & 0x1) && (m860.scc3.scce & 0x1)) { |
---|
| 593 | m860.scc3.scce = 0x1; |
---|
| 594 | /* m860.scc3.sccm &= ~0x1;*/ |
---|
| 595 | |
---|
| 596 | while ((RxBd[SCC3_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 597 | rxBufListTail[SCC3_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 598 | if (rxBufListTail[SCC3_MINOR]->next) { |
---|
| 599 | rxBufListTail[SCC3_MINOR] = rxBufListTail[SCC3_MINOR]->next; |
---|
| 600 | rxBufListTail[SCC3_MINOR]->buf = RxBd[SCC3_MINOR]->buffer; |
---|
| 601 | rxBufListTail[SCC3_MINOR]->len = RxBd[SCC3_MINOR]->length; |
---|
| 602 | rxBufListTail[SCC3_MINOR]->pos = 0; |
---|
| 603 | rxBufListTail[SCC3_MINOR]->next = 0; |
---|
| 604 | |
---|
| 605 | RxBd[SCC3_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 606 | } |
---|
| 607 | RxBd[SCC3_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 608 | M860_BD_INTERRUPT; |
---|
| 609 | } |
---|
| 610 | } |
---|
| 611 | |
---|
| 612 | /* |
---|
| 613 | * Buffer transmitted? |
---|
| 614 | */ |
---|
| 615 | #if 0 |
---|
| 616 | if (m860.smc1.smce & 0x2) { |
---|
| 617 | m860.smc1.smce = 0x2; |
---|
| 618 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 619 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 620 | } |
---|
| 621 | #endif |
---|
| 622 | m860.cisr = 1UL << 28; /* Clear SCC3 interrupt-in-service bit */ |
---|
| 623 | } |
---|
| 624 | |
---|
| 625 | rtems_isr |
---|
| 626 | m860_scc4_console_interrupt_handler (rtems_vector_number v) |
---|
| 627 | { |
---|
| 628 | /* |
---|
| 629 | * Buffer received? |
---|
| 630 | */ |
---|
| 631 | if ((m860.scc4.sccm & 0x1) && (m860.scc4.scce & 0x1)) { |
---|
| 632 | m860.scc4.scce = 0x1; |
---|
| 633 | /* m860.scc4.sccm &= ~0x1;*/ |
---|
| 634 | |
---|
| 635 | while ((RxBd[SCC4_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 636 | rxBufListTail[SCC4_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 637 | if (rxBufListTail[SCC4_MINOR]->next) { |
---|
| 638 | rxBufListTail[SCC4_MINOR] = rxBufListTail[SCC4_MINOR]->next; |
---|
| 639 | rxBufListTail[SCC4_MINOR]->buf = RxBd[SCC4_MINOR]->buffer; |
---|
| 640 | rxBufListTail[SCC4_MINOR]->len = RxBd[SCC4_MINOR]->length; |
---|
| 641 | rxBufListTail[SCC4_MINOR]->pos = 0; |
---|
| 642 | rxBufListTail[SCC4_MINOR]->next = 0; |
---|
| 643 | |
---|
| 644 | RxBd[SCC4_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 645 | } |
---|
| 646 | RxBd[SCC4_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 647 | M860_BD_INTERRUPT; |
---|
| 648 | } |
---|
| 649 | } |
---|
| 650 | |
---|
| 651 | /* |
---|
| 652 | * Buffer transmitted? |
---|
| 653 | */ |
---|
| 654 | #if 0 |
---|
| 655 | if (m860.smc1.smce & 0x2) { |
---|
| 656 | m860.smc1.smce = 0x2; |
---|
| 657 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 658 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 659 | } |
---|
| 660 | #endif |
---|
| 661 | m860.cisr = 1UL << 27; /* Clear SCC4 interrupt-in-service bit */ |
---|
| 662 | } |
---|
| 663 | |
---|
| 664 | rtems_isr |
---|
| 665 | m860_smc1_console_interrupt_handler (rtems_vector_number v) |
---|
| 666 | { |
---|
| 667 | /* |
---|
| 668 | * Buffer received? |
---|
| 669 | */ |
---|
| 670 | if (m860.smc1.smce & 0x1) { |
---|
| 671 | m860.smc1.smce = 0x1; |
---|
| 672 | /* m860.scc2.sccm &= ~0x1;*/ |
---|
| 673 | |
---|
| 674 | while ((RxBd[SMC1_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 675 | rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 676 | if (rxBufListTail[SMC1_MINOR]->next) { |
---|
| 677 | rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; |
---|
| 678 | rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; |
---|
| 679 | rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; |
---|
| 680 | rxBufListTail[SMC1_MINOR]->pos = 0; |
---|
| 681 | rxBufListTail[SMC1_MINOR]->next = 0; |
---|
| 682 | |
---|
| 683 | RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 684 | } |
---|
| 685 | RxBd[SMC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 686 | M860_BD_INTERRUPT; |
---|
| 687 | } |
---|
| 688 | } |
---|
| 689 | |
---|
| 690 | /* |
---|
| 691 | * Buffer transmitted? |
---|
| 692 | */ |
---|
| 693 | #if 0 |
---|
| 694 | if (m860.smc1.smce & 0x2) { |
---|
| 695 | m860.smc1.smce = 0x2; |
---|
| 696 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 697 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 698 | } |
---|
| 699 | #endif |
---|
| 700 | m860.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ |
---|
| 701 | } |
---|
| 702 | |
---|
| 703 | rtems_isr |
---|
| 704 | m860_smc2_console_interrupt_handler (rtems_vector_number v) |
---|
| 705 | { |
---|
| 706 | /* |
---|
| 707 | * Buffer received? |
---|
| 708 | */ |
---|
| 709 | if (m860.smc2.smce & 0x1) { |
---|
| 710 | m860.smc2.smce = 0x1; |
---|
| 711 | |
---|
| 712 | while ((RxBd[SMC2_MINOR]->status & M860_BD_EMPTY) == 0) { |
---|
| 713 | rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
| 714 | if (rxBufListTail[SMC2_MINOR]->next) { |
---|
| 715 | rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; |
---|
| 716 | rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; |
---|
| 717 | rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; |
---|
| 718 | rxBufListTail[SMC2_MINOR]->pos = 0; |
---|
| 719 | rxBufListTail[SMC2_MINOR]->next = 0; |
---|
| 720 | |
---|
| 721 | RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
| 722 | } |
---|
| 723 | RxBd[SMC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | |
---|
| 724 | M860_BD_INTERRUPT; |
---|
| 725 | } |
---|
| 726 | } |
---|
| 727 | |
---|
| 728 | /* |
---|
| 729 | * Buffer transmitted? |
---|
| 730 | */ |
---|
| 731 | #if 0 |
---|
| 732 | if (m860.smc1.smce & 0x2) { |
---|
| 733 | m860.smc1.smce = 0x2; |
---|
| 734 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
| 735 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
| 736 | } |
---|
| 737 | #endif |
---|
| 738 | m860.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ |
---|
| 739 | } |
---|
| 740 | |
---|
| 741 | |
---|
| 742 | int |
---|
| 743 | m860_buf_poll_read (int minor, char **buf) |
---|
| 744 | { |
---|
| 745 | int len; |
---|
| 746 | |
---|
| 747 | if (RxBd[minor]->status & M860_BD_EMPTY) |
---|
| 748 | return -1; |
---|
| 749 | |
---|
| 750 | RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ |
---|
| 751 | len = RxBd[minor]->length; |
---|
| 752 | RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; |
---|
| 753 | |
---|
| 754 | return len; |
---|
| 755 | } |
---|
| 756 | |
---|
| 757 | int |
---|
| 758 | m860_buf_poll_write (int minor, char *buf, int len) |
---|
| 759 | { |
---|
| 760 | static char *last_buf[6]; |
---|
| 761 | |
---|
| 762 | while (TxBd[minor]->status & M860_BD_READY) |
---|
| 763 | continue; |
---|
| 764 | if (last_buf[minor]) |
---|
| 765 | free(last_buf[minor]); |
---|
| 766 | last_buf[minor] = buf; |
---|
| 767 | TxBd[minor]->buffer = buf; |
---|
| 768 | TxBd[minor]->length = len; |
---|
| 769 | TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; |
---|
| 770 | return 0; |
---|
| 771 | } |
---|
| 772 | |
---|
| 773 | /* |
---|
| 774 | * This is needed in case we use TERMIOS |
---|
| 775 | */ |
---|
| 776 | void m860_console_reserve_resources(rtems_configuration_table *configuration) |
---|
| 777 | { |
---|
| 778 | rtems_termios_reserve_resources (configuration, 1); |
---|
| 779 | } |
---|
| 780 | |
---|
| 781 | void m860_console_initialize(void) |
---|
| 782 | { |
---|
| 783 | int i; |
---|
| 784 | |
---|
| 785 | for (i=0; i < NIFACES; i++) { |
---|
| 786 | rxBufList[i] = malloc(sizeof(Buf_t)); |
---|
| 787 | rxBufListTail[i] = rxBufList[i]; |
---|
| 788 | rxBufList[i]->buf = 0; |
---|
| 789 | rxBufList[i]->len = 0; |
---|
| 790 | rxBufList[i]->pos = 0; |
---|
| 791 | rxBufList[i]->next = 0; |
---|
| 792 | } |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | rtems_device_driver m860_console_read(rtems_device_major_number major, |
---|
| 796 | rtems_device_minor_number minor, |
---|
| 797 | void *arg) |
---|
| 798 | { |
---|
| 799 | rtems_libio_rw_args_t *rw_args; |
---|
| 800 | char *buffer; |
---|
| 801 | int maximum; |
---|
| 802 | int count; |
---|
| 803 | Buf_t *tmp_buf; |
---|
| 804 | rtems_unsigned32 level; |
---|
| 805 | |
---|
| 806 | /* |
---|
| 807 | * Set up interrupts |
---|
| 808 | * FIXME: DANGER: WARNING: |
---|
| 809 | * CICR and SIMASK must be set in any module that uses |
---|
| 810 | * the CPM. Currently those are console-generic.c and |
---|
| 811 | * network.c. If the registers are not set the same |
---|
| 812 | * in both places, strange things may happen. |
---|
| 813 | * If they are only set in one place, then an application |
---|
| 814 | * that used the other module won't work correctly. |
---|
| 815 | * Put this comment in each module that sets these 2 registers |
---|
| 816 | */ |
---|
| 817 | m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
| 818 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
| 819 | m860.simask |= M860_SIMASK_LVM1; |
---|
| 820 | |
---|
| 821 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
| 822 | buffer = rw_args->buffer; |
---|
| 823 | maximum = rw_args->count; |
---|
| 824 | count = 0; |
---|
| 825 | |
---|
| 826 | while (count == 0) { |
---|
| 827 | if (rxBufList[minor]->len) { |
---|
| 828 | while ((count < maximum) && |
---|
| 829 | (rxBufList[minor]->pos < rxBufList[minor]->len)) { |
---|
| 830 | buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; |
---|
| 831 | } |
---|
| 832 | _CPU_ISR_Disable(level); |
---|
| 833 | if (rxBufList[minor]->pos == rxBufList[minor]->len) { |
---|
| 834 | if (rxBufList[minor]->next) { |
---|
| 835 | tmp_buf=rxBufList[minor]->next; |
---|
[656dabf] | 836 | free ((void *) rxBufList[minor]->buf); |
---|
| 837 | free ((void *) rxBufList[minor]); |
---|
[ee733965] | 838 | rxBufList[minor]=tmp_buf; |
---|
| 839 | } |
---|
| 840 | else { |
---|
| 841 | free(rxBufList[minor]->buf); |
---|
| 842 | rxBufList[minor]->buf=0; |
---|
| 843 | rxBufList[minor]->len=0; |
---|
| 844 | rxBufList[minor]->pos=0; |
---|
| 845 | } |
---|
| 846 | } |
---|
| 847 | _CPU_ISR_Enable(level); |
---|
| 848 | } |
---|
| 849 | else |
---|
| 850 | if(rxBufList[minor]->next && !rxBufList[minor]->len) { |
---|
| 851 | tmp_buf = rxBufList[minor]; |
---|
| 852 | rxBufList[minor] = rxBufList[minor]->next; |
---|
| 853 | free(tmp_buf); |
---|
| 854 | } |
---|
| 855 | /* sleep(1);*/ |
---|
| 856 | } |
---|
| 857 | rw_args->bytes_moved = count; |
---|
| 858 | return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; |
---|
| 859 | } |
---|
| 860 | |
---|
| 861 | rtems_device_driver m860_console_write(rtems_device_major_number major, |
---|
| 862 | rtems_device_minor_number minor, |
---|
| 863 | void *arg) |
---|
| 864 | { |
---|
| 865 | int count; |
---|
| 866 | int maximum; |
---|
| 867 | rtems_libio_rw_args_t *rw_args; |
---|
| 868 | char *in_buffer; |
---|
| 869 | char *out_buffer; |
---|
| 870 | int n; |
---|
| 871 | |
---|
| 872 | /* |
---|
| 873 | * Set up interrupts |
---|
| 874 | * FIXME: DANGER: WARNING: |
---|
| 875 | * CICR and SIMASK must be set in any module that uses |
---|
| 876 | * the CPM. Currently those are console-generic.c and |
---|
| 877 | * network.c. If the registers are not set the same |
---|
| 878 | * in both places, strange things may happen. |
---|
| 879 | * If they are only set in one place, then an application |
---|
| 880 | * that used the other module won't work correctly. |
---|
| 881 | * Put this comment in each module that sets these 2 registers |
---|
| 882 | */ |
---|
[656dabf] | 883 | #if 0 |
---|
| 884 | m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
[ee733965] | 885 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
[656dabf] | 886 | m860.simask |= M860_SIMASK_LVM1; |
---|
| 887 | #endif |
---|
[ee733965] | 888 | |
---|
| 889 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
| 890 | |
---|
| 891 | in_buffer = rw_args->buffer; |
---|
| 892 | maximum = rw_args->count; |
---|
| 893 | |
---|
| 894 | out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ |
---|
| 895 | /* be too small */ |
---|
| 896 | |
---|
| 897 | if (!out_buffer) { |
---|
| 898 | rw_args->bytes_moved = 0; |
---|
| 899 | return RTEMS_NO_MEMORY; |
---|
| 900 | } |
---|
| 901 | n=0; |
---|
| 902 | for (count = 0; count < maximum; count++) { |
---|
| 903 | if ( in_buffer[ count ] == '\n') { |
---|
| 904 | out_buffer[count + n] = '\r'; |
---|
| 905 | n++; |
---|
| 906 | } |
---|
| 907 | out_buffer[count + n] = in_buffer[count]; |
---|
| 908 | } |
---|
| 909 | m860_buf_poll_write(minor, out_buffer, maximum+n); |
---|
| 910 | rw_args->bytes_moved = maximum; |
---|
| 911 | return RTEMS_SUCCESSFUL; |
---|
| 912 | } |
---|
| 913 | |
---|
| 914 | |
---|
| 915 | /* |
---|
| 916 | * How to use the console. |
---|
| 917 | * In your BSP, have the following functions: |
---|
| 918 | * |
---|
| 919 | * rtems_device_driver console_initialize(rtems_device_major_number major, |
---|
| 920 | * rtems_device_minor_number minor, |
---|
| 921 | * void *arg) |
---|
| 922 | * rtems_device_driver console_open(rtems_device_major_number major, |
---|
| 923 | * rtems_device_minor_number minor, |
---|
| 924 | * void *arg) |
---|
| 925 | * rtems_device_driver console_close(rtems_device_major_number major, |
---|
| 926 | * rtems_device_minor_number minor, |
---|
| 927 | * void *arg) |
---|
| 928 | * rtems_device_driver console_read(rtems_device_major_number major, |
---|
| 929 | * rtems_device_minor_number minor, |
---|
| 930 | * void *arg) |
---|
| 931 | * rtems_device_driver console_write(rtems_device_major_number major, |
---|
| 932 | * rtems_device_minor_number minor, |
---|
| 933 | * void *arg) |
---|
| 934 | * rtems_device_driver console_control(rtems_device_major_number major, |
---|
| 935 | * rtems_device_minor_number minor, |
---|
| 936 | * void *arg) |
---|
| 937 | * |
---|
| 938 | */ |
---|