1 | /* |
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2 | * General Serial I/O functions. |
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3 | * |
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4 | * This file contains the functions for performing serial I/O. |
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5 | * The actual system calls (console_*) should be in the BSP part |
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6 | * of the source tree. That way different BSPs can use whichever |
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7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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8 | * this file, and it caused problems with one BSP using SCC2 |
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9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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10 | * |
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11 | * On-chip resources used: |
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12 | * resource minor note |
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13 | * SMC1 0 |
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14 | * SMC2 1 |
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15 | * SCC1 2 |
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16 | * SCC2 3 |
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17 | * SCC3 4 |
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18 | * SCC4 5 |
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19 | * BRG1 |
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20 | * BRG2 |
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21 | * BRG3 |
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22 | * BRG4 |
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23 | */ |
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24 | |
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25 | /* |
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26 | * Author: Jay Monkman (jmonkman@frasca.com) |
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27 | * Copyright (C) 1998 by Frasca International, Inc. |
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28 | * |
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29 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: |
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30 | * W. Eric Norum |
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31 | * Saskatchewan Accelerator Laboratory |
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32 | * University of Saskatchewan |
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33 | * Saskatoon, Saskatchewan, CANADA |
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34 | * eric@skatter.usask.ca |
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35 | * |
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36 | * COPYRIGHT (c) 1989-1998. |
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37 | * On-Line Applications Research Corporation (OAR). |
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38 | * |
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39 | * Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca> |
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40 | * and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> |
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41 | * Copyright (c) 1999, National Research Council of Canada |
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42 | * |
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43 | * Copyright (c) 2001, Surrey Satellite Technology Ltd |
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44 | * SCC1 and SSC2 are used on MPC8260ADS board |
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45 | * SMCs are unused |
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46 | * |
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47 | * The license and distribution terms for this file may be |
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48 | * found in the file LICENSE in this distribution or at |
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49 | * http://www.rtems.org/license/LICENSE. |
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50 | */ |
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51 | |
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52 | #include <bsp.h> |
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53 | #include <rtems/libio.h> |
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54 | #include <mpc8260.h> |
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55 | #include <mpc8260/console.h> |
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56 | #include <mpc8260/cpm.h> |
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57 | #include <stdlib.h> |
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58 | #include <unistd.h> |
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59 | #include <termios.h> |
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60 | #include <bsp/irq.h> |
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61 | #include <rtems/bspIo.h> /* for printk */ |
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62 | |
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63 | /* |
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64 | * Interrupt-driven input buffer |
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65 | */ |
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66 | #define RXBUFSIZE 16 |
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67 | |
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68 | /* |
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69 | * I/O buffers and pointers to buffer descriptors. |
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70 | * Currently, single buffered input is done. This will work only |
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71 | * if the Rx interrupts are serviced quickly. |
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72 | * |
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73 | * TODO: Add a least double buffering for safety. |
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74 | */ |
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75 | static volatile char rxBuf[NUM_PORTS][RXBUFSIZE]; |
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76 | static volatile char txBuf[NUM_PORTS]; |
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77 | |
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78 | /* SCC/SMC buffer descriptors */ |
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79 | static volatile m8260BufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS]; |
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80 | |
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81 | /* Used to track termios private data for callbacks */ |
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82 | struct rtems_termios_tty *ttyp[NUM_PORTS]; |
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83 | |
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84 | #if 0 |
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85 | /* Used to record previous ISR */ |
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86 | static rtems_isr_entry old_handler[NUM_PORTS]; |
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87 | #endif |
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88 | |
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89 | /* |
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90 | * Device-specific routines |
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91 | */ |
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92 | static int m8xx_smc_set_attributes(int, const struct termios*); |
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93 | static int m8xx_scc_set_attributes(int, const struct termios*); |
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94 | static rtems_isr m8xx_smc1_interrupt_handler(rtems_irq_hdl_param unused); |
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95 | static rtems_isr m8xx_smc2_interrupt_handler(rtems_irq_hdl_param unused); |
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96 | static rtems_isr m8xx_scc1_interrupt_handler(rtems_irq_hdl_param unused); |
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97 | static rtems_isr m8xx_scc2_interrupt_handler(rtems_irq_hdl_param unused); |
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98 | static rtems_isr m8xx_scc3_interrupt_handler(rtems_irq_hdl_param unused); |
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99 | static rtems_isr m8xx_scc4_interrupt_handler(rtems_irq_hdl_param unused); |
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100 | |
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101 | /* |
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102 | * Hardware-dependent portion of tcsetattr(). |
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103 | */ |
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104 | static int |
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105 | m8xx_smc_set_attributes (int minor, const struct termios *t) |
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106 | { |
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107 | int baud, brg=0, csize=0, ssize, psize; |
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108 | uint16_t clen=0, cstopb, parenb, parodd, cread; |
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109 | |
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110 | /* Baud rate */ |
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111 | switch (t->c_cflag & CBAUD) { |
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112 | default: baud = -1; break; |
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113 | case B50: baud = 50; break; |
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114 | case B75: baud = 75; break; |
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115 | case B110: baud = 110; break; |
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116 | case B134: baud = 134; break; |
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117 | case B150: baud = 150; break; |
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118 | case B200: baud = 200; break; |
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119 | case B300: baud = 300; break; |
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120 | case B600: baud = 600; break; |
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121 | case B1200: baud = 1200; break; |
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122 | case B1800: baud = 1800; break; |
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123 | case B2400: baud = 2400; break; |
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124 | case B4800: baud = 4800; break; |
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125 | case B9600: baud = 9600; break; |
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126 | case B19200: baud = 19200; break; |
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127 | case B38400: baud = 38400; break; |
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128 | case B57600: baud = 57600; break; |
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129 | case B115200: baud = 115200; break; |
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130 | case B230400: baud = 230400; break; |
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131 | case B460800: baud = 460800; break; |
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132 | } |
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133 | if (baud > 0) { |
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134 | switch( minor ) { |
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135 | case SMC1_MINOR: |
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136 | /* SMC1 can only choose between BRG1 and 7 */ |
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137 | brg = m8xx_get_brg( M8260_SMC1_BRGS, baud*16 ) + 1; |
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138 | m8260.cmxsmr &= ~0x30; |
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139 | m8260.cmxsmr |= (brg==1? 0x00: 0x10 ); |
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140 | break; |
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141 | case SMC2_MINOR: |
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142 | /* SMC2 can only choose between BRG2 and 8 */ |
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143 | brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; |
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144 | m8260.cmxsmr &= ~0x30; |
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145 | m8260.cmxsmr |= (brg==2? 0x00: 0x01 ); |
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146 | break; |
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147 | } |
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148 | } |
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149 | |
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150 | /* Number of data bits */ |
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151 | switch ( t->c_cflag & CSIZE ) { |
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152 | case CS5: csize = 5; break; |
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153 | case CS6: csize = 6; break; |
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154 | case CS7: csize = 7; break; |
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155 | case CS8: csize = 8; break; |
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156 | } |
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157 | |
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158 | /* Stop bits */ |
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159 | if ( t->c_cflag & CSTOPB ) { |
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160 | cstopb = 0x0400; /* Two stop bits */ |
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161 | ssize = 2; |
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162 | } else { |
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163 | cstopb = 0x0000; /* One stop bit */ |
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164 | ssize = 1; |
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165 | } |
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166 | |
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167 | /* Parity */ |
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168 | if ( t->c_cflag & PARENB ) { |
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169 | parenb = 0x0200; /* Parity enabled on Tx and Rx */ |
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170 | psize = 1; |
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171 | } else { |
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172 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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173 | psize = 0; |
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174 | } |
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175 | |
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176 | if ( t->c_cflag & PARODD ) |
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177 | parodd = 0x0000; /* Odd parity */ |
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178 | else |
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179 | parodd = 0x0100; |
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180 | |
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181 | /* |
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182 | * Character Length = start + data + parity + stop - 1 |
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183 | */ |
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184 | switch ( 1 + csize + psize + ssize - 1 ) { |
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185 | case 6: clen = 0x3000; break; |
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186 | case 7: clen = 0x3800; break; |
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187 | case 8: clen = 0x4000; break; |
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188 | case 9: clen = 0x4800; break; |
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189 | case 10: clen = 0x5000; break; |
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190 | case 11: clen = 0x5800; break; |
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191 | } |
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192 | |
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193 | if ( t->c_cflag & CREAD ) |
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194 | cread = 0x0023; /* UART normal operation, enable Rx and Tx */ |
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195 | else |
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196 | cread = 0x0021; /* UART normal operation, enable Tx */ |
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197 | |
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198 | /* Write the SIMODE/SMCMR registers */ |
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199 | switch (minor) { |
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200 | case SMC1_MINOR: |
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201 | /* |
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202 | m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) ); |
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203 | */ |
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204 | m8260.smc1.smcmr = clen | cstopb | parenb | parodd | cread; |
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205 | break; |
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206 | case SMC2_MINOR: |
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207 | /* CHECK THIS */ |
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208 | /* |
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209 | m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) ); |
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210 | */ |
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211 | m8260.smc2.smcmr = clen | cstopb | parenb | parodd | cread; |
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212 | break; |
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213 | } |
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214 | return 0; |
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215 | } |
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216 | |
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217 | static int |
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218 | m8xx_scc_set_attributes (int minor, const struct termios *t) |
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219 | { |
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220 | int baud, brg=0; |
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221 | uint16_t csize=0, cstopb, parenb, parodd; |
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222 | |
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223 | /* Baud rate */ |
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224 | switch (t->c_cflag & CBAUD) { |
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225 | default: baud = -1; break; |
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226 | case B50: baud = 50; break; |
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227 | case B75: baud = 75; break; |
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228 | case B110: baud = 110; break; |
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229 | case B134: baud = 134; break; |
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230 | case B150: baud = 150; break; |
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231 | case B200: baud = 200; break; |
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232 | case B300: baud = 300; break; |
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233 | case B600: baud = 600; break; |
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234 | case B1200: baud = 1200; break; |
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235 | case B1800: baud = 1800; break; |
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236 | case B2400: baud = 2400; break; |
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237 | case B4800: baud = 4800; break; |
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238 | case B9600: baud = 9600; break; |
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239 | case B19200: baud = 19200; break; |
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240 | case B38400: baud = 38400; break; |
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241 | case B57600: baud = 57600; break; |
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242 | case B115200: baud = 115200; break; |
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243 | case B230400: baud = 230400; break; |
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244 | case B460800: baud = 460800; break; |
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245 | } |
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246 | if (baud > 0) { |
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247 | brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); |
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248 | m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); |
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249 | m8260.cmxscr |= ((brg<<(3+8*(3-(minor-SCC1_MINOR)))) & |
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250 | (brg<<(8*(3-(minor-SCC1_MINOR))))); |
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251 | } |
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252 | /* Number of data bits */ |
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253 | switch ( t->c_cflag & CSIZE ) { |
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254 | case CS5: csize = 0x0000; break; |
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255 | case CS6: csize = 0x1000; break; |
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256 | case CS7: csize = 0x2000; break; |
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257 | case CS8: csize = 0x3000; break; |
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258 | } |
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259 | |
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260 | /* Stop bits */ |
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261 | if ( t->c_cflag & CSTOPB ) |
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262 | cstopb = 0x4000; /* Two stop bits */ |
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263 | else |
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264 | cstopb = 0x0000; /* One stop bit */ |
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265 | |
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266 | /* Parity */ |
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267 | if ( t->c_cflag & PARENB ) |
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268 | parenb = 0x0010; /* Parity enabled on Tx and Rx */ |
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269 | else |
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270 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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271 | |
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272 | if ( t->c_cflag & PARODD ) |
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273 | parodd = 0x0000; /* Odd parity */ |
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274 | else |
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275 | parodd = 0x000a; |
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276 | |
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277 | /* Write the SICR/PSMR Registers */ |
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278 | switch (minor) { |
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279 | case SCC1_MINOR: |
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280 | /* |
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281 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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282 | */ |
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283 | m8260.scc1.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc1.psmr & 0x8fe0) ); |
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284 | break; |
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285 | case SCC2_MINOR: |
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286 | /* |
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287 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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288 | */ |
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289 | m8260.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc2.psmr & 0x8fe0) ); |
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290 | break; |
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291 | case SCC3_MINOR: |
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292 | /* |
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293 | m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) ); |
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294 | */ |
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295 | m8260.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc3.psmr & 0x8fe0) ); |
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296 | break; |
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297 | case SCC4_MINOR: |
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298 | /* |
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299 | m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) ); |
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300 | */ |
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301 | m8260.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc4.psmr & 0x8fe0) ); |
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302 | break; |
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303 | } |
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304 | |
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305 | return 0; |
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306 | } |
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307 | |
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308 | int |
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309 | m8xx_uart_setAttributes( |
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310 | int minor, |
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311 | const struct termios *t |
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312 | ) |
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313 | { |
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314 | /* |
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315 | * Check that port number is valid |
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316 | */ |
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317 | if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) |
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318 | return 0; |
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319 | |
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320 | switch (minor) { |
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321 | case SMC1_MINOR: |
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322 | case SMC2_MINOR: |
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323 | return m8xx_smc_set_attributes( minor, t ); |
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324 | |
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325 | case SCC1_MINOR: |
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326 | case SCC2_MINOR: |
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327 | case SCC3_MINOR: |
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328 | case SCC4_MINOR: |
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329 | return m8xx_scc_set_attributes( minor, t ); |
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330 | } |
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331 | return 0; |
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332 | } |
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333 | |
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334 | /* |
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335 | * Interrupt handlers |
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336 | */ |
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337 | static void |
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338 | m8xx_scc1_interrupt_handler (rtems_irq_hdl_param unused) |
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339 | { |
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340 | /* |
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341 | * Buffer received? |
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342 | */ |
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343 | if ((m8260.scc1.sccm & M8260_SCCE_RX) && (m8260.scc1.scce & M8260_SCCE_RX)) { |
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344 | m8260.scc1.scce = M8260_SCCE_RX; /* Clear the event */ |
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345 | |
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346 | |
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347 | /* Check that the buffer is ours */ |
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348 | if ((RxBd[SCC1_MINOR]->status & M8260_BD_EMPTY) == 0) { |
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349 | rtems_cache_invalidate_multiple_data_lines( |
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350 | (const void *) RxBd[SCC1_MINOR]->buffer, |
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351 | RxBd[SCC1_MINOR]->length ); |
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352 | rtems_termios_enqueue_raw_characters( |
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353 | (void *)ttyp[SCC1_MINOR], |
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354 | (char *)RxBd[SCC1_MINOR]->buffer, |
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355 | (int)RxBd[SCC1_MINOR]->length ); |
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356 | RxBd[SCC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
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357 | M8260_BD_INTERRUPT; |
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358 | } |
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359 | } |
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360 | |
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361 | /* |
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362 | * Buffer transmitted? |
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363 | */ |
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364 | if (m8260.scc1.scce & M8260_SCCE_TX) { |
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365 | m8260.scc1.scce = M8260_SCCE_TX; /* Clear the event */ |
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366 | |
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367 | /* Check that the buffer is ours */ |
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368 | if ((TxBd[SCC1_MINOR]->status & M8260_BD_READY) == 0) |
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369 | rtems_termios_dequeue_characters ( |
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370 | (void *)ttyp[SCC1_MINOR], |
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371 | (int)TxBd[SCC1_MINOR]->length); |
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372 | } |
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373 | |
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374 | #if 0 |
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375 | m8260.sipnr_l |= M8260_SIMASK_SCC1; /* Clear pending register */ |
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376 | #endif |
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377 | } |
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378 | |
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379 | static void |
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380 | m8xx_scc2_interrupt_handler (rtems_irq_hdl_param unused) |
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381 | { |
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382 | /* |
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383 | * Buffer received? |
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384 | */ |
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385 | if ((m8260.scc2.sccm & M8260_SCCE_RX) && (m8260.scc2.scce & M8260_SCCE_RX)) { |
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386 | m8260.scc2.scce = M8260_SCCE_RX; /* Clear the event */ |
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387 | |
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388 | |
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389 | /* Check that the buffer is ours */ |
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390 | if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) { |
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391 | rtems_cache_invalidate_multiple_data_lines( |
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392 | (const void *) RxBd[SCC2_MINOR]->buffer, |
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393 | RxBd[SCC2_MINOR]->length ); |
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394 | rtems_termios_enqueue_raw_characters( |
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395 | (void *)ttyp[SCC2_MINOR], |
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396 | (char *)RxBd[SCC2_MINOR]->buffer, |
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397 | (int)RxBd[SCC2_MINOR]->length ); |
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398 | RxBd[SCC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
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399 | M8260_BD_INTERRUPT; |
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400 | } |
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401 | } |
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402 | |
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403 | /* |
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404 | * Buffer transmitted? |
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405 | */ |
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406 | if (m8260.scc2.scce & M8260_SCCE_TX) { |
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407 | m8260.scc2.scce = M8260_SCCE_TX; /* Clear the event */ |
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408 | |
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409 | /* Check that the buffer is ours */ |
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410 | if ((TxBd[SCC2_MINOR]->status & M8260_BD_READY) == 0) |
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411 | rtems_termios_dequeue_characters ( |
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412 | (void *)ttyp[SCC2_MINOR], |
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413 | (int)TxBd[SCC2_MINOR]->length); |
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414 | } |
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415 | |
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416 | #if 0 |
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417 | m8260.sipnr_l |= M8260_SIMASK_SCC2; /* Clear pending register */ |
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418 | #endif |
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419 | } |
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420 | |
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421 | static void |
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422 | m8xx_scc3_interrupt_handler (rtems_irq_hdl_param unused) |
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423 | { |
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424 | /* |
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425 | * Buffer received? |
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426 | */ |
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427 | if ((m8260.scc3.sccm & M8260_SCCE_RX) && (m8260.scc3.scce & M8260_SCCE_RX)) { |
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428 | m8260.scc3.scce = M8260_SCCE_RX; /* Clear the event */ |
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429 | |
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430 | |
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431 | /* Check that the buffer is ours */ |
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432 | if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) { |
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433 | rtems_cache_invalidate_multiple_data_lines( |
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434 | (const void *) RxBd[SCC3_MINOR]->buffer, |
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435 | RxBd[SCC3_MINOR]->length ); |
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436 | rtems_termios_enqueue_raw_characters( |
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437 | (void *)ttyp[SCC3_MINOR], |
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438 | (char *)RxBd[SCC3_MINOR]->buffer, |
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439 | (int)RxBd[SCC3_MINOR]->length ); |
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440 | RxBd[SCC3_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
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441 | M8260_BD_INTERRUPT; |
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442 | } |
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443 | } |
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444 | |
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445 | /* |
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446 | * Buffer transmitted? |
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447 | */ |
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448 | if (m8260.scc3.scce & M8260_SCCE_TX) { |
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449 | m8260.scc3.scce = M8260_SCCE_TX; /* Clear the event */ |
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450 | |
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451 | /* Check that the buffer is ours */ |
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452 | if ((TxBd[SCC3_MINOR]->status & M8260_BD_READY) == 0) |
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453 | rtems_termios_dequeue_characters ( |
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454 | (void *)ttyp[SCC3_MINOR], |
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455 | (int)TxBd[SCC3_MINOR]->length); |
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456 | } |
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457 | |
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458 | |
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459 | #if 0 |
---|
460 | m8260.sipnr_l |= M8260_SIMASK_SCC3; /* Clear pending register */ |
---|
461 | #endif |
---|
462 | } |
---|
463 | |
---|
464 | static void |
---|
465 | m8xx_scc4_interrupt_handler (rtems_irq_hdl_param unused) |
---|
466 | { |
---|
467 | /* |
---|
468 | * Buffer received? |
---|
469 | */ |
---|
470 | if ((m8260.scc4.sccm & M8260_SCCE_RX) && (m8260.scc4.scce & M8260_SCCE_RX)) { |
---|
471 | m8260.scc4.scce = M8260_SCCE_RX; /* Clear the event */ |
---|
472 | |
---|
473 | |
---|
474 | /* Check that the buffer is ours */ |
---|
475 | if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
476 | rtems_cache_invalidate_multiple_data_lines( |
---|
477 | (const void *) RxBd[SCC4_MINOR]->buffer, |
---|
478 | RxBd[SCC4_MINOR]->length ); |
---|
479 | rtems_termios_enqueue_raw_characters( |
---|
480 | (void *)ttyp[SCC4_MINOR], |
---|
481 | (char *)RxBd[SCC4_MINOR]->buffer, |
---|
482 | (int)RxBd[SCC4_MINOR]->length ); |
---|
483 | RxBd[SCC4_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
484 | M8260_BD_INTERRUPT; |
---|
485 | } |
---|
486 | } |
---|
487 | |
---|
488 | /* |
---|
489 | * Buffer transmitted? |
---|
490 | */ |
---|
491 | if (m8260.scc4.scce & M8260_SCCE_TX) { |
---|
492 | m8260.scc4.scce = M8260_SCCE_TX; /* Clear the event */ |
---|
493 | |
---|
494 | /* Check that the buffer is ours */ |
---|
495 | if ((TxBd[SCC4_MINOR]->status & M8260_BD_READY) == 0) |
---|
496 | rtems_termios_dequeue_characters ( |
---|
497 | (void *)ttyp[SCC4_MINOR], |
---|
498 | (int)TxBd[SCC4_MINOR]->length); |
---|
499 | } |
---|
500 | |
---|
501 | #if 0 |
---|
502 | m8260.sipnr_l |= M8260_SIMASK_SCC4; /* Clear pending register */ |
---|
503 | #endif |
---|
504 | } |
---|
505 | |
---|
506 | static void |
---|
507 | m8xx_smc1_interrupt_handler (rtems_irq_hdl_param unused) |
---|
508 | { |
---|
509 | /* |
---|
510 | * Buffer received? |
---|
511 | */ |
---|
512 | if (m8260.smc1.smce & M8260_SMCE_RX) { |
---|
513 | m8260.smc1.smce = M8260_SMCE_RX; /* Clear the event */ |
---|
514 | |
---|
515 | |
---|
516 | /* Check that the buffer is ours */ |
---|
517 | if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
518 | rtems_cache_invalidate_multiple_data_lines( |
---|
519 | (const void *) RxBd[SMC1_MINOR]->buffer, |
---|
520 | RxBd[SMC1_MINOR]->length ); |
---|
521 | rtems_termios_enqueue_raw_characters( |
---|
522 | (void *)ttyp[SMC1_MINOR], |
---|
523 | (char *)RxBd[SMC1_MINOR]->buffer, |
---|
524 | (int)RxBd[SMC1_MINOR]->length ); |
---|
525 | RxBd[SMC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
526 | M8260_BD_INTERRUPT; |
---|
527 | } |
---|
528 | } |
---|
529 | |
---|
530 | /* |
---|
531 | * Buffer transmitted? |
---|
532 | */ |
---|
533 | if (m8260.smc1.smce & M8260_SMCE_TX) { |
---|
534 | m8260.smc1.smce = M8260_SMCE_TX; /* Clear the event */ |
---|
535 | |
---|
536 | /* Check that the buffer is ours */ |
---|
537 | if ((TxBd[SMC1_MINOR]->status & M8260_BD_READY) == 0) |
---|
538 | rtems_termios_dequeue_characters ( |
---|
539 | (void *)ttyp[SMC1_MINOR], |
---|
540 | (int)TxBd[SMC1_MINOR]->length); |
---|
541 | } |
---|
542 | |
---|
543 | #if 0 |
---|
544 | m8260.sipnr_l = 0x00001000; /* Clear SMC1 interrupt-in-service bit */ |
---|
545 | #endif |
---|
546 | } |
---|
547 | |
---|
548 | static void |
---|
549 | m8xx_smc2_interrupt_handler (rtems_irq_hdl_param unused) |
---|
550 | { |
---|
551 | /* |
---|
552 | * Buffer received? |
---|
553 | */ |
---|
554 | if (m8260.smc2.smce & M8260_SMCE_RX) { |
---|
555 | m8260.smc2.smce = M8260_SMCE_RX; /* Clear the event */ |
---|
556 | |
---|
557 | |
---|
558 | /* Check that the buffer is ours */ |
---|
559 | if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
560 | rtems_cache_invalidate_multiple_data_lines( |
---|
561 | (const void *) RxBd[SMC2_MINOR]->buffer, |
---|
562 | RxBd[SMC2_MINOR]->length ); |
---|
563 | rtems_termios_enqueue_raw_characters( |
---|
564 | (void *)ttyp[SMC2_MINOR], |
---|
565 | (char *)RxBd[SMC2_MINOR]->buffer, |
---|
566 | (int)RxBd[SMC2_MINOR]->length ); |
---|
567 | RxBd[SMC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
568 | M8260_BD_INTERRUPT; |
---|
569 | } |
---|
570 | } |
---|
571 | |
---|
572 | /* |
---|
573 | * Buffer transmitted? |
---|
574 | */ |
---|
575 | if (m8260.smc2.smce & M8260_SMCE_TX) { |
---|
576 | m8260.smc2.smce = M8260_SMCE_TX; /* Clear the event */ |
---|
577 | |
---|
578 | /* Check that the buffer is ours */ |
---|
579 | if ((TxBd[SMC2_MINOR]->status & M8260_BD_READY) == 0) |
---|
580 | rtems_termios_dequeue_characters ( |
---|
581 | (void *)ttyp[SMC2_MINOR], |
---|
582 | (int)TxBd[SMC2_MINOR]->length); |
---|
583 | } |
---|
584 | |
---|
585 | #if 0 |
---|
586 | m8260.sipnr_l = 0x00000800; /* Clear SMC2 interrupt-in-service bit */ |
---|
587 | #endif |
---|
588 | } |
---|
589 | |
---|
590 | static void m8xx_scc_enable(const rtems_irq_connect_data* ptr) |
---|
591 | { |
---|
592 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
593 | switch (ptr->name) { |
---|
594 | case BSP_CPM_IRQ_SCC4 : |
---|
595 | m8260.sipnr_l |= M8260_SIMASK_SCC4; |
---|
596 | sccregs = &m8260.scc4; |
---|
597 | break; |
---|
598 | case BSP_CPM_IRQ_SCC3 : |
---|
599 | m8260.sipnr_l |= M8260_SIMASK_SCC3; |
---|
600 | sccregs = &m8260.scc3; |
---|
601 | break; |
---|
602 | case BSP_CPM_IRQ_SCC2 : |
---|
603 | m8260.sipnr_l |= M8260_SIMASK_SCC2; |
---|
604 | sccregs = &m8260.scc2; |
---|
605 | break; |
---|
606 | case BSP_CPM_IRQ_SCC1 : |
---|
607 | m8260.sipnr_l |= M8260_SIMASK_SCC1; |
---|
608 | sccregs = &m8260.scc1; |
---|
609 | break; |
---|
610 | default: |
---|
611 | break; |
---|
612 | } |
---|
613 | sccregs->sccm = 3; |
---|
614 | } |
---|
615 | |
---|
616 | static void m8xx_scc_disable(const rtems_irq_connect_data* ptr) |
---|
617 | { |
---|
618 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
619 | switch (ptr->name) { |
---|
620 | case BSP_CPM_IRQ_SCC4 : |
---|
621 | sccregs = &m8260.scc4; |
---|
622 | break; |
---|
623 | case BSP_CPM_IRQ_SCC3 : |
---|
624 | sccregs = &m8260.scc3; |
---|
625 | break; |
---|
626 | case BSP_CPM_IRQ_SCC2 : |
---|
627 | sccregs = &m8260.scc2; |
---|
628 | break; |
---|
629 | case BSP_CPM_IRQ_SCC1 : |
---|
630 | sccregs = &m8260.scc1; |
---|
631 | break; |
---|
632 | default: |
---|
633 | break; |
---|
634 | } |
---|
635 | sccregs->sccm &= (~3); |
---|
636 | } |
---|
637 | |
---|
638 | static int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) |
---|
639 | { |
---|
640 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
641 | } |
---|
642 | |
---|
643 | static rtems_irq_connect_data consoleIrqData = |
---|
644 | { |
---|
645 | BSP_CPM_IRQ_SCC1, |
---|
646 | (rtems_irq_hdl)m8xx_scc1_interrupt_handler, |
---|
647 | NULL, |
---|
648 | (rtems_irq_enable) m8xx_scc_enable, |
---|
649 | (rtems_irq_disable) m8xx_scc_disable, |
---|
650 | (rtems_irq_is_enabled) m8xx_scc_isOn |
---|
651 | }; |
---|
652 | |
---|
653 | void |
---|
654 | m8xx_uart_scc_initialize (int minor) |
---|
655 | { |
---|
656 | unsigned char brg; |
---|
657 | volatile m8260SCCparms_t *sccparms = 0; |
---|
658 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
659 | |
---|
660 | /* |
---|
661 | * Check that minor number is valid |
---|
662 | */ |
---|
663 | if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) |
---|
664 | return; |
---|
665 | |
---|
666 | /* Get the sicr clock source bit values for 9600 bps */ |
---|
667 | brg = m8xx_get_brg(M8260_SCC_BRGS, 9600*16); |
---|
668 | |
---|
669 | m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); |
---|
670 | m8260.cmxscr |= (brg<<(3+8*(3-(minor-SCC1_MINOR)))); |
---|
671 | m8260.cmxscr |= (brg<<(8*(3-(minor-SCC1_MINOR)))); |
---|
672 | |
---|
673 | /* |
---|
674 | * Allocate buffer descriptors |
---|
675 | */ |
---|
676 | RxBd[minor] = m8xx_bd_allocate(1); |
---|
677 | TxBd[minor] = m8xx_bd_allocate(1); |
---|
678 | |
---|
679 | /* |
---|
680 | * Configure ports to enable TXDx and RXDx pins |
---|
681 | */ |
---|
682 | |
---|
683 | m8260.ppard |= (0x07 << ((minor-SCC1_MINOR)*3)); |
---|
684 | m8260.psord &= ~(0x07 << ((minor-SCC1_MINOR)*3)); |
---|
685 | if( minor == SCC1_MINOR ) |
---|
686 | m8260.psord |= 0x02; |
---|
687 | m8260.pdird |= (0x06 << ((minor-SCC1_MINOR)*3)); |
---|
688 | m8260.pdird &= ~(0x01 << ((minor-SCC1_MINOR)*3)); |
---|
689 | |
---|
690 | |
---|
691 | /* |
---|
692 | * Set up SMC1 parameter RAM common to all protocols |
---|
693 | */ |
---|
694 | if( minor == SCC1_MINOR ) { |
---|
695 | sccparms = (m8260SCCparms_t*)&m8260.scc1p; |
---|
696 | sccregs = (m8260SCCRegisters_t*)&m8260.scc1; |
---|
697 | } |
---|
698 | else if( minor == SCC2_MINOR ) { |
---|
699 | sccparms = (m8260SCCparms_t*)&m8260.scc2p; |
---|
700 | sccregs = (m8260SCCRegisters_t*)&m8260.scc2; |
---|
701 | } |
---|
702 | else if( minor == SCC3_MINOR ) { |
---|
703 | sccparms = (m8260SCCparms_t*)&m8260.scc3p; |
---|
704 | sccregs = (m8260SCCRegisters_t*)&m8260.scc3; |
---|
705 | } |
---|
706 | else { |
---|
707 | sccparms = (m8260SCCparms_t*)&m8260.scc4p; |
---|
708 | sccregs = (m8260SCCRegisters_t*)&m8260.scc4; |
---|
709 | } |
---|
710 | |
---|
711 | sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260; |
---|
712 | sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260; |
---|
713 | |
---|
714 | sccparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; |
---|
715 | sccparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; |
---|
716 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
717 | sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
718 | else |
---|
719 | sccparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
720 | sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
721 | sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
722 | |
---|
723 | sccparms->un.uart.parec = 0; /* Clear parity error counter */ |
---|
724 | sccparms->un.uart.frmec = 0; /* Clear framing error counter */ |
---|
725 | sccparms->un.uart.nosec = 0; /* Clear noise counter */ |
---|
726 | sccparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
727 | |
---|
728 | sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */ |
---|
729 | sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */ |
---|
730 | sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */ |
---|
731 | |
---|
732 | sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */ |
---|
733 | sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */ |
---|
734 | sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */ |
---|
735 | sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */ |
---|
736 | sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */ |
---|
737 | sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */ |
---|
738 | sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */ |
---|
739 | sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */ |
---|
740 | |
---|
741 | sccparms->un.uart.rccm = 0xc0ff; /* No masking */ |
---|
742 | |
---|
743 | /* |
---|
744 | * Set up the Receive Buffer Descriptor |
---|
745 | */ |
---|
746 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
747 | RxBd[minor]->length = 0; |
---|
748 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
749 | |
---|
750 | /* |
---|
751 | * Setup the Transmit Buffer Descriptor |
---|
752 | */ |
---|
753 | TxBd[minor]->status = M8260_BD_WRAP; |
---|
754 | |
---|
755 | /* |
---|
756 | * Set up SCCx general and protocol-specific mode registers |
---|
757 | */ |
---|
758 | sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */ |
---|
759 | sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/ |
---|
760 | sccregs->scce = ~0; /* Clear any pending event */ |
---|
761 | sccregs->sccm = 0; /* Mask all interrupt/event sources */ |
---|
762 | sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit, |
---|
763 | 8 data bits, no parity */ |
---|
764 | sccregs->dsr = 0x7E7E; /* No fractional stop bits */ |
---|
765 | sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */ |
---|
766 | |
---|
767 | /* |
---|
768 | * Initialize the Rx and Tx with the new parameters. |
---|
769 | */ |
---|
770 | switch (minor) { |
---|
771 | case SCC1_MINOR: |
---|
772 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC1); |
---|
773 | break; |
---|
774 | case SCC2_MINOR: |
---|
775 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC2); |
---|
776 | break; |
---|
777 | case SCC3_MINOR: |
---|
778 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3); |
---|
779 | break; |
---|
780 | case SCC4_MINOR: |
---|
781 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC4); |
---|
782 | break; |
---|
783 | } |
---|
784 | |
---|
785 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
786 | switch (minor) { |
---|
787 | case SCC1_MINOR: |
---|
788 | consoleIrqData.name = BSP_CPM_IRQ_SCC1; |
---|
789 | consoleIrqData.hdl = m8xx_scc1_interrupt_handler; |
---|
790 | break; |
---|
791 | case SCC2_MINOR: |
---|
792 | consoleIrqData.name = BSP_CPM_IRQ_SCC2; |
---|
793 | consoleIrqData.hdl = m8xx_scc2_interrupt_handler; |
---|
794 | break; |
---|
795 | case SCC3_MINOR: |
---|
796 | consoleIrqData.name = BSP_CPM_IRQ_SCC3; |
---|
797 | consoleIrqData.hdl = m8xx_scc3_interrupt_handler; |
---|
798 | break; |
---|
799 | case SCC4_MINOR: |
---|
800 | consoleIrqData.name = BSP_CPM_IRQ_SCC4; |
---|
801 | consoleIrqData.hdl = m8xx_scc4_interrupt_handler; |
---|
802 | break; |
---|
803 | |
---|
804 | } |
---|
805 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
806 | printk("Unable to connect SCC Irq handler\n"); |
---|
807 | rtems_fatal_error_occurred(1); |
---|
808 | } |
---|
809 | } |
---|
810 | } |
---|
811 | |
---|
812 | static void m8xx_smc_enable(const rtems_irq_connect_data* ptr) |
---|
813 | { |
---|
814 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
815 | switch (ptr->name) { |
---|
816 | case BSP_CPM_IRQ_SMC1 : |
---|
817 | smcregs = &m8260.smc1; |
---|
818 | break; |
---|
819 | case BSP_CPM_IRQ_SMC2 : |
---|
820 | smcregs = &m8260.smc2; |
---|
821 | break; |
---|
822 | default: |
---|
823 | break; |
---|
824 | } |
---|
825 | smcregs->smcm = 3; |
---|
826 | } |
---|
827 | |
---|
828 | static void m8xx_smc_disable(const rtems_irq_connect_data* ptr) |
---|
829 | { |
---|
830 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
831 | switch (ptr->name) { |
---|
832 | case BSP_CPM_IRQ_SMC1 : |
---|
833 | smcregs = &m8260.smc1; |
---|
834 | break; |
---|
835 | case BSP_CPM_IRQ_SMC2 : |
---|
836 | smcregs = &m8260.smc2; |
---|
837 | break; |
---|
838 | default: |
---|
839 | break; |
---|
840 | } |
---|
841 | smcregs->smcm &= (~3); |
---|
842 | } |
---|
843 | |
---|
844 | static int m8xx_smc_isOn(const rtems_irq_connect_data* ptr) |
---|
845 | { |
---|
846 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
847 | } |
---|
848 | |
---|
849 | void |
---|
850 | m8xx_uart_smc_initialize (int minor) |
---|
851 | { |
---|
852 | unsigned char brg; |
---|
853 | volatile m8260SMCparms_t *smcparms = 0; |
---|
854 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
855 | |
---|
856 | /* |
---|
857 | * Check that minor number is valid |
---|
858 | */ |
---|
859 | if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) |
---|
860 | return; |
---|
861 | |
---|
862 | /* Get the simode clock source bit values for 9600 bps */ |
---|
863 | if( minor == SMC1_MINOR ) |
---|
864 | brg = m8xx_get_brg(M8260_SMC1_BRGS, 9600*16); |
---|
865 | else |
---|
866 | brg = m8xx_get_brg(M8260_SMC2_BRGS, 9600*16); |
---|
867 | (void) brg; /* avoid set but not used warning */ |
---|
868 | |
---|
869 | /* |
---|
870 | * Allocate buffer descriptors |
---|
871 | */ |
---|
872 | RxBd[minor] = m8xx_bd_allocate (1); |
---|
873 | TxBd[minor] = m8xx_bd_allocate (1); |
---|
874 | |
---|
875 | /* |
---|
876 | * Get the address of the parameter RAM for the specified port, |
---|
877 | * configure I/O port B and put SMC in NMSI mode, connect the |
---|
878 | * SMC to the appropriate BRG. |
---|
879 | * |
---|
880 | * SMC2 RxD is shared with port B bit 20 |
---|
881 | * SMC2 TxD is shared with port B bit 21 |
---|
882 | * SMC1 RxD is shared with port B bit 24 |
---|
883 | * SMC1 TxD is shared with port B bit 25 |
---|
884 | */ |
---|
885 | switch (minor) { |
---|
886 | case SMC1_MINOR: |
---|
887 | smcparms = &m8260.smc1p; |
---|
888 | smcregs = &m8260.smc1; |
---|
889 | |
---|
890 | #if 0 |
---|
891 | m8260.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ |
---|
892 | m8260.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ |
---|
893 | m8260.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ |
---|
894 | |
---|
895 | m8260.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */ |
---|
896 | m8260.simode |= brg << 12; /* SMC1CS = brg */ |
---|
897 | #endif |
---|
898 | break; |
---|
899 | |
---|
900 | case SMC2_MINOR: |
---|
901 | smcparms = &m8260.smc2p; |
---|
902 | smcregs = &m8260.smc2; |
---|
903 | #if 0 |
---|
904 | m8260.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ |
---|
905 | m8260.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ |
---|
906 | m8260.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ |
---|
907 | |
---|
908 | m8260.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ |
---|
909 | m8260.simode |= brg << 28; /* SMC2CS = brg */ |
---|
910 | #endif |
---|
911 | break; |
---|
912 | } |
---|
913 | |
---|
914 | /* |
---|
915 | * Set up SMC parameter RAM common to all protocols |
---|
916 | */ |
---|
917 | smcparms->rbase = (char *)RxBd[minor] - (char *)&m8260; |
---|
918 | smcparms->tbase = (char *)TxBd[minor] - (char *)&m8260; |
---|
919 | smcparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; |
---|
920 | smcparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; |
---|
921 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
922 | smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
923 | else |
---|
924 | smcparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
925 | |
---|
926 | /* |
---|
927 | * Set up SMC1 parameter RAM UART-specific parameters |
---|
928 | */ |
---|
929 | smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
930 | smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
931 | smcparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
932 | |
---|
933 | /* |
---|
934 | * Set up the Receive Buffer Descriptor |
---|
935 | */ |
---|
936 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
937 | RxBd[minor]->length = 0; |
---|
938 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
939 | |
---|
940 | /* |
---|
941 | * Setup the Transmit Buffer Descriptor |
---|
942 | */ |
---|
943 | TxBd[minor]->status = M8260_BD_WRAP; |
---|
944 | |
---|
945 | /* |
---|
946 | * Set up SMCx general and protocol-specific mode registers |
---|
947 | */ |
---|
948 | smcregs->smce = ~0; /* Clear any pending events */ |
---|
949 | smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */ |
---|
950 | smcregs->smcmr = M8260_SMCMR_CLEN(9) | M8260_SMCMR_SM_UART; |
---|
951 | |
---|
952 | /* |
---|
953 | * Send "Init parameters" command |
---|
954 | */ |
---|
955 | switch (minor) { |
---|
956 | case SMC1_MINOR: |
---|
957 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC1); |
---|
958 | break; |
---|
959 | |
---|
960 | case SMC2_MINOR: |
---|
961 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC2); |
---|
962 | break; |
---|
963 | } |
---|
964 | |
---|
965 | /* |
---|
966 | * Enable receiver and transmitter |
---|
967 | */ |
---|
968 | smcregs->smcmr |= M8260_SMCMR_TEN | M8260_SMCMR_REN; |
---|
969 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
970 | consoleIrqData.on = m8xx_smc_enable; |
---|
971 | consoleIrqData.off = m8xx_smc_disable; |
---|
972 | consoleIrqData.isOn = m8xx_smc_isOn; |
---|
973 | switch (minor) { |
---|
974 | case SMC1_MINOR: |
---|
975 | consoleIrqData.name = BSP_CPM_IRQ_SMC1; |
---|
976 | consoleIrqData.hdl = m8xx_smc1_interrupt_handler; |
---|
977 | break; |
---|
978 | |
---|
979 | case SMC2_MINOR: |
---|
980 | consoleIrqData.name = BSP_CPM_IRQ_SMC2; |
---|
981 | consoleIrqData.hdl = m8xx_smc2_interrupt_handler; |
---|
982 | break; |
---|
983 | #if 0 |
---|
984 | case SMC1_MINOR: |
---|
985 | rtems_interrupt_catch (m8xx_smc1_interrupt_handler, |
---|
986 | PPC_IRQ_CPM_SMC1, |
---|
987 | &old_handler[minor]); |
---|
988 | |
---|
989 | smcregs->smcm = 3; /* Enable SMC1 Rx & Tx interrupts */ |
---|
990 | m8260.sipnr_l |= M8260_SIMASK_SMC1; /* Clear pending register */ |
---|
991 | m8260.simr_l |= M8260_SIMASK_SMC1; /* Enable SMC1 interrupts */ |
---|
992 | break; |
---|
993 | |
---|
994 | case SMC2_MINOR: |
---|
995 | rtems_interrupt_catch (m8xx_smc2_interrupt_handler, |
---|
996 | PPC_IRQ_CPM_SMC2, |
---|
997 | &old_handler[minor]); |
---|
998 | |
---|
999 | smcregs->smcm = 3; /* Enable SMC2 Rx & Tx interrupts */ |
---|
1000 | m8260.sipnr_l |= M8260_SIMASK_SMC2; /* Clear pending register */ |
---|
1001 | m8260.simr_l |= M8260_SIMASK_SMC2; /* Enable SMC2 interrupts */ |
---|
1002 | break; |
---|
1003 | #endif |
---|
1004 | } |
---|
1005 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
1006 | printk("Unable to connect SMC Irq handler\n"); |
---|
1007 | rtems_fatal_error_occurred(1); |
---|
1008 | } |
---|
1009 | } |
---|
1010 | } |
---|
1011 | |
---|
1012 | void |
---|
1013 | m8xx_uart_initialize(void) |
---|
1014 | { |
---|
1015 | } |
---|
1016 | |
---|
1017 | void |
---|
1018 | m8xx_uart_interrupts_initialize(void) |
---|
1019 | { |
---|
1020 | #ifdef mpc8260 |
---|
1021 | /* CHECK THIS */ |
---|
1022 | |
---|
1023 | #else |
---|
1024 | |
---|
1025 | #if defined(mpc860) |
---|
1026 | m8xx.cicr = 0x00E43F80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
1027 | SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */ |
---|
1028 | #else |
---|
1029 | m8xx.cicr = 0x00043F80; /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */ |
---|
1030 | #endif |
---|
1031 | m8xx.simask |= M8xx_SIMASK_LVM1; /* Enable level interrupts */ |
---|
1032 | #endif |
---|
1033 | } |
---|
1034 | |
---|
1035 | int |
---|
1036 | m8xx_uart_pollRead( |
---|
1037 | int minor |
---|
1038 | ) |
---|
1039 | { |
---|
1040 | unsigned char c; |
---|
1041 | |
---|
1042 | if (RxBd[minor]->status & M8260_BD_EMPTY) { |
---|
1043 | return -1; |
---|
1044 | } |
---|
1045 | rtems_cache_invalidate_multiple_data_lines( |
---|
1046 | (const void *) RxBd[minor]->buffer, |
---|
1047 | RxBd[minor]->length |
---|
1048 | ); |
---|
1049 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
1050 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP; |
---|
1051 | return c; |
---|
1052 | } |
---|
1053 | |
---|
1054 | /* |
---|
1055 | * TODO: Get a free buffer and set it up. |
---|
1056 | */ |
---|
1057 | ssize_t |
---|
1058 | m8xx_uart_write( |
---|
1059 | int minor, |
---|
1060 | const char *buf, |
---|
1061 | size_t len |
---|
1062 | ) |
---|
1063 | { |
---|
1064 | if (len > 0) { |
---|
1065 | while( (TxBd[minor]->status) & M8260_BD_READY ); |
---|
1066 | |
---|
1067 | rtems_cache_flush_multiple_data_lines( buf, len ); |
---|
1068 | TxBd[minor]->buffer = (char *) buf; |
---|
1069 | TxBd[minor]->length = len; |
---|
1070 | TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
1071 | } |
---|
1072 | |
---|
1073 | return 0; |
---|
1074 | } |
---|
1075 | |
---|
1076 | ssize_t |
---|
1077 | m8xx_uart_pollWrite( |
---|
1078 | int minor, |
---|
1079 | const char *buf, |
---|
1080 | size_t len |
---|
1081 | ) |
---|
1082 | { |
---|
1083 | size_t retval = len; |
---|
1084 | |
---|
1085 | while (len--) { |
---|
1086 | while (TxBd[minor]->status & M8260_BD_READY) |
---|
1087 | continue; |
---|
1088 | txBuf[minor] = *buf++; |
---|
1089 | rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 ); |
---|
1090 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
1091 | TxBd[minor]->length = 1; |
---|
1092 | TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP; |
---|
1093 | } |
---|
1094 | |
---|
1095 | return retval; |
---|
1096 | } |
---|