[1ec501c] | 1 | /* |
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| 2 | * General Serial I/O functions. |
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| 3 | * |
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| 4 | * This file contains the functions for performing serial I/O. |
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| 5 | * The actual system calls (console_*) should be in the BSP part |
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| 6 | * of the source tree. That way different BSPs can use whichever |
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| 7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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| 8 | * this file, and it caused problems with one BSP using SCC2 |
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| 9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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| 10 | * |
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| 11 | * On-chip resources used: |
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| 12 | * resource minor note |
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| 13 | * SMC1 0 |
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| 14 | * SMC2 1 |
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| 15 | * SCC1 2 |
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| 16 | * SCC2 3 |
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| 17 | * SCC3 4 |
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| 18 | * SCC4 5 |
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| 19 | * BRG1 |
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| 20 | * BRG2 |
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| 21 | * BRG3 |
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| 22 | * BRG4 |
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| 23 | * Author: Jay Monkman (jmonkman@frasca.com) |
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| 24 | * Copyright (C) 1998 by Frasca International, Inc. |
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| 25 | * |
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| 26 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: |
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| 27 | * W. Eric Norum |
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| 28 | * Saskatchewan Accelerator Laboratory |
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| 29 | * University of Saskatchewan |
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| 30 | * Saskatoon, Saskatchewan, CANADA |
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| 31 | * eric@skatter.usask.ca |
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| 32 | * |
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| 33 | * COPYRIGHT (c) 1989-1998. |
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| 34 | * On-Line Applications Research Corporation (OAR). |
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| 35 | * |
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| 36 | * Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca> |
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| 37 | * and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> |
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| 38 | * Copyright (c) 1999, National Research Council of Canada |
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| 39 | * |
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| 40 | * Modifications by Andy Dachs <a.dachs@sstl.co.uk> to add MPC8260 |
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| 41 | * support. |
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| 42 | * Copyright (c) 2001, Surrey Satellite Technology Ltd |
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| 43 | * SCC1 and SSC2 are used on MPC8260ADS board |
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| 44 | * SMCs are unused |
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| 45 | * |
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| 46 | * The license and distribution terms for this file may be |
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| 47 | * found in the file LICENSE in this distribution or at |
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| 48 | * |
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[21e1c44] | 49 | * http://www.rtems.com/license/LICENSE. |
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[1ec501c] | 50 | * |
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| 51 | * $Id$ |
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| 52 | */ |
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| 53 | |
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| 54 | #include <rtems.h> |
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| 55 | #include <rtems/libio.h> |
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| 56 | #include <mpc8260.h> |
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| 57 | #include <mpc8260/console.h> |
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| 58 | #include <mpc8260/cpm.h> |
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| 59 | #include <stdlib.h> |
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| 60 | #include <unistd.h> |
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| 61 | #include <termios.h> |
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| 62 | #include <bsp/irq.h> |
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[5c76213] | 63 | #include <rtems/bspIo.h> /* for printk */ |
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[1ec501c] | 64 | |
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| 65 | |
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| 66 | |
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| 67 | /* BSP supplied routine */ |
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| 68 | extern int mbx8xx_console_get_configuration(); |
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| 69 | |
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| 70 | |
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| 71 | /* |
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| 72 | * Interrupt-driven input buffer |
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| 73 | */ |
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| 74 | #define RXBUFSIZE 16 |
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| 75 | |
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| 76 | /* |
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| 77 | * I/O buffers and pointers to buffer descriptors. |
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| 78 | * Currently, single buffered input is done. This will work only |
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| 79 | * if the Rx interrupts are serviced quickly. |
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| 80 | * |
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| 81 | * TODO: Add a least double buffering for safety. |
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| 82 | */ |
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| 83 | static volatile char rxBuf[NUM_PORTS][RXBUFSIZE]; |
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| 84 | static volatile char txBuf[NUM_PORTS]; |
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| 85 | |
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| 86 | /* SCC/SMC buffer descriptors */ |
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| 87 | static volatile m8260BufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS]; |
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| 88 | |
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| 89 | |
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| 90 | |
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| 91 | /* Used to track termios private data for callbacks */ |
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| 92 | struct rtems_termios_tty *ttyp[NUM_PORTS]; |
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| 93 | |
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[9c8838f1] | 94 | #if 0 |
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[1ec501c] | 95 | /* Used to record previous ISR */ |
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| 96 | static rtems_isr_entry old_handler[NUM_PORTS]; |
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[9c8838f1] | 97 | #endif |
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[1ec501c] | 98 | |
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| 99 | /* |
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| 100 | * Device-specific routines |
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| 101 | */ |
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| 102 | void m8xx_console_reserve_resources(rtems_configuration_table *); |
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| 103 | static int m8xx_smc_set_attributes(int, const struct termios*); |
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| 104 | static int m8xx_scc_set_attributes(int, const struct termios*); |
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[9c8838f1] | 105 | static rtems_isr m8xx_smc1_interrupt_handler(); |
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| 106 | static rtems_isr m8xx_smc2_interrupt_handler(); |
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| 107 | static rtems_isr m8xx_scc1_interrupt_handler(); |
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| 108 | static rtems_isr m8xx_scc2_interrupt_handler(); |
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| 109 | static rtems_isr m8xx_scc3_interrupt_handler(); |
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| 110 | static rtems_isr m8xx_scc4_interrupt_handler(); |
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[1ec501c] | 111 | |
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| 112 | |
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| 113 | |
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| 114 | /* |
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| 115 | * Hardware-dependent portion of tcsetattr(). |
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| 116 | */ |
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| 117 | static int |
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| 118 | m8xx_smc_set_attributes (int minor, const struct termios *t) |
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| 119 | { |
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| 120 | int baud, brg=0, csize=0, ssize, psize; |
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[66c373bf] | 121 | uint16_t clen=0, cstopb, parenb, parodd, cread; |
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[1ec501c] | 122 | |
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| 123 | /* Baud rate */ |
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| 124 | switch (t->c_cflag & CBAUD) { |
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| 125 | default: baud = -1; break; |
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| 126 | case B50: baud = 50; break; |
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| 127 | case B75: baud = 75; break; |
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| 128 | case B110: baud = 110; break; |
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| 129 | case B134: baud = 134; break; |
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| 130 | case B150: baud = 150; break; |
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| 131 | case B200: baud = 200; break; |
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| 132 | case B300: baud = 300; break; |
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| 133 | case B600: baud = 600; break; |
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| 134 | case B1200: baud = 1200; break; |
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| 135 | case B1800: baud = 1800; break; |
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| 136 | case B2400: baud = 2400; break; |
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| 137 | case B4800: baud = 4800; break; |
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| 138 | case B9600: baud = 9600; break; |
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| 139 | case B19200: baud = 19200; break; |
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| 140 | case B38400: baud = 38400; break; |
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| 141 | case B57600: baud = 57600; break; |
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| 142 | case B115200: baud = 115200; break; |
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| 143 | case B230400: baud = 230400; break; |
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| 144 | case B460800: baud = 460800; break; |
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| 145 | } |
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| 146 | if (baud > 0) { |
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| 147 | switch( minor ) { |
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| 148 | case SMC1_MINOR: |
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| 149 | /* SMC1 can only choose between BRG1 and 7 */ |
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| 150 | brg = m8xx_get_brg( M8260_SMC1_BRGS, baud*16 ) + 1; |
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| 151 | m8260.cmxsmr &= ~0x30; |
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| 152 | m8260.cmxsmr |= (brg==1? 0x00: 0x10 ); |
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| 153 | break; |
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| 154 | case SMC2_MINOR: |
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| 155 | /* SMC2 can only choose between BRG2 and 8 */ |
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| 156 | brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; |
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| 157 | m8260.cmxsmr &= ~0x30; |
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| 158 | m8260.cmxsmr |= (brg==2? 0x00: 0x01 ); |
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| 159 | break; |
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| 160 | } |
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| 161 | } |
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| 162 | |
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| 163 | /* Number of data bits */ |
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| 164 | switch ( t->c_cflag & CSIZE ) { |
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| 165 | case CS5: csize = 5; break; |
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| 166 | case CS6: csize = 6; break; |
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| 167 | case CS7: csize = 7; break; |
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| 168 | case CS8: csize = 8; break; |
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| 169 | } |
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| 170 | |
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| 171 | /* Stop bits */ |
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| 172 | if ( t->c_cflag & CSTOPB ) { |
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| 173 | cstopb = 0x0400; /* Two stop bits */ |
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| 174 | ssize = 2; |
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| 175 | } else { |
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| 176 | cstopb = 0x0000; /* One stop bit */ |
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| 177 | ssize = 1; |
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| 178 | } |
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| 179 | |
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| 180 | /* Parity */ |
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| 181 | if ( t->c_cflag & PARENB ) { |
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| 182 | parenb = 0x0200; /* Parity enabled on Tx and Rx */ |
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| 183 | psize = 1; |
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| 184 | } else { |
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| 185 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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| 186 | psize = 0; |
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| 187 | } |
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| 188 | |
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| 189 | if ( t->c_cflag & PARODD ) |
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| 190 | parodd = 0x0000; /* Odd parity */ |
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| 191 | else |
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| 192 | parodd = 0x0100; |
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| 193 | |
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| 194 | /* |
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| 195 | * Character Length = start + data + parity + stop - 1 |
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| 196 | */ |
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| 197 | switch ( 1 + csize + psize + ssize - 1 ) { |
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| 198 | case 6: clen = 0x3000; break; |
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| 199 | case 7: clen = 0x3800; break; |
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| 200 | case 8: clen = 0x4000; break; |
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| 201 | case 9: clen = 0x4800; break; |
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| 202 | case 10: clen = 0x5000; break; |
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| 203 | case 11: clen = 0x5800; break; |
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| 204 | } |
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| 205 | |
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| 206 | if ( t->c_cflag & CREAD ) |
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| 207 | cread = 0x0023; /* UART normal operation, enable Rx and Tx */ |
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| 208 | else |
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| 209 | cread = 0x0021; /* UART normal operation, enable Tx */ |
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| 210 | |
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| 211 | /* Write the SIMODE/SMCMR registers */ |
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| 212 | switch (minor) { |
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| 213 | case SMC1_MINOR: |
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| 214 | /* |
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| 215 | m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) ); |
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| 216 | */ |
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| 217 | m8260.smc1.smcmr = clen | cstopb | parenb | parodd | cread; |
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| 218 | break; |
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| 219 | case SMC2_MINOR: |
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| 220 | /* CHECK THIS */ |
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| 221 | /* |
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| 222 | m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) ); |
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| 223 | */ |
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| 224 | m8260.smc2.smcmr = clen | cstopb | parenb | parodd | cread; |
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| 225 | break; |
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| 226 | } |
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| 227 | return 0; |
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| 228 | } |
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| 229 | |
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| 230 | |
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| 231 | static int |
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| 232 | m8xx_scc_set_attributes (int minor, const struct termios *t) |
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| 233 | { |
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| 234 | int baud, brg=0; |
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[66c373bf] | 235 | uint16_t csize=0, cstopb, parenb, parodd; |
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[1ec501c] | 236 | |
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| 237 | /* Baud rate */ |
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| 238 | switch (t->c_cflag & CBAUD) { |
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| 239 | default: baud = -1; break; |
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| 240 | case B50: baud = 50; break; |
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| 241 | case B75: baud = 75; break; |
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| 242 | case B110: baud = 110; break; |
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| 243 | case B134: baud = 134; break; |
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| 244 | case B150: baud = 150; break; |
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| 245 | case B200: baud = 200; break; |
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| 246 | case B300: baud = 300; break; |
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| 247 | case B600: baud = 600; break; |
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| 248 | case B1200: baud = 1200; break; |
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| 249 | case B1800: baud = 1800; break; |
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| 250 | case B2400: baud = 2400; break; |
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| 251 | case B4800: baud = 4800; break; |
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| 252 | case B9600: baud = 9600; break; |
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| 253 | case B19200: baud = 19200; break; |
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| 254 | case B38400: baud = 38400; break; |
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| 255 | case B57600: baud = 57600; break; |
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| 256 | case B115200: baud = 115200; break; |
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| 257 | case B230400: baud = 230400; break; |
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| 258 | case B460800: baud = 460800; break; |
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| 259 | } |
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| 260 | if (baud > 0) { |
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| 261 | brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); |
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| 262 | m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); |
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| 263 | m8260.cmxscr |= ((brg<<(3+8*(3-(minor-SCC1_MINOR)))) & |
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| 264 | (brg<<(8*(3-(minor-SCC1_MINOR))))); |
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| 265 | } |
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| 266 | /* Number of data bits */ |
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| 267 | switch ( t->c_cflag & CSIZE ) { |
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| 268 | case CS5: csize = 0x0000; break; |
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| 269 | case CS6: csize = 0x1000; break; |
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| 270 | case CS7: csize = 0x2000; break; |
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| 271 | case CS8: csize = 0x3000; break; |
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| 272 | } |
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| 273 | |
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| 274 | /* Stop bits */ |
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| 275 | if ( t->c_cflag & CSTOPB ) |
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| 276 | cstopb = 0x4000; /* Two stop bits */ |
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| 277 | else |
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| 278 | cstopb = 0x0000; /* One stop bit */ |
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| 279 | |
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| 280 | /* Parity */ |
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| 281 | if ( t->c_cflag & PARENB ) |
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| 282 | parenb = 0x0010; /* Parity enabled on Tx and Rx */ |
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| 283 | else |
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| 284 | parenb = 0x0000; /* No parity on Tx and Rx */ |
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| 285 | |
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| 286 | if ( t->c_cflag & PARODD ) |
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| 287 | parodd = 0x0000; /* Odd parity */ |
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| 288 | else |
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| 289 | parodd = 0x000a; |
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| 290 | |
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| 291 | /* Write the SICR/PSMR Registers */ |
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| 292 | switch (minor) { |
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| 293 | case SCC1_MINOR: |
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| 294 | /* |
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| 295 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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| 296 | */ |
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| 297 | m8260.scc1.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc1.psmr & 0x8fe0) ); |
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| 298 | break; |
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| 299 | case SCC2_MINOR: |
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| 300 | /* |
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| 301 | m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); |
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| 302 | */ |
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| 303 | m8260.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc2.psmr & 0x8fe0) ); |
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| 304 | break; |
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| 305 | case SCC3_MINOR: |
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| 306 | /* |
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| 307 | m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) ); |
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| 308 | */ |
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| 309 | m8260.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc3.psmr & 0x8fe0) ); |
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| 310 | break; |
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| 311 | case SCC4_MINOR: |
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| 312 | /* |
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| 313 | m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) ); |
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| 314 | */ |
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| 315 | m8260.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc4.psmr & 0x8fe0) ); |
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| 316 | break; |
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| 317 | } |
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| 318 | |
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| 319 | return 0; |
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| 320 | } |
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| 321 | |
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| 322 | |
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| 323 | int |
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| 324 | m8xx_uart_setAttributes( |
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| 325 | int minor, |
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| 326 | const struct termios *t |
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| 327 | ) |
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| 328 | { |
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| 329 | /* |
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| 330 | * Check that port number is valid |
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| 331 | */ |
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| 332 | if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) |
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| 333 | return 0; |
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| 334 | |
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| 335 | switch (minor) { |
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| 336 | case SMC1_MINOR: |
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| 337 | case SMC2_MINOR: |
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| 338 | return m8xx_smc_set_attributes( minor, t ); |
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| 339 | |
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| 340 | case SCC1_MINOR: |
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| 341 | case SCC2_MINOR: |
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| 342 | case SCC3_MINOR: |
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| 343 | case SCC4_MINOR: |
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| 344 | return m8xx_scc_set_attributes( minor, t ); |
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| 345 | } |
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| 346 | return 0; |
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| 347 | } |
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| 348 | |
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| 349 | |
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| 350 | /* |
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| 351 | * Interrupt handlers |
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| 352 | */ |
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| 353 | |
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| 354 | static void |
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[9c8838f1] | 355 | m8xx_scc1_interrupt_handler () |
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[1ec501c] | 356 | { |
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| 357 | int nb_overflow; |
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| 358 | |
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| 359 | /* |
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| 360 | * Buffer received? |
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| 361 | */ |
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| 362 | if ((m8260.scc1.sccm & M8260_SCCE_RX) && (m8260.scc1.scce & M8260_SCCE_RX)) { |
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| 363 | m8260.scc1.scce = M8260_SCCE_RX; /* Clear the event */ |
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| 364 | |
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| 365 | |
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| 366 | /* Check that the buffer is ours */ |
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| 367 | if ((RxBd[SCC1_MINOR]->status & M8260_BD_EMPTY) == 0) { |
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| 368 | rtems_cache_invalidate_multiple_data_lines( |
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| 369 | (const void *) RxBd[SCC1_MINOR]->buffer, |
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| 370 | RxBd[SCC1_MINOR]->length ); |
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| 371 | nb_overflow = rtems_termios_enqueue_raw_characters( |
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| 372 | (void *)ttyp[SCC1_MINOR], |
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| 373 | (char *)RxBd[SCC1_MINOR]->buffer, |
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| 374 | (int)RxBd[SCC1_MINOR]->length ); |
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| 375 | RxBd[SCC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
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| 376 | M8260_BD_INTERRUPT; |
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| 377 | } |
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| 378 | } |
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| 379 | |
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| 380 | /* |
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| 381 | * Buffer transmitted? |
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| 382 | */ |
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| 383 | if (m8260.scc1.scce & M8260_SCCE_TX) { |
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| 384 | m8260.scc1.scce = M8260_SCCE_TX; /* Clear the event */ |
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| 385 | |
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| 386 | /* Check that the buffer is ours */ |
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| 387 | if ((TxBd[SCC1_MINOR]->status & M8260_BD_READY) == 0) |
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| 388 | rtems_termios_dequeue_characters ( |
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| 389 | (void *)ttyp[SCC1_MINOR], |
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| 390 | (int)TxBd[SCC1_MINOR]->length); |
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| 391 | } |
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| 392 | |
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| 393 | #if 0 |
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| 394 | m8260.sipnr_l |= M8260_SIMASK_SCC1; /* Clear pending register */ |
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| 395 | #endif |
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| 396 | } |
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| 397 | |
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| 398 | static void |
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[9c8838f1] | 399 | m8xx_scc2_interrupt_handler () |
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[1ec501c] | 400 | { |
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| 401 | int nb_overflow; |
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| 402 | |
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| 403 | /* |
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| 404 | * Buffer received? |
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| 405 | */ |
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| 406 | if ((m8260.scc2.sccm & M8260_SCCE_RX) && (m8260.scc2.scce & M8260_SCCE_RX)) { |
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| 407 | m8260.scc2.scce = M8260_SCCE_RX; /* Clear the event */ |
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| 408 | |
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| 409 | |
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| 410 | /* Check that the buffer is ours */ |
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| 411 | if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) { |
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| 412 | rtems_cache_invalidate_multiple_data_lines( |
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| 413 | (const void *) RxBd[SCC2_MINOR]->buffer, |
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| 414 | RxBd[SCC2_MINOR]->length ); |
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| 415 | nb_overflow = rtems_termios_enqueue_raw_characters( |
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| 416 | (void *)ttyp[SCC2_MINOR], |
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| 417 | (char *)RxBd[SCC2_MINOR]->buffer, |
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| 418 | (int)RxBd[SCC2_MINOR]->length ); |
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| 419 | RxBd[SCC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
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| 420 | M8260_BD_INTERRUPT; |
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| 421 | } |
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| 422 | } |
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| 423 | |
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| 424 | /* |
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| 425 | * Buffer transmitted? |
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| 426 | */ |
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| 427 | if (m8260.scc2.scce & M8260_SCCE_TX) { |
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| 428 | m8260.scc2.scce = M8260_SCCE_TX; /* Clear the event */ |
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| 429 | |
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| 430 | /* Check that the buffer is ours */ |
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| 431 | if ((TxBd[SCC2_MINOR]->status & M8260_BD_READY) == 0) |
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| 432 | rtems_termios_dequeue_characters ( |
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| 433 | (void *)ttyp[SCC2_MINOR], |
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| 434 | (int)TxBd[SCC2_MINOR]->length); |
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| 435 | } |
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| 436 | |
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| 437 | #if 0 |
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| 438 | m8260.sipnr_l |= M8260_SIMASK_SCC2; /* Clear pending register */ |
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| 439 | #endif |
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| 440 | } |
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| 441 | |
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| 442 | |
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| 443 | static void |
---|
[9c8838f1] | 444 | m8xx_scc3_interrupt_handler () |
---|
[1ec501c] | 445 | { |
---|
| 446 | int nb_overflow; |
---|
| 447 | |
---|
| 448 | /* |
---|
| 449 | * Buffer received? |
---|
| 450 | */ |
---|
| 451 | if ((m8260.scc3.sccm & M8260_SCCE_RX) && (m8260.scc3.scce & M8260_SCCE_RX)) { |
---|
| 452 | m8260.scc3.scce = M8260_SCCE_RX; /* Clear the event */ |
---|
| 453 | |
---|
| 454 | |
---|
| 455 | /* Check that the buffer is ours */ |
---|
| 456 | if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
| 457 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 458 | (const void *) RxBd[SCC3_MINOR]->buffer, |
---|
| 459 | RxBd[SCC3_MINOR]->length ); |
---|
| 460 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 461 | (void *)ttyp[SCC3_MINOR], |
---|
| 462 | (char *)RxBd[SCC3_MINOR]->buffer, |
---|
| 463 | (int)RxBd[SCC3_MINOR]->length ); |
---|
| 464 | RxBd[SCC3_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
| 465 | M8260_BD_INTERRUPT; |
---|
| 466 | } |
---|
| 467 | } |
---|
| 468 | |
---|
| 469 | /* |
---|
| 470 | * Buffer transmitted? |
---|
| 471 | */ |
---|
| 472 | if (m8260.scc3.scce & M8260_SCCE_TX) { |
---|
| 473 | m8260.scc3.scce = M8260_SCCE_TX; /* Clear the event */ |
---|
| 474 | |
---|
| 475 | /* Check that the buffer is ours */ |
---|
| 476 | if ((TxBd[SCC3_MINOR]->status & M8260_BD_READY) == 0) |
---|
| 477 | rtems_termios_dequeue_characters ( |
---|
| 478 | (void *)ttyp[SCC3_MINOR], |
---|
| 479 | (int)TxBd[SCC3_MINOR]->length); |
---|
| 480 | } |
---|
| 481 | |
---|
| 482 | |
---|
| 483 | #if 0 |
---|
| 484 | m8260.sipnr_l |= M8260_SIMASK_SCC3; /* Clear pending register */ |
---|
| 485 | #endif |
---|
| 486 | } |
---|
| 487 | |
---|
| 488 | |
---|
| 489 | static void |
---|
[9c8838f1] | 490 | m8xx_scc4_interrupt_handler () |
---|
[1ec501c] | 491 | { |
---|
| 492 | int nb_overflow; |
---|
| 493 | |
---|
| 494 | /* |
---|
| 495 | * Buffer received? |
---|
| 496 | */ |
---|
| 497 | if ((m8260.scc4.sccm & M8260_SCCE_RX) && (m8260.scc4.scce & M8260_SCCE_RX)) { |
---|
| 498 | m8260.scc4.scce = M8260_SCCE_RX; /* Clear the event */ |
---|
| 499 | |
---|
| 500 | |
---|
| 501 | /* Check that the buffer is ours */ |
---|
| 502 | if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
| 503 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 504 | (const void *) RxBd[SCC4_MINOR]->buffer, |
---|
| 505 | RxBd[SCC4_MINOR]->length ); |
---|
| 506 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 507 | (void *)ttyp[SCC4_MINOR], |
---|
| 508 | (char *)RxBd[SCC4_MINOR]->buffer, |
---|
| 509 | (int)RxBd[SCC4_MINOR]->length ); |
---|
| 510 | RxBd[SCC4_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
| 511 | M8260_BD_INTERRUPT; |
---|
| 512 | } |
---|
| 513 | } |
---|
| 514 | |
---|
| 515 | /* |
---|
| 516 | * Buffer transmitted? |
---|
| 517 | */ |
---|
| 518 | if (m8260.scc4.scce & M8260_SCCE_TX) { |
---|
| 519 | m8260.scc4.scce = M8260_SCCE_TX; /* Clear the event */ |
---|
| 520 | |
---|
| 521 | /* Check that the buffer is ours */ |
---|
| 522 | if ((TxBd[SCC4_MINOR]->status & M8260_BD_READY) == 0) |
---|
| 523 | rtems_termios_dequeue_characters ( |
---|
| 524 | (void *)ttyp[SCC4_MINOR], |
---|
| 525 | (int)TxBd[SCC4_MINOR]->length); |
---|
| 526 | } |
---|
| 527 | |
---|
| 528 | #if 0 |
---|
| 529 | m8260.sipnr_l |= M8260_SIMASK_SCC4; /* Clear pending register */ |
---|
| 530 | #endif |
---|
| 531 | } |
---|
| 532 | |
---|
| 533 | static void |
---|
[9c8838f1] | 534 | m8xx_smc1_interrupt_handler () |
---|
[1ec501c] | 535 | { |
---|
| 536 | int nb_overflow; |
---|
| 537 | |
---|
| 538 | /* |
---|
| 539 | * Buffer received? |
---|
| 540 | */ |
---|
| 541 | if (m8260.smc1.smce & M8260_SMCE_RX) { |
---|
| 542 | m8260.smc1.smce = M8260_SMCE_RX; /* Clear the event */ |
---|
| 543 | |
---|
| 544 | |
---|
| 545 | /* Check that the buffer is ours */ |
---|
| 546 | if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
| 547 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 548 | (const void *) RxBd[SMC1_MINOR]->buffer, |
---|
| 549 | RxBd[SMC1_MINOR]->length ); |
---|
| 550 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 551 | (void *)ttyp[SMC1_MINOR], |
---|
| 552 | (char *)RxBd[SMC1_MINOR]->buffer, |
---|
| 553 | (int)RxBd[SMC1_MINOR]->length ); |
---|
| 554 | RxBd[SMC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
| 555 | M8260_BD_INTERRUPT; |
---|
| 556 | } |
---|
| 557 | } |
---|
| 558 | |
---|
| 559 | /* |
---|
| 560 | * Buffer transmitted? |
---|
| 561 | */ |
---|
| 562 | if (m8260.smc1.smce & M8260_SMCE_TX) { |
---|
| 563 | m8260.smc1.smce = M8260_SMCE_TX; /* Clear the event */ |
---|
| 564 | |
---|
| 565 | /* Check that the buffer is ours */ |
---|
| 566 | if ((TxBd[SMC1_MINOR]->status & M8260_BD_READY) == 0) |
---|
| 567 | rtems_termios_dequeue_characters ( |
---|
| 568 | (void *)ttyp[SMC1_MINOR], |
---|
| 569 | (int)TxBd[SMC1_MINOR]->length); |
---|
| 570 | } |
---|
| 571 | |
---|
| 572 | #if 0 |
---|
| 573 | m8260.sipnr_l = 0x00001000; /* Clear SMC1 interrupt-in-service bit */ |
---|
| 574 | #endif |
---|
| 575 | } |
---|
| 576 | |
---|
| 577 | |
---|
| 578 | static void |
---|
[9c8838f1] | 579 | m8xx_smc2_interrupt_handler () |
---|
[1ec501c] | 580 | { |
---|
| 581 | int nb_overflow; |
---|
| 582 | |
---|
| 583 | /* |
---|
| 584 | * Buffer received? |
---|
| 585 | */ |
---|
| 586 | if (m8260.smc2.smce & M8260_SMCE_RX) { |
---|
| 587 | m8260.smc2.smce = M8260_SMCE_RX; /* Clear the event */ |
---|
| 588 | |
---|
| 589 | |
---|
| 590 | /* Check that the buffer is ours */ |
---|
| 591 | if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) { |
---|
| 592 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 593 | (const void *) RxBd[SMC2_MINOR]->buffer, |
---|
| 594 | RxBd[SMC2_MINOR]->length ); |
---|
| 595 | nb_overflow = rtems_termios_enqueue_raw_characters( |
---|
| 596 | (void *)ttyp[SMC2_MINOR], |
---|
| 597 | (char *)RxBd[SMC2_MINOR]->buffer, |
---|
| 598 | (int)RxBd[SMC2_MINOR]->length ); |
---|
| 599 | RxBd[SMC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | |
---|
| 600 | M8260_BD_INTERRUPT; |
---|
| 601 | } |
---|
| 602 | } |
---|
| 603 | |
---|
| 604 | /* |
---|
| 605 | * Buffer transmitted? |
---|
| 606 | */ |
---|
| 607 | if (m8260.smc2.smce & M8260_SMCE_TX) { |
---|
| 608 | m8260.smc2.smce = M8260_SMCE_TX; /* Clear the event */ |
---|
| 609 | |
---|
| 610 | /* Check that the buffer is ours */ |
---|
| 611 | if ((TxBd[SMC2_MINOR]->status & M8260_BD_READY) == 0) |
---|
| 612 | rtems_termios_dequeue_characters ( |
---|
| 613 | (void *)ttyp[SMC2_MINOR], |
---|
| 614 | (int)TxBd[SMC2_MINOR]->length); |
---|
| 615 | } |
---|
| 616 | |
---|
| 617 | #if 0 |
---|
| 618 | m8260.sipnr_l = 0x00000800; /* Clear SMC2 interrupt-in-service bit */ |
---|
| 619 | #endif |
---|
| 620 | } |
---|
| 621 | |
---|
| 622 | |
---|
| 623 | void m8xx_scc_enable(const rtems_irq_connect_data* ptr) |
---|
| 624 | { |
---|
| 625 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
| 626 | switch (ptr->name) { |
---|
| 627 | case BSP_CPM_IRQ_SCC4 : |
---|
| 628 | m8260.sipnr_l |= M8260_SIMASK_SCC4; |
---|
| 629 | sccregs = &m8260.scc4; |
---|
| 630 | break; |
---|
| 631 | case BSP_CPM_IRQ_SCC3 : |
---|
| 632 | m8260.sipnr_l |= M8260_SIMASK_SCC3; |
---|
| 633 | sccregs = &m8260.scc3; |
---|
| 634 | break; |
---|
| 635 | case BSP_CPM_IRQ_SCC2 : |
---|
| 636 | m8260.sipnr_l |= M8260_SIMASK_SCC2; |
---|
| 637 | sccregs = &m8260.scc2; |
---|
| 638 | break; |
---|
| 639 | case BSP_CPM_IRQ_SCC1 : |
---|
| 640 | m8260.sipnr_l |= M8260_SIMASK_SCC1; |
---|
| 641 | sccregs = &m8260.scc1; |
---|
| 642 | break; |
---|
| 643 | default: |
---|
| 644 | break; |
---|
| 645 | } |
---|
| 646 | sccregs->sccm = 3; |
---|
| 647 | } |
---|
| 648 | |
---|
| 649 | void m8xx_scc_disable(const rtems_irq_connect_data* ptr) |
---|
| 650 | { |
---|
| 651 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
| 652 | switch (ptr->name) { |
---|
| 653 | case BSP_CPM_IRQ_SCC4 : |
---|
| 654 | sccregs = &m8260.scc4; |
---|
| 655 | break; |
---|
| 656 | case BSP_CPM_IRQ_SCC3 : |
---|
| 657 | sccregs = &m8260.scc3; |
---|
| 658 | break; |
---|
| 659 | case BSP_CPM_IRQ_SCC2 : |
---|
| 660 | sccregs = &m8260.scc2; |
---|
| 661 | break; |
---|
| 662 | case BSP_CPM_IRQ_SCC1 : |
---|
| 663 | sccregs = &m8260.scc1; |
---|
| 664 | break; |
---|
| 665 | default: |
---|
| 666 | break; |
---|
| 667 | } |
---|
| 668 | sccregs->sccm &= (~3); |
---|
| 669 | } |
---|
| 670 | |
---|
| 671 | int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) |
---|
| 672 | { |
---|
| 673 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
| 674 | } |
---|
| 675 | |
---|
| 676 | static rtems_irq_connect_data consoleIrqData = |
---|
| 677 | { |
---|
| 678 | BSP_CPM_IRQ_SCC1, |
---|
| 679 | (rtems_irq_hdl)m8xx_scc1_interrupt_handler, |
---|
| 680 | (rtems_irq_enable) m8xx_scc_enable, |
---|
| 681 | (rtems_irq_disable) m8xx_scc_disable, |
---|
| 682 | (rtems_irq_is_enabled) m8xx_scc_isOn |
---|
| 683 | }; |
---|
| 684 | |
---|
| 685 | |
---|
| 686 | void |
---|
| 687 | m8xx_uart_scc_initialize (int minor) |
---|
| 688 | { |
---|
| 689 | unsigned char brg; |
---|
| 690 | volatile m8260SCCparms_t *sccparms = 0; |
---|
| 691 | volatile m8260SCCRegisters_t *sccregs = 0; |
---|
| 692 | |
---|
| 693 | /* |
---|
| 694 | * Check that minor number is valid |
---|
| 695 | */ |
---|
| 696 | if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) |
---|
| 697 | return; |
---|
| 698 | |
---|
| 699 | /* Get the sicr clock source bit values for 9600 bps */ |
---|
| 700 | brg = m8xx_get_brg(M8260_SCC_BRGS, 9600*16); |
---|
| 701 | |
---|
| 702 | m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); |
---|
| 703 | m8260.cmxscr |= (brg<<(3+8*(3-(minor-SCC1_MINOR)))); |
---|
| 704 | m8260.cmxscr |= (brg<<(8*(3-(minor-SCC1_MINOR)))); |
---|
| 705 | |
---|
| 706 | /* |
---|
| 707 | * Allocate buffer descriptors |
---|
| 708 | */ |
---|
| 709 | RxBd[minor] = m8xx_bd_allocate(1); |
---|
| 710 | TxBd[minor] = m8xx_bd_allocate(1); |
---|
| 711 | |
---|
| 712 | /* |
---|
| 713 | * Configure ports to enable TXDx and RXDx pins |
---|
| 714 | */ |
---|
| 715 | |
---|
| 716 | m8260.ppard |= (0x07 << ((minor-SCC1_MINOR)*3)); |
---|
| 717 | m8260.psord &= ~(0x07 << ((minor-SCC1_MINOR)*3)); |
---|
| 718 | if( minor == SCC1_MINOR ) |
---|
| 719 | m8260.psord |= 0x02; |
---|
| 720 | m8260.pdird |= (0x06 << ((minor-SCC1_MINOR)*3)); |
---|
| 721 | m8260.pdird &= ~(0x01 << ((minor-SCC1_MINOR)*3)); |
---|
| 722 | |
---|
| 723 | |
---|
| 724 | /* |
---|
| 725 | * Set up SMC1 parameter RAM common to all protocols |
---|
| 726 | */ |
---|
| 727 | if( minor == SCC1_MINOR ) { |
---|
| 728 | sccparms = (m8260SCCparms_t*)&m8260.scc1p; |
---|
| 729 | sccregs = (m8260SCCRegisters_t*)&m8260.scc1; |
---|
| 730 | } |
---|
| 731 | else if( minor == SCC2_MINOR ) { |
---|
| 732 | sccparms = (m8260SCCparms_t*)&m8260.scc2p; |
---|
| 733 | sccregs = (m8260SCCRegisters_t*)&m8260.scc2; |
---|
| 734 | } |
---|
| 735 | else if( minor == SCC3_MINOR ) { |
---|
| 736 | sccparms = (m8260SCCparms_t*)&m8260.scc3p; |
---|
| 737 | sccregs = (m8260SCCRegisters_t*)&m8260.scc3; |
---|
| 738 | } |
---|
| 739 | else { |
---|
| 740 | sccparms = (m8260SCCparms_t*)&m8260.scc4p; |
---|
| 741 | sccregs = (m8260SCCRegisters_t*)&m8260.scc4; |
---|
| 742 | } |
---|
| 743 | |
---|
| 744 | sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260; |
---|
| 745 | sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260; |
---|
| 746 | |
---|
| 747 | |
---|
| 748 | |
---|
| 749 | |
---|
| 750 | sccparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; |
---|
| 751 | sccparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; |
---|
| 752 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
| 753 | sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
| 754 | else |
---|
| 755 | sccparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
| 756 | sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
| 757 | sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
| 758 | |
---|
| 759 | sccparms->un.uart.parec = 0; /* Clear parity error counter */ |
---|
| 760 | sccparms->un.uart.frmec = 0; /* Clear framing error counter */ |
---|
| 761 | sccparms->un.uart.nosec = 0; /* Clear noise counter */ |
---|
| 762 | sccparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
| 763 | |
---|
| 764 | sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */ |
---|
| 765 | sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */ |
---|
| 766 | sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */ |
---|
| 767 | |
---|
| 768 | sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */ |
---|
| 769 | sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */ |
---|
| 770 | sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */ |
---|
| 771 | sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */ |
---|
| 772 | sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */ |
---|
| 773 | sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */ |
---|
| 774 | sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */ |
---|
| 775 | sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */ |
---|
| 776 | |
---|
| 777 | |
---|
| 778 | sccparms->un.uart.rccm = 0xc0ff; /* No masking */ |
---|
| 779 | |
---|
| 780 | /* |
---|
| 781 | * Set up the Receive Buffer Descriptor |
---|
| 782 | */ |
---|
| 783 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
| 784 | RxBd[minor]->length = 0; |
---|
| 785 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
| 786 | |
---|
| 787 | /* |
---|
| 788 | * Setup the Transmit Buffer Descriptor |
---|
| 789 | */ |
---|
| 790 | TxBd[minor]->status = M8260_BD_WRAP; |
---|
| 791 | |
---|
| 792 | /* |
---|
| 793 | * Set up SCCx general and protocol-specific mode registers |
---|
| 794 | */ |
---|
| 795 | sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */ |
---|
| 796 | sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/ |
---|
| 797 | sccregs->scce = ~0; /* Clear any pending event */ |
---|
| 798 | sccregs->sccm = 0; /* Mask all interrupt/event sources */ |
---|
| 799 | sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit, |
---|
| 800 | 8 data bits, no parity */ |
---|
| 801 | sccregs->dsr = 0x7E7E; /* No fractional stop bits */ |
---|
| 802 | sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */ |
---|
| 803 | |
---|
| 804 | /* |
---|
| 805 | * Initialize the Rx and Tx with the new parameters. |
---|
| 806 | */ |
---|
| 807 | switch (minor) { |
---|
| 808 | case SCC1_MINOR: |
---|
| 809 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC1); |
---|
| 810 | break; |
---|
| 811 | case SCC2_MINOR: |
---|
| 812 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC2); |
---|
| 813 | break; |
---|
| 814 | case SCC3_MINOR: |
---|
| 815 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3); |
---|
| 816 | break; |
---|
| 817 | case SCC4_MINOR: |
---|
| 818 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC4); |
---|
| 819 | break; |
---|
| 820 | } |
---|
| 821 | |
---|
| 822 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
| 823 | switch (minor) { |
---|
| 824 | case SCC1_MINOR: |
---|
| 825 | consoleIrqData.name = BSP_CPM_IRQ_SCC1; |
---|
| 826 | consoleIrqData.hdl = m8xx_scc1_interrupt_handler; |
---|
| 827 | break; |
---|
| 828 | case SCC2_MINOR: |
---|
| 829 | consoleIrqData.name = BSP_CPM_IRQ_SCC2; |
---|
| 830 | consoleIrqData.hdl = m8xx_scc2_interrupt_handler; |
---|
| 831 | break; |
---|
| 832 | case SCC3_MINOR: |
---|
| 833 | consoleIrqData.name = BSP_CPM_IRQ_SCC3; |
---|
| 834 | consoleIrqData.hdl = m8xx_scc3_interrupt_handler; |
---|
| 835 | break; |
---|
| 836 | case SCC4_MINOR: |
---|
| 837 | consoleIrqData.name = BSP_CPM_IRQ_SCC4; |
---|
| 838 | consoleIrqData.hdl = m8xx_scc4_interrupt_handler; |
---|
| 839 | break; |
---|
| 840 | |
---|
| 841 | } |
---|
| 842 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
| 843 | printk("Unable to connect SCC Irq handler\n"); |
---|
| 844 | rtems_fatal_error_occurred(1); |
---|
| 845 | } |
---|
| 846 | } |
---|
| 847 | } |
---|
| 848 | |
---|
| 849 | |
---|
| 850 | |
---|
| 851 | void m8xx_smc_enable(const rtems_irq_connect_data* ptr) |
---|
| 852 | { |
---|
| 853 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
| 854 | switch (ptr->name) { |
---|
| 855 | case BSP_CPM_IRQ_SMC1 : |
---|
| 856 | smcregs = &m8260.smc1; |
---|
| 857 | break; |
---|
| 858 | case BSP_CPM_IRQ_SMC2 : |
---|
| 859 | smcregs = &m8260.smc2; |
---|
| 860 | break; |
---|
| 861 | default: |
---|
| 862 | break; |
---|
| 863 | } |
---|
| 864 | smcregs->smcm = 3; |
---|
| 865 | } |
---|
| 866 | |
---|
| 867 | void m8xx_smc_disable(const rtems_irq_connect_data* ptr) |
---|
| 868 | { |
---|
| 869 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
| 870 | switch (ptr->name) { |
---|
| 871 | case BSP_CPM_IRQ_SMC1 : |
---|
| 872 | smcregs = &m8260.smc1; |
---|
| 873 | break; |
---|
| 874 | case BSP_CPM_IRQ_SMC2 : |
---|
| 875 | smcregs = &m8260.smc2; |
---|
| 876 | break; |
---|
| 877 | default: |
---|
| 878 | break; |
---|
| 879 | } |
---|
| 880 | smcregs->smcm &= (~3); |
---|
| 881 | } |
---|
| 882 | |
---|
| 883 | int m8xx_smc_isOn(const rtems_irq_connect_data* ptr) |
---|
| 884 | { |
---|
| 885 | return BSP_irq_enabled_at_cpm (ptr->name); |
---|
| 886 | } |
---|
| 887 | |
---|
| 888 | |
---|
| 889 | void |
---|
| 890 | m8xx_uart_smc_initialize (int minor) |
---|
| 891 | { |
---|
| 892 | unsigned char brg; |
---|
| 893 | volatile m8260SMCparms_t *smcparms = 0; |
---|
| 894 | volatile m8260SMCRegisters_t *smcregs = 0; |
---|
| 895 | |
---|
| 896 | /* |
---|
| 897 | * Check that minor number is valid |
---|
| 898 | */ |
---|
| 899 | if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) |
---|
| 900 | return; |
---|
| 901 | |
---|
| 902 | /* Get the simode clock source bit values for 9600 bps */ |
---|
| 903 | if( minor == SMC1_MINOR ) |
---|
| 904 | brg = m8xx_get_brg(M8260_SMC1_BRGS, 9600*16); |
---|
| 905 | else |
---|
| 906 | brg = m8xx_get_brg(M8260_SMC2_BRGS, 9600*16); |
---|
| 907 | |
---|
| 908 | /* |
---|
| 909 | * Allocate buffer descriptors |
---|
| 910 | */ |
---|
| 911 | RxBd[minor] = m8xx_bd_allocate (1); |
---|
| 912 | TxBd[minor] = m8xx_bd_allocate (1); |
---|
| 913 | |
---|
| 914 | /* |
---|
| 915 | * Get the address of the parameter RAM for the specified port, |
---|
| 916 | * configure I/O port B and put SMC in NMSI mode, connect the |
---|
| 917 | * SMC to the appropriate BRG. |
---|
| 918 | * |
---|
| 919 | * SMC2 RxD is shared with port B bit 20 |
---|
| 920 | * SMC2 TxD is shared with port B bit 21 |
---|
| 921 | * SMC1 RxD is shared with port B bit 24 |
---|
| 922 | * SMC1 TxD is shared with port B bit 25 |
---|
| 923 | */ |
---|
| 924 | switch (minor) { |
---|
| 925 | case SMC1_MINOR: |
---|
| 926 | smcparms = &m8260.smc1p; |
---|
| 927 | smcregs = &m8260.smc1; |
---|
| 928 | |
---|
| 929 | #if 0 |
---|
| 930 | m8260.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ |
---|
| 931 | m8260.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ |
---|
| 932 | m8260.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ |
---|
| 933 | |
---|
| 934 | m8260.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */ |
---|
| 935 | m8260.simode |= brg << 12; /* SMC1CS = brg */ |
---|
| 936 | #endif |
---|
| 937 | break; |
---|
| 938 | |
---|
| 939 | case SMC2_MINOR: |
---|
| 940 | smcparms = &m8260.smc2p; |
---|
| 941 | smcregs = &m8260.smc2; |
---|
| 942 | #if 0 |
---|
| 943 | m8260.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ |
---|
| 944 | m8260.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ |
---|
| 945 | m8260.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ |
---|
| 946 | |
---|
| 947 | m8260.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ |
---|
| 948 | m8260.simode |= brg << 28; /* SMC2CS = brg */ |
---|
| 949 | #endif |
---|
| 950 | break; |
---|
| 951 | } |
---|
| 952 | |
---|
| 953 | /* |
---|
| 954 | * Set up SMC parameter RAM common to all protocols |
---|
| 955 | */ |
---|
| 956 | smcparms->rbase = (char *)RxBd[minor] - (char *)&m8260; |
---|
| 957 | smcparms->tbase = (char *)TxBd[minor] - (char *)&m8260; |
---|
| 958 | smcparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; |
---|
| 959 | smcparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; |
---|
| 960 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) |
---|
| 961 | smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ |
---|
| 962 | else |
---|
| 963 | smcparms->mrblr = 1; /* Maximum Rx buffer size */ |
---|
| 964 | |
---|
| 965 | /* |
---|
| 966 | * Set up SMC1 parameter RAM UART-specific parameters |
---|
| 967 | */ |
---|
| 968 | smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ |
---|
| 969 | smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ |
---|
| 970 | smcparms->un.uart.brkec = 0; /* Clear break counter */ |
---|
| 971 | |
---|
| 972 | /* |
---|
| 973 | * Set up the Receive Buffer Descriptor |
---|
| 974 | */ |
---|
| 975 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
| 976 | RxBd[minor]->length = 0; |
---|
| 977 | RxBd[minor]->buffer = rxBuf[minor]; |
---|
| 978 | |
---|
| 979 | /* |
---|
| 980 | * Setup the Transmit Buffer Descriptor |
---|
| 981 | */ |
---|
| 982 | TxBd[minor]->status = M8260_BD_WRAP; |
---|
| 983 | |
---|
| 984 | /* |
---|
| 985 | * Set up SMCx general and protocol-specific mode registers |
---|
| 986 | */ |
---|
| 987 | smcregs->smce = ~0; /* Clear any pending events */ |
---|
| 988 | smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */ |
---|
| 989 | smcregs->smcmr = M8260_SMCMR_CLEN(9) | M8260_SMCMR_SM_UART; |
---|
| 990 | |
---|
| 991 | /* |
---|
| 992 | * Send "Init parameters" command |
---|
| 993 | */ |
---|
| 994 | switch (minor) { |
---|
| 995 | case SMC1_MINOR: |
---|
| 996 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC1); |
---|
| 997 | break; |
---|
| 998 | |
---|
| 999 | case SMC2_MINOR: |
---|
| 1000 | m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC2); |
---|
| 1001 | break; |
---|
| 1002 | } |
---|
| 1003 | |
---|
| 1004 | /* |
---|
| 1005 | * Enable receiver and transmitter |
---|
| 1006 | */ |
---|
| 1007 | smcregs->smcmr |= M8260_SMCMR_TEN | M8260_SMCMR_REN; |
---|
| 1008 | if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { |
---|
| 1009 | consoleIrqData.on = m8xx_smc_enable; |
---|
| 1010 | consoleIrqData.off = m8xx_smc_disable; |
---|
| 1011 | consoleIrqData.isOn = m8xx_smc_isOn; |
---|
| 1012 | switch (minor) { |
---|
| 1013 | case SMC1_MINOR: |
---|
| 1014 | consoleIrqData.name = BSP_CPM_IRQ_SMC1; |
---|
| 1015 | consoleIrqData.hdl = m8xx_smc1_interrupt_handler; |
---|
| 1016 | break; |
---|
| 1017 | |
---|
| 1018 | case SMC2_MINOR: |
---|
| 1019 | consoleIrqData.name = BSP_CPM_IRQ_SMC2; |
---|
| 1020 | consoleIrqData.hdl = m8xx_smc2_interrupt_handler; |
---|
| 1021 | break; |
---|
| 1022 | #if 0 |
---|
| 1023 | case SMC1_MINOR: |
---|
| 1024 | rtems_interrupt_catch (m8xx_smc1_interrupt_handler, |
---|
| 1025 | PPC_IRQ_CPM_SMC1, |
---|
| 1026 | &old_handler[minor]); |
---|
| 1027 | |
---|
| 1028 | smcregs->smcm = 3; /* Enable SMC1 Rx & Tx interrupts */ |
---|
| 1029 | m8260.sipnr_l |= M8260_SIMASK_SMC1; /* Clear pending register */ |
---|
| 1030 | m8260.simr_l |= M8260_SIMASK_SMC1; /* Enable SMC1 interrupts */ |
---|
| 1031 | break; |
---|
| 1032 | |
---|
| 1033 | case SMC2_MINOR: |
---|
| 1034 | rtems_interrupt_catch (m8xx_smc2_interrupt_handler, |
---|
| 1035 | PPC_IRQ_CPM_SMC2, |
---|
| 1036 | &old_handler[minor]); |
---|
| 1037 | |
---|
| 1038 | smcregs->smcm = 3; /* Enable SMC2 Rx & Tx interrupts */ |
---|
| 1039 | m8260.sipnr_l |= M8260_SIMASK_SMC2; /* Clear pending register */ |
---|
| 1040 | m8260.simr_l |= M8260_SIMASK_SMC2; /* Enable SMC2 interrupts */ |
---|
| 1041 | break; |
---|
| 1042 | #endif |
---|
| 1043 | } |
---|
| 1044 | if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { |
---|
| 1045 | printk("Unable to connect SMC Irq handler\n"); |
---|
| 1046 | rtems_fatal_error_occurred(1); |
---|
| 1047 | } |
---|
| 1048 | } |
---|
| 1049 | } |
---|
| 1050 | |
---|
| 1051 | void |
---|
| 1052 | m8xx_uart_initialize(void) |
---|
| 1053 | { |
---|
| 1054 | |
---|
| 1055 | } |
---|
| 1056 | |
---|
| 1057 | |
---|
| 1058 | void |
---|
| 1059 | m8xx_uart_interrupts_initialize(void) |
---|
| 1060 | { |
---|
| 1061 | #ifdef mpc8260 |
---|
| 1062 | /* CHECK THIS */ |
---|
| 1063 | |
---|
| 1064 | #else |
---|
| 1065 | |
---|
| 1066 | #if defined(mpc860) |
---|
| 1067 | m8xx.cicr = 0x00E43F80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
| 1068 | SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */ |
---|
| 1069 | #else |
---|
| 1070 | m8xx.cicr = 0x00043F80; /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */ |
---|
| 1071 | #endif |
---|
| 1072 | m8xx.simask |= M8xx_SIMASK_LVM1; /* Enable level interrupts */ |
---|
| 1073 | |
---|
| 1074 | #endif |
---|
| 1075 | } |
---|
| 1076 | |
---|
| 1077 | |
---|
| 1078 | int |
---|
| 1079 | m8xx_uart_pollRead( |
---|
| 1080 | int minor |
---|
| 1081 | ) |
---|
| 1082 | { |
---|
| 1083 | unsigned char c; |
---|
| 1084 | |
---|
| 1085 | if (RxBd[minor]->status & M8260_BD_EMPTY) { |
---|
| 1086 | return -1; |
---|
| 1087 | } |
---|
| 1088 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 1089 | (const void *) RxBd[minor]->buffer, |
---|
| 1090 | RxBd[minor]->length |
---|
| 1091 | ); |
---|
| 1092 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
| 1093 | RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP; |
---|
| 1094 | return c; |
---|
| 1095 | } |
---|
| 1096 | |
---|
| 1097 | |
---|
| 1098 | /* |
---|
| 1099 | * TODO: Get a free buffer and set it up. |
---|
| 1100 | */ |
---|
| 1101 | int |
---|
| 1102 | m8xx_uart_write( |
---|
| 1103 | int minor, |
---|
| 1104 | const char *buf, |
---|
| 1105 | int len |
---|
| 1106 | ) |
---|
| 1107 | { |
---|
| 1108 | while( (TxBd[minor]->status) & M8260_BD_READY ); |
---|
| 1109 | |
---|
| 1110 | rtems_cache_flush_multiple_data_lines( buf, len ); |
---|
| 1111 | TxBd[minor]->buffer = (char *) buf; |
---|
| 1112 | TxBd[minor]->length = len; |
---|
| 1113 | TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT; |
---|
| 1114 | return 0; |
---|
| 1115 | } |
---|
| 1116 | |
---|
| 1117 | |
---|
| 1118 | int |
---|
| 1119 | m8xx_uart_pollWrite( |
---|
| 1120 | int minor, |
---|
| 1121 | const char *buf, |
---|
| 1122 | int len |
---|
| 1123 | ) |
---|
| 1124 | { |
---|
| 1125 | |
---|
| 1126 | while (len--) { |
---|
| 1127 | while (TxBd[minor]->status & M8260_BD_READY) |
---|
| 1128 | continue; |
---|
| 1129 | txBuf[minor] = *buf++; |
---|
| 1130 | rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 ); |
---|
| 1131 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
| 1132 | TxBd[minor]->length = 1; |
---|
| 1133 | TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP; |
---|
| 1134 | } |
---|
| 1135 | |
---|
| 1136 | return 0; |
---|
| 1137 | } |
---|
| 1138 | |
---|
| 1139 | void |
---|
| 1140 | m8xx_uart_reserve_resources( |
---|
| 1141 | rtems_configuration_table *configuration |
---|
| 1142 | ) |
---|
| 1143 | { |
---|
| 1144 | rtems_termios_reserve_resources (configuration, NUM_PORTS); |
---|
| 1145 | } |
---|