source: rtems/c/src/lib/libcpu/powerpc/mpc821/vectors/align_h.S @ 3084de2

4.104.114.84.95
Last change on this file since 3084de2 was 3084de2, checked in by Joel Sherrill <joel.sherrill@…>, on 04/07/99 at 15:57:05

MPC821 support and PPC patches from Andrew Bray <andy@…>:

In c/src/exec/score/cpu/powerpc/rtems/score/ppc.h:

A lot of hardware interrupts were omitted. Patch enclosed.
I have also added the 821.

In c/src/exec/score/cpu/powerpc/rtems/score/cpu.h:

My patch adds the 821.

In c/src/exec/score/cpu/powerpc/cpu.c:

I have added the MPC821, and also fixed up for the missing hardware
interrupts. It is also inconsistent with
c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S. This has been fixed.

In c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S:

Fixed an inconsistency with cpu.c.

I also include some new files to go with the above patches. These are the
cpu library rtems-19990331/c/src/lib/libcpu/powerpc/mpc821/* and
c/src/exec/score/cpu/powerpc/mpc821.h which are minor modifications of
the 860 equivalents.

Other comments:

The various accesses to the DPRAM on the 860 are done with a linktime
symbol. This could be done dynamically at run time by reading the immr
register, and masking off the lower 16 bits. This takes the same amount
of time as loading an address constant, and the same number of
instructions as well (2).

In c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c:

This will silently fail if you attempt to use SCC1. This is only relevant
if you are not using SCC1 for ethernet.

This file also sets one of port B output pins for each port. This is NOT
generic, it should be in the BSP specific console driver.

  • Property mode set to 100644
File size: 16.1 KB
Line 
1/*  align_h.s   1.1 - 95/12/04
2 *
3 *  This file contains the assembly code for the PowerPC 403
4 *  alignment exception handler for RTEMS.
5 *
6 *  Based upon IBM provided code with the following release:
7 *
8 *  This source code has been made available to you by IBM on an AS-IS
9 *  basis.  Anyone receiving this source is licensed under IBM
10 *  copyrights to use it in any way he or she deems fit, including
11 *  copying it, modifying it, compiling it, and redistributing it either
12 *  with or without modifications.  No license under IBM patents or
13 *  patent applications is to be implied by the copyright license.
14 *
15 *  Any user of this software should understand that IBM cannot provide
16 *  technical support for this software and will not be responsible for
17 *  any consequences resulting from the use of this software.
18 *
19 *  Any person who transfers this source code or any derivative work
20 *  must include the IBM copyright notice, this paragraph, and the
21 *  preceding two paragraphs in the transferred software.
22 *
23 *      COPYRIGHT   I B M   CORPORATION 1995
24 *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
25 *
26 * Modifications:
27 *
28 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
29 *
30 *  COPYRIGHT (c) 1995 by i-cubed ltd.
31 *
32 *  To anyone who acknowledges that this file is provided "AS IS"
33 *  without any express or implied warranty:
34 *      permission to use, copy, modify, and distribute this file
35 *      for any purpose is hereby granted without fee, provided that
36 *      the above copyright notice and this notice appears in all
37 *      copies, and that the name of i-cubed limited not be used in
38 *      advertising or publicity pertaining to distribution of the
39 *      software without specific, written prior permission.
40 *      i-cubed limited makes no representations about the suitability
41 *      of this software for any purpose.
42 *
43 *  $Id$
44 */
45
46#include "asm.h"
47/*#include "bsp.h"*/
48#define ALIGN_REGS 0x0140
49
50.set    CACHE_SIZE,16           # cache line size of 32 bytes
51.set    CACHE_SIZE_L2,4         # cache line size, log 2
52
53.set    Open_gpr0,0
54.set    Open_gpr1,4
55.set    Open_gpr2,8
56.set    Open_gpr3,12
57.set    Open_gpr4,16
58.set    Open_gpr5,20
59.set    Open_gpr6,24
60.set    Open_gpr7,28
61.set    Open_gpr8,32
62.set    Open_gpr9,36
63.set    Open_gpr10,40
64.set    Open_gpr11,44
65.set    Open_gpr12,48
66.set    Open_gpr13,52
67.set    Open_gpr14,56
68.set    Open_gpr15,60
69.set    Open_gpr16,64
70.set    Open_gpr17,68
71.set    Open_gpr18,72
72.set    Open_gpr19,76
73.set    Open_gpr20,80
74.set    Open_gpr21,84
75.set    Open_gpr22,88
76.set    Open_gpr23,92
77.set    Open_gpr24,96
78.set    Open_gpr25,100
79.set    Open_gpr26,104
80.set    Open_gpr27,108
81.set    Open_gpr28,112
82.set    Open_gpr29,116
83.set    Open_gpr30,120
84.set    Open_gpr31,124
85.set    Open_xer,128
86.set    Open_lr,132
87.set    Open_ctr,136
88.set    Open_cr,140
89.set    Open_srr2,144
90.set    Open_srr3,148
91.set    Open_srr0,152
92.set    Open_srr1,156
93
94
95/*
96 *  This code makes several assumptions for processing efficiency
97 *  *  General purpose registers are continuous in the image, beginning with
98 *     Open_gpr0
99 *  *  Hash table is highly dependent on opcodes - opcode changes *will*
100 *     require rework of the instruction decode mechanism.
101 */
102
103        .text
104        .globl  align_h
105
106        .align  CACHE_SIZE_L2
107align_h:
108        /*-----------------------------------------------------------------------
109         * Store GPRs in Open Reg save area
110         * Set up r2 as base reg, r1 pointing to Open Reg save area
111         *----------------------------------------------------------------------*/
112        stmw    r0,ALIGN_REGS(r0)
113        li      r1,ALIGN_REGS
114        /*-----------------------------------------------------------------------
115         * Store special purpose registers in reg save area
116         *----------------------------------------------------------------------*/
117        mfxer   r7
118        mflr    r8
119        mfcr    r9
120        mfctr   r10
121        stw     r7,Open_xer(r1)
122        stw     r8,Open_lr(r1)
123        stw     r9,Open_cr(r1)
124        stw     r10,Open_ctr(r1)
125        mfspr   r7, srr2                /* SRR 2 */
126        mfspr   r8, srr3                /* SRR 3 */
127        mfspr   r9, srr0                /* SRR 0 */
128        mfspr   r10, srr1               /* SRR 1 */
129        stw     r7,Open_srr2(r1)
130        stw     r8,Open_srr3(r1)
131        stw     r9,Open_srr0(r1)
132        stw     r10,Open_srr1(r1)
133
134/*      Set up common registers */
135        mfspr   r5, dear                /* DEAR: R5 is data exception address */
136        lwz     r9,Open_srr0(r1)        /* get faulting instruction */
137        addi    r7,r9,4                 /* bump instruction */
138        stw     r7,Open_srr0(r1)        /* restore to image */
139        lwz     r9, 0(r9)               /* retrieve actual instruction */
140        rlwinm  r6,r9,18,25,29          /* r6 is RA * 4 field from instruction */
141        rlwinm  r7,r9,6,26,31           /* r7 is primary opcode */
142        bl      ref_point               /* establish addressibility */
143ref_point:
144        mflr    r11                     /* r11 is the anchor point for ref_point */
145        addi    r10, r7, -31            /* r10 = r7 - 31 */
146        rlwinm  r10,r10,2,2,31          /* r10 *= 4 */
147        add     r10, r10, r11           /* r10 += anchor point */
148        lwz     r10, primary_jt-ref_point(r10)
149        mtlr    r10
150        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
151        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
152        blr
153primary_jt:
154        .long   xform
155        .long   lwz
156        .long   lwzu
157        .long   0
158        .long   0
159        .long   stw
160        .long   stwu
161        .long   0
162        .long   0
163        .long   lhz
164        .long   lhzu
165        .long   lha
166        .long   lhau
167        .long   sth
168        .long   sthu
169        .long   lmw
170        .long   stmw
171/*
172 *   handlers
173 */
174/*
175 * xform instructions require an additional decode.  Fortunately, a relatively
176 * simple hash step breaks the instructions out with no collisions
177 */
178xform:
179        rlwinm  r7,r9,31,22,31          /* r7 is secondary opcode */
180        rlwinm  r10,r7,27,5,31          /* r10 = r7 >> 5 */
181        add     r10,r7,r10              /* r10 = r7 + r10 */
182        rlwinm  r10,r10,2,25,29         /* r10 = (r10 & 0x1F) * 4 */
183        add     r10,r10,r11             /* r10 += anchor point */
184        lwz     r10, secondary_ht-ref_point(r10)
185        mtlr    r10
186        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
187        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
188        blrl
189
190secondary_ht:
191        .long   lhzux                   /* b 0  0x137 */
192        .long   lhax                    /* b 1  0x157 */
193        .long   lhaux                   /* b 2  0x177 */
194        .long   sthx                    /* b 3  0x197 */
195        .long   sthux                   /* b 4  0x1b7 */
196        .long   0                       /* b 5 */
197        .long   lwbrx                   /* b 6  0x216 */
198        .long   0                       /* b 7 */
199        .long   0                       /* b 8 */
200        .long   0                       /* b 9 */
201        .long   stwbrx                  /* b A  0x296 */
202        .long   0                       /* b B */
203        .long   0                       /* b C */
204        .long   0                       /* b D */
205        .long   lhbrx                   /* b E   0x316 */
206        .long   0                       /* b F */
207        .long   0                       /* b 10 */
208        .long   0                       /* b 11 */
209        .long   sthbrx                  /* b 12  0x396 */
210        .long   0                       /* b 13 */
211        .long   lwarx                   /* b 14  0x014 */
212        .long   dcbz                    /* b 15  0x3f6 */
213        .long   0                       /* b 16 */
214        .long   lwzx                    /* b 17  0x017 */
215        .long   lwzux                   /* b 18  0x037 */
216        .long   0                       /* b 19 */
217        .long   stwcx                   /* b 1A  0x096 */
218        .long   stwx                    /* b 1B  0x097 */
219        .long   stwux                   /* b 1C  0x0B7 */
220        .long   0                       /* b 1D */
221        .long   0                       /* b 1E */
222        .long   lhzx                    /* b 1F 0x117 */
223
224/*
225 * for all handlers
226 *       r4 - Addressability to interrupt context
227 *       r5 - DEAR address (faulting data address)
228 *       r6 - RA field * 4
229 *       r7 - Address of GPR 0 in image
230 *       r8 - RD field * 4
231 *       r9 - Failing instruction
232 */
233
234/*       Load halfword algebraic with update */
235lhau:
236/*       Load halfword algebraic with update indexed */
237lhaux:
238        stwx    r5,r7,r6                /* update RA with effective addr */
239
240/*       Load halfword algebraic */
241lha:
242/*       Load halfword algebraic indexed */
243lhax:
244        lswi    r10,r5,2                /* load two bytes into r10 */
245        srawi   r10,r10,16              /* shift right 2 bytes, extending sign */
246        stwx    r10,r7,r8               /* update reg image */
247        b       align_complete          /* return */
248
249/*       Load Half Word Byte-Reversed Indexed */
250lhbrx:
251        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
252        rlwinm  r10,r10,0,0,15          /* mask off lower 2 bytes */
253        stwbrx  r10,r7,r8               /* store reversed in reg image */
254        b       align_complete          /* return */
255
256/*       Load Half Word and Zero with Update */
257lhzu:
258/*       Load Half Word and Zero with Update Indexed */
259lhzux:
260        stwx    r5,r7,r6                /* update RA with effective addr */
261
262/*       Load Half Word and Zero */
263lhz:
264/*       Load Half Word and Zero Indexed */
265lhzx:
266        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
267        rlwinm  r10,r10,16,16,31        /* shift right 2 bytes, with zero fill */
268        stwx    r10,r7,r8               /* update reg image */
269        b       align_complete          /* return */
270
271/*
272 *       Load Multiple Word
273 */
274lmw:
275        lwzx    r9,r6,r7                /* R9 contains saved value of RA */
276        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
277        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
278        subfic  r8,r8,32                /* r8 is reg count to load */
279        mtctr   r8                      /* load counter */
280        addi    r8,r8,-1                /* r8-- */
281        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
282        add     r5,r5,r8                /* update DEAR to point to last reg */
283lwmloop:
284        lswi    r11,r5,4                /* load r11 with 4 bytes from DEAR */
285        stwu    r11,-4(r10)             /* load image and decrement pointer */
286        addi    r5,r5,-4                /* decrement effective address */
287        bdnz    lwmloop
288        stwx    r9,r6,r7                /* restore RA (in case it was trashed) */
289        b       align_complete          /* return */
290
291/*
292 *       Load Word and Reserve Indexed
293 */
294lwarx:
295        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
296        stwx    r10,r7,r8               /* update reg image */
297        rlwinm  r5,r5,0,0,29            /* Word align address */
298        lwarx   r10,0,r5                /* Set reservation */
299        b       align_complete          /* return */
300
301/*
302 *       Load Word Byte-Reversed Indexed
303 */
304lwbrx:
305        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
306        stwbrx  r10,r7,r8               /* store reversed in reg image */
307        b       align_complete          /* return */
308
309/*       Load Word and Zero with Update */
310lwzu:
311/*       Load Word and Zero with Update Indexed */
312lwzux:
313        stwx    r5,r7,r6                /* update RA with effective addr */
314
315/*       Load Word and Zero */
316lwz:
317/*       Load Word and Zero Indexed */
318lwzx:
319        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
320        stwx    r10,r7,r8               /* update reg image */
321        b       align_complete          /* return */
322
323/*    Store instructions */
324
325/* */
326/*       Store Half Word and Update */
327sthu:
328/*       Store Half Word and Update Indexed */
329sthux:
330        stwx    r5,r7,r6                /* Update RA with effective address */
331
332/*       Store Half Word */
333sth:
334/*       Store Half Word Indexed */
335sthx:
336        lwzx    r10,r8,r7               /* retrieve source register value */
337        rlwinm  r10,r10,16,0,15         /* move two bytes to high end of reg */
338        stswi   r10,r5,2                /* store bytes to DEAR address */
339        b       align_complete          /* return */
340
341/* */
342/*       Store Half Word Byte-Reversed Indexed */
343sthbrx:
344        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
345        stswi   r10,r5,2                /* move two bytes to DEAR address */
346        b       align_complete          /* return */
347
348/* */
349/*       Store Multiple Word */
350stmw:
351        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
352        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
353        subfic  r8,r8,32                /* r8 is reg count to load */
354        mtctr   r8                      /* load counter */
355        addi    r8,r8,-1                /* r8-- */
356        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
357        add     r5,r5,r8                /* update DEAR to point to last reg */
358stmloop:
359        lwzu    r11,-4(r10)             /* get register value */
360        stswi   r11,r5,4                /* output to DEAR address */
361        addi    r5,r5,-4                /* decrement effective address */
362        bdnz    stmloop
363        b       align_complete          /* return */
364
365/* */
366/*       Store Word and Update */
367stwu:
368/*       Store Word and Update Indexed */
369stwux:
370        stwx    r5,r7,r6                /* Update RA with effective address */
371
372/*       Store Word */
373stw:
374/*       Store Word Indexed */
375stwx:
376        lwzx    r10,r8,r7               /* retrieve source register value */
377        stswi   r10,r5,4                /* store bytes to DEAR address */
378        b       align_complete          /* return */
379
380/* */
381/*       Store Word Byte-Reversed Indexed */
382stwbrx:
383        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
384        stswi   r10,r5,4                /* move two bytes to DEAR address */
385        b       align_complete          /* return */
386
387/* */
388/*       Store Word Conditional Indexed */
389stwcx:
390        rlwinm  r10,r5,0,0,29           /* r10 = word aligned DEAR */
391        lwz     r11,0(r10)              /* save original value of store */
392        stwcx.  r11,r0,r10              /* attempt store to address */
393        bne     stwcx_moveon            /* store failed, move on */
394        stw     r11,0(r10)              /* repair damage */
395        lwzx    r9,r7,r8                /* get register value */
396        stswi   r10,r5,4                /* store bytes to DEAR address */
397stwcx_moveon:
398        mfcr    r11                     /* get condition reg */
399        lwz     r9,Open_cr(r1)          /* get condition reg image */
400        rlwimi  r9,r11,0,0,2            /* insert 3 CR bits into cr image */
401        lwz     r11,Open_xer(r1)        /* get XER reg */
402        rlwimi  r9,r11,29,2,2           /* insert XER SO bit into cr image */
403        stw     r9,Open_cr(r1)          /* store cr image */
404        b       align_complete          /* return */
405
406/* */
407/*       Data Cache Block Zero */
408dcbz:
409        rlwinm  r5,r5,0,0,31-CACHE_SIZE_L2
410                                        /* get address to nearest Cache line */
411        addi    r5,r5,-4                /* adjust by a word */
412        addi    r10,r0,CACHE_SIZE/4     /* set counter value */
413        mtctr   r10
414        addi    r11,r0,0                /* r11 = 0 */
415dcbz_loop:
416        stwu    r11,4(r5)               /* store a word and update EA */
417        bdnz    dcbz_loop
418        b       align_complete          /* return */
419
420align_complete:
421        /*-----------------------------------------------------------------------
422         * Restore regs and return from the interrupt
423         *----------------------------------------------------------------------*/
424        lmw     r24,Open_xer+ALIGN_REGS(r0)
425        mtxer   r24
426        mtlr    r25
427        mtctr   r26
428        mtcrf   0xFF, r27
429        mtspr   srr2, r28               /* SRR 2 */
430        mtspr   srr3, r29               /* SRR 3 */
431        mtspr   srr0, r30               /* SRR 0 */
432        mtspr   srr1, r31               /* SRR 1 */
433        lmw     r1,Open_gpr1+ALIGN_REGS(r0)
434        lwz     r0,Open_gpr0+ALIGN_REGS(r0)
435        rfi
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