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mpc821.h @ 817466c

4.104.114.84.95

Last change on this file since 817466c was fbe75c6e, checked in by Joel Sherrill <joel.sherrill@…>, on 06/14/99 at 18:17:33

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE

As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :

| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |

^{------

| VIA PCI/ISA bridge

| x

-------- PCI interrupts}

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE

Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

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File size: 46.1 KB

Line
1	/*
2	**************************************************************************
3	**************************************************************************
4
5	MOTOROLA MPC21 PORTABLE SYSTEMS MICROPROCESSOR
6
7	HARDWARE DECLARATIONS
8
9
10	Submitted By:
11
12	W. Eric Norum
13	Saskatchewan Accelerator Laboratory
14	University of Saskatchewan
15	107 North Road
16	Saskatoon, Saskatchewan, CANADA
17	S7N 5C6
18
19	eric@skatter.usask.ca
20
21	Modified for use with the MPC860 (original code was for MC68360)
22	by
23	Jay Monkman
24	Frasca International, Inc.
25	906 E. Airport Rd.
26	Urbana, IL, 61801
27
28	jmonkman@frasca.com
29
30	Modified further for use with the MPC821 by:
31	Andrew Bray <andy@chaos.org.uk>
32
33	**************************************************************************
34	**************************************************************************
35	*/
36
37	#ifndef __MPC821_h
38	#define __MPC821_h
39
40	#ifndef ASM
41	/*
42	Macros for SPRs
43	*/
44
45	#define M821_MI_CTR_GPM (1<<31)
46	#define M821_MI_CTR_PPM (1<<30)
47	#define M821_MI_CTR_CIDEF (1<<29)
48	#define M821_MI_CTR_RSV4I (1<<27)
49	#define M821_MI_CTR_PPCS (1<<25)
50
51	#define M821_MD_CTR_GPM (1<<31)
52	#define M821_MD_CTR_PPM (1<<30)
53	#define M821_MD_CTR_CIDEF (1<<29)
54	#define M821_MD_CTR_WTDEF (1<<28)
55	#define M821_MD_CTR_RSV4D (1<<27)
56	#define M821_MD_CTR_TWAM (1<<26)
57	#define M821_MD_CTR_PPCS (1<<25)
58
59	#define M821_MI_EPN_VALID (1<<9)
60
61	#define M821_MD_EPN_VALID (1<<9)
62
63	#define M821_MI_TWC_G (1<<4)
64	#define M821_MI_TWC_PSS (0<<2)
65	#define M821_MI_TWC_PS512 (1<<2)
66	#define M821_MI_TWC_PS8 (3<<2)
67	#define M821_MI_TWC_VALID (1)
68
69	#define M821_MD_TWC_G (1<<4)
70	#define M821_MD_TWC_PSS (0<<2)
71	#define M821_MD_TWC_PS512 (1<<2)
72	#define M821_MD_TWC_PS8 (3<<2)
73	#define M821_MD_TWC_WT (1<<1)
74	#define M821_MD_TWC_VALID (1)
75
76	#define M821_MI_RPN_F (0xf<<4)
77	#define M821_MI_RPN_16K (1<<3)
78	#define M821_MI_RPN_SHARED (1<<2)
79	#define M821_MI_RPN_CI (1<<1)
80	#define M821_MI_RPN_VALID (1)
81
82	#define M821_MD_RPN_CHANGE (1<<8)
83	#define M821_MD_RPN_F (0xf<<4)
84	#define M821_MD_RPN_16K (1<<3)
85	#define M821_MD_RPN_SHARED (1<<2)
86	#define M821_MD_RPN_CI (1<<1)
87	#define M821_MD_RPN_VALID (1)
88
89	#define M821_MI_AP_Kp (1)
90
91	#define M821_MD_AP_Kp (1)
92
93	#define M821_CACHE_CMD_SFWT (0x1<<24)
94	#define M821_CACHE_CMD_ENABLE (0x2<<24)
95	#define M821_CACHE_CMD_CFWT (0x3<<24)
96	#define M821_CACHE_CMD_DISABLE (0x4<<24)
97	#define M821_CACHE_CMD_STLES (0x5<<24)
98	#define M821_CACHE_CMD_LLCB (0x6<<24)
99	#define M821_CACHE_CMD_CLES (0x7<<24)
100	#define M821_CACHE_CMD_UNLOCK (0x8<<24)
101	#define M821_CACHE_CMD_UNLOCKALL (0xa<<24)
102	#define M821_CACHE_CMD_INVALIDATE (0xc<<24)
103	#define M821_CACHE_CMD_FLUSH (0xe<<24)
104
105
106
107	/*
108	*************************************************************************
109	* REGISTER SUBBLOCKS *
110	*************************************************************************
111	*/
112
113	/*
114	* Memory controller registers
115	*/
116	typedef struct m821MEMCRegisters_ {
117	rtems_unsigned32 br;
118	rtems_unsigned32 or;
119	} m821MEMCRegisters_t;
120
121	/*
122	* Serial Communications Controller registers
123	*/
124	typedef struct m821SCCRegisters_ {
125	rtems_unsigned32 gsmr_l;
126	rtems_unsigned32 gsmr_h;
127	rtems_unsigned16 psmr;
128	rtems_unsigned16 _pad0;
129	rtems_unsigned16 todr;
130	rtems_unsigned16 dsr;
131	rtems_unsigned16 scce;
132	rtems_unsigned16 _pad1;
133	rtems_unsigned16 sccm;
134	rtems_unsigned8 _pad2;
135	rtems_unsigned8 sccs;
136	rtems_unsigned32 _pad3[2];
137	} m821SCCRegisters_t;
138
139	/*
140	* Serial Management Controller registers
141	*/
142	typedef struct m821SMCRegisters_ {
143	rtems_unsigned16 _pad0;
144	rtems_unsigned16 smcmr;
145	rtems_unsigned16 _pad1;
146	rtems_unsigned8 smce;
147	rtems_unsigned8 _pad2;
148	rtems_unsigned16 _pad3;
149	rtems_unsigned8 smcm;
150	rtems_unsigned8 _pad4;
151	rtems_unsigned32 _pad5;
152	} m821SMCRegisters_t;
153
154	/*
155	*************************************************************************
156	* Miscellaneous Parameters *
157	*************************************************************************
158	*/
159	typedef struct m821MiscParms_ {
160	rtems_unsigned16 rev_num;
161	rtems_unsigned16 _res1;
162	rtems_unsigned32 _res2;
163	rtems_unsigned32 _res3;
164	} m821MiscParms_t;
165
166	/*
167	*************************************************************************
168	* RISC Timers *
169	*************************************************************************
170	*/
171	typedef struct m821TimerParms_ {
172	rtems_unsigned16 tm_base;
173	rtems_unsigned16 _tm_ptr;
174	rtems_unsigned16 _r_tmr;
175	rtems_unsigned16 _r_tmv;
176	rtems_unsigned32 tm_cmd;
177	rtems_unsigned32 tm_cnt;
178	} m821TimerParms_t;
179
180	/*
181	* RISC Controller Configuration Register (RCCR)
182	* All other bits in this register are reserved.
183	*/
184	#define M821_RCCR_TIME (1<<15) /* Enable timer */
185	#define M821_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
186	#define M821_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */
187	#define M821_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */
188	#define M821_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */
189	#define M821_RCCR_EIE (1<<3) /* External Interrupt Enable */
190	#define M821_RCCR_SCD (1<<2) /* Scheduler Configuration */
191	#define M821_RCCR_ERAM(x) (x) /* Enable RAM Microcode */
192
193	/*
194	* Command register
195	* Set up this register before issuing a M821_CR_OP_SET_TIMER command.
196	*/
197	#define M821_TM_CMD_V (1<<31) /* Set to enable timer */
198	#define M821_TM_CMD_R (1<<30) /* Set for automatic restart */
199	#define M821_TM_CMD_PWM (1<<29) /* Set for PWM operation */
200	#define M821_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
201	#define M821_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
202
203	/*
204	*************************************************************************
205	* DMA Controllers *
206	*************************************************************************
207	*/
208	typedef struct m821IDMAparms_ {
209	rtems_unsigned16 ibase;
210	rtems_unsigned16 dcmr;
211	rtems_unsigned32 _sapr;
212	rtems_unsigned32 _dapr;
213	rtems_unsigned16 ibptr;
214	rtems_unsigned16 _write_sp;
215	rtems_unsigned32 _s_byte_c;
216	rtems_unsigned32 _d_byte_c;
217	rtems_unsigned32 _s_state;
218	rtems_unsigned32 _itemp[4];
219	rtems_unsigned32 _sr_mem;
220	rtems_unsigned16 _read_sp;
221	rtems_unsigned16 _res0;
222	rtems_unsigned16 _res1;
223	rtems_unsigned16 _res2;
224	rtems_unsigned32 _d_state;
225	} m821IDMAparms_t;
226
227
228	/*
229	*************************************************************************
230	* DSP *
231	*************************************************************************
232	*/
233	typedef struct m821DSPparms_ {
234	rtems_unsigned32 fdbase;
235	rtems_unsigned32 _fd_ptr;
236	rtems_unsigned32 _dstate;
237	rtems_unsigned32 _pad0;
238	rtems_unsigned16 _dstatus;
239	rtems_unsigned16 _i;
240	rtems_unsigned16 _tap;
241	rtems_unsigned16 _cbase;
242	rtems_unsigned16 _pad1;
243	rtems_unsigned16 _xptr;
244	rtems_unsigned16 _pad2;
245	rtems_unsigned16 _yptr;
246	rtems_unsigned16 _m;
247	rtems_unsigned16 _pad3;
248	rtems_unsigned16 _n;
249	rtems_unsigned16 _pad4;
250	rtems_unsigned16 _k;
251	rtems_unsigned16 _pad5;
252	} m821DSPparms_t;
253
254	/*
255	*************************************************************************
256	* Serial Communication Controllers *
257	*************************************************************************
258	*/
259	typedef struct m821SCCparms_ {
260	rtems_unsigned16 rbase;
261	rtems_unsigned16 tbase;
262	rtems_unsigned8 rfcr;
263	rtems_unsigned8 tfcr;
264	rtems_unsigned16 mrblr;
265	rtems_unsigned32 _rstate;
266	rtems_unsigned32 _pad0;
267	rtems_unsigned16 _rbptr;
268	rtems_unsigned16 _pad1;
269	rtems_unsigned32 _pad2;
270	rtems_unsigned32 _tstate;
271	rtems_unsigned32 _pad3;
272	rtems_unsigned16 _tbptr;
273	rtems_unsigned16 _pad4;
274	rtems_unsigned32 _pad5;
275	rtems_unsigned32 _rcrc;
276	rtems_unsigned32 _tcrc;
277	union {
278	struct {
279	rtems_unsigned32 _res0;
280	rtems_unsigned32 _res1;
281	rtems_unsigned16 max_idl;
282	rtems_unsigned16 _idlc;
283	rtems_unsigned16 brkcr;
284	rtems_unsigned16 parec;
285	rtems_unsigned16 frmec;
286	rtems_unsigned16 nosec;
287	rtems_unsigned16 brkec;
288	rtems_unsigned16 brklen;
289	rtems_unsigned16 uaddr[2];
290	rtems_unsigned16 _rtemp;
291	rtems_unsigned16 toseq;
292	rtems_unsigned16 character[8];
293	rtems_unsigned16 rccm;
294	rtems_unsigned16 rccr;
295	rtems_unsigned16 rlbc;
296	} uart;
297	} un;
298	} m821SCCparms_t;
299
300	typedef struct m821SCCENparms_ {
301	rtems_unsigned16 rbase;
302	rtems_unsigned16 tbase;
303	rtems_unsigned8 rfcr;
304	rtems_unsigned8 tfcr;
305	rtems_unsigned16 mrblr;
306	rtems_unsigned32 _rstate;
307	rtems_unsigned32 _pad0;
308	rtems_unsigned16 _rbptr;
309	rtems_unsigned16 _pad1;
310	rtems_unsigned32 _pad2;
311	rtems_unsigned32 _tstate;
312	rtems_unsigned32 _pad3;
313	rtems_unsigned16 _tbptr;
314	rtems_unsigned16 _pad4;
315	rtems_unsigned32 _pad5;
316	rtems_unsigned32 _rcrc;
317	rtems_unsigned32 _tcrc;
318	union {
319	struct {
320	rtems_unsigned32 _res0;
321	rtems_unsigned32 _res1;
322	rtems_unsigned16 max_idl;
323	rtems_unsigned16 _idlc;
324	rtems_unsigned16 brkcr;
325	rtems_unsigned16 parec;
326	rtems_unsigned16 frmec;
327	rtems_unsigned16 nosec;
328	rtems_unsigned16 brkec;
329	rtems_unsigned16 brklen;
330	rtems_unsigned16 uaddr[2];
331	rtems_unsigned16 _rtemp;
332	rtems_unsigned16 toseq;
333	rtems_unsigned16 character[8];
334	rtems_unsigned16 rccm;
335	rtems_unsigned16 rccr;
336	rtems_unsigned16 rlbc;
337	} uart;
338	struct {
339	rtems_unsigned32 c_pres;
340	rtems_unsigned32 c_mask;
341	rtems_unsigned32 crcec;
342	rtems_unsigned32 alec;
343	rtems_unsigned32 disfc;
344	rtems_unsigned16 pads;
345	rtems_unsigned16 ret_lim;
346	rtems_unsigned16 _ret_cnt;
347	rtems_unsigned16 mflr;
348	rtems_unsigned16 minflr;
349	rtems_unsigned16 maxd1;
350	rtems_unsigned16 maxd2;
351	rtems_unsigned16 _maxd;
352	rtems_unsigned16 dma_cnt;
353	rtems_unsigned16 _max_b;
354	rtems_unsigned16 gaddr1;
355	rtems_unsigned16 gaddr2;
356	rtems_unsigned16 gaddr3;
357	rtems_unsigned16 gaddr4;
358	rtems_unsigned32 _tbuf0data0;
359	rtems_unsigned32 _tbuf0data1;
360	rtems_unsigned32 _tbuf0rba0;
361	rtems_unsigned32 _tbuf0crc;
362	rtems_unsigned16 _tbuf0bcnt;
363	rtems_unsigned16 paddr_h;
364	rtems_unsigned16 paddr_m;
365	rtems_unsigned16 paddr_l;
366	rtems_unsigned16 p_per;
367	rtems_unsigned16 _rfbd_ptr;
368	rtems_unsigned16 _tfbd_ptr;
369	rtems_unsigned16 _tlbd_ptr;
370	rtems_unsigned32 _tbuf1data0;
371	rtems_unsigned32 _tbuf1data1;
372	rtems_unsigned32 _tbuf1rba0;
373	rtems_unsigned32 _tbuf1crc;
374	rtems_unsigned16 _tbuf1bcnt;
375	rtems_unsigned16 _tx_len;
376	rtems_unsigned16 iaddr1;
377	rtems_unsigned16 iaddr2;
378	rtems_unsigned16 iaddr3;
379	rtems_unsigned16 iaddr4;
380	rtems_unsigned16 _boff_cnt;
381	rtems_unsigned16 taddr_l;
382	rtems_unsigned16 taddr_m;
383	rtems_unsigned16 taddr_h;
384	} ethernet;
385	} un;
386	} m821SCCENparms_t;
387
388	/*
389	* Receive and transmit function code register bits
390	* These apply to the function code registers of all devices, not just SCC.
391	*/
392	#define M821_RFCR_BO(x) ((x)<<3)
393	#define M821_RFCR_MOT (2<<3)
394	#define M821_RFCR_DMA_SPACE(x) (x)
395	#define M821_TFCR_BO(x) ((x)<<3)
396	#define M821_TFCR_MOT (2<<3)
397	#define M821_TFCR_DMA_SPACE(x) (x)
398
399	/*
400	*************************************************************************
401	* Serial Management Controllers *
402	*************************************************************************
403	*/
404	typedef struct m821SMCparms_ {
405	rtems_unsigned16 rbase;
406	rtems_unsigned16 tbase;
407	rtems_unsigned8 rfcr;
408	rtems_unsigned8 tfcr;
409	rtems_unsigned16 mrblr;
410	rtems_unsigned32 _rstate;
411	rtems_unsigned32 _pad0;
412	rtems_unsigned16 _rbptr;
413	rtems_unsigned16 _pad1;
414	rtems_unsigned32 _pad2;
415	rtems_unsigned32 _tstate;
416	rtems_unsigned32 _pad3;
417	rtems_unsigned16 _tbptr;
418	rtems_unsigned16 _pad4;
419	rtems_unsigned32 _pad5;
420	union {
421	struct {
422	rtems_unsigned16 max_idl;
423	rtems_unsigned16 _idlc;
424	rtems_unsigned16 brklen;
425	rtems_unsigned16 brkec;
426	rtems_unsigned16 brkcr;
427	rtems_unsigned16 _r_mask;
428	} uart;
429	struct {
430	rtems_unsigned16 _pad0[5];
431	} transparent;
432	} un;
433	} m821SMCparms_t;
434
435	/*
436	* Mode register
437	*/
438	#define M821_SMCMR_CLEN(x) ((x)<<11) /* Character length */
439	#define M821_SMCMR_2STOP (1<<10) /* 2 stop bits */
440	#define M821_SMCMR_PARITY (1<<9) /* Enable parity */
441	#define M821_SMCMR_EVEN (1<<8) /* Even parity */
442	#define M821_SMCMR_SM_GCI (0<<4) /* GCI Mode */
443	#define M821_SMCMR_SM_UART (2<<4) /* UART Mode */
444	#define M821_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
445	#define M821_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
446	#define M821_SMCMR_DM_ECHO (2<<2) /* Echo mode */
447	#define M821_SMCMR_TEN (1<<1) /* Enable transmitter */
448	#define M821_SMCMR_REN (1<<0) /* Enable receiver */
449
450	/*
451	* Event and mask registers (SMCE, SMCM)
452	*/
453	#define M821_SMCE_BRKE (1<<6)
454	#define M821_SMCE_BRK (1<<4)
455	#define M821_SMCE_BSY (1<<2)
456	#define M821_SMCE_TX (1<<1)
457	#define M821_SMCE_RX (1<<0)
458
459	/*
460	*************************************************************************
461	* Serial Peripheral Interface *
462	*************************************************************************
463	*/
464	typedef struct m821SPIparms_ {
465	rtems_unsigned16 rbase;
466	rtems_unsigned16 tbase;
467	rtems_unsigned8 rfcr;
468	rtems_unsigned8 tfcr;
469	rtems_unsigned16 mrblr;
470	rtems_unsigned32 _rstate;
471	rtems_unsigned32 _pad0;
472	rtems_unsigned16 _rbptr;
473	rtems_unsigned16 _pad1;
474	rtems_unsigned32 _pad2;
475	rtems_unsigned32 _tstate;
476	rtems_unsigned32 _pad3;
477	rtems_unsigned16 _tbptr;
478	rtems_unsigned16 _pad4;
479	rtems_unsigned32 _pad5;
480	} m821SPIparms_t;
481
482	/*
483	* Mode register (SPMODE)
484	*/
485	#define M821_SPMODE_LOOP (1<<14) /* Local loopback mode */
486	#define M821_SPMODE_CI (1<<13) /* Clock invert */
487	#define M821_SPMODE_CP (1<<12) /* Clock phase */
488	#define M821_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
489	#define M821_SPMODE_REV (1<<10) /* Reverse data */
490	#define M821_SPMODE_MASTER (1<<9) /* SPI is master */
491	#define M821_SPMODE_EN (1<<8) /* Enable SPI */
492	#define M821_SPMODE_CLEN(x) ((x)<<4) /* Character length */
493	#define M821_SPMODE_PM(x) (x) /* Prescaler modulus */
494
495	/*
496	* Mode register (SPCOM)
497	*/
498	#define M821_SPCOM_STR (1<<7) /* Start transmit */
499
500	/*
501	* Event and mask registers (SPIE, SPIM)
502	*/
503	#define M821_SPIE_MME (1<<5) /* Multi-master error */
504	#define M821_SPIE_TXE (1<<4) /* Tx error */
505	#define M821_SPIE_BSY (1<<2) /* Busy condition*/
506	#define M821_SPIE_TXB (1<<1) /* Tx buffer */
507	#define M821_SPIE_RXB (1<<0) /* Rx buffer */
508
509	/*
510	*************************************************************************
511	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
512	*************************************************************************
513	*/
514	typedef struct m821BufferDescriptor_ {
515	rtems_unsigned16 status;
516	rtems_unsigned16 length;
517	volatile void *buffer;
518	} m821BufferDescriptor_t;
519
520	/*
521	* Bits in receive buffer descriptor status word
522	*/
523	#define M821_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
524	#define M821_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
525	#define M821_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
526	#define M821_BD_LAST (1<<11) /* Ethernet, SPI */
527	#define M821_BD_CONTROL_CHAR (1<<11) /* SCC UART */
528	#define M821_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
529	#define M821_BD_ADDRESS (1<<10) /* SCC UART */
530	#define M821_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
531	#define M821_BD_MISS (1<<8) /* Ethernet */
532	#define M821_BD_IDLE (1<<8) /* SCC UART, SMC UART */
533	#define M821_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
534	#define M821_BD_LONG (1<<5) /* Ethernet */
535	#define M821_BD_BREAK (1<<5) /* SCC UART, SMC UART */
536	#define M821_BD_NONALIGNED (1<<4) /* Ethernet */
537	#define M821_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
538	#define M821_BD_SHORT (1<<3) /* Ethernet */
539	#define M821_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
540	#define M821_BD_CRC_ERROR (1<<2) /* Ethernet */
541	#define M821_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
542	#define M821_BD_COLLISION (1<<0) /* Ethernet */
543	#define M821_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
544	#define M821_BD_MASTER_ERROR (1<<0) /* SPI */
545
546	/*
547	* Bits in transmit buffer descriptor status word
548	* Many bits have the same meaning as those in receiver buffer descriptors.
549	*/
550	#define M821_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
551	#define M821_BD_PAD (1<<14) /* Ethernet */
552	#define M821_BD_CTS_REPORT (1<<11) /* SCC UART */
553	#define M821_BD_TX_CRC (1<<10) /* Ethernet */
554	#define M821_BD_DEFER (1<<9) /* Ethernet */
555	#define M821_BD_HEARTBEAT (1<<8) /* Ethernet */
556	#define M821_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
557	#define M821_BD_LATE_COLLISION (1<<7) /* Ethernet */
558	#define M821_BD_NO_STOP_BIT (1<<7) /* SCC UART */
559	#define M821_BD_RETRY_LIMIT (1<<6) /* Ethernet */
560	#define M821_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
561	#define M821_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
562	#define M821_BD_CARRIER_LOST (1<<0) /* Ethernet */
563	#define M821_BD_CTS_LOST (1<<0) /* SCC UART */
564
565	/*
566	*************************************************************************
567	* IDMA Buffer Descriptors *
568	*************************************************************************
569	*/
570	typedef struct m821IDMABufferDescriptor_ {
571	rtems_unsigned16 status;
572	rtems_unsigned8 dfcr;
573	rtems_unsigned8 sfcr;
574	rtems_unsigned32 length;
575	void *source;
576	void *destination;
577	} m821IDMABufferDescriptor_t;
578
579	/*
580	*************************************************************************
581	* RISC Communication Processor Module Command Register (CR) *
582	*************************************************************************
583	*/
584	#define M821_CR_RST (1<<15) /* Reset communication processor */
585	#define M821_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
586	#define M821_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
587	#define M821_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
588	#define M821_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
589	#define M821_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
590	#define M821_CR_OP_GR_STOP_TX (5<<8) /* SCC */
591	#define M821_CR_OP_INIT_IDMA (5<<8) /* IDMA */
592	#define M821_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
593	#define M821_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
594	#define M821_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
595	#define M821_CR_OP_SET_TIMER (8<<8) /* Timer */
596	#define M821_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
597	#define M821_CR_OP_RESERT_BCS (10<<8) /* SCC */
598	#define M821_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
599	#define M821_CR_OP_STOP_IDMA (11<<8) /* IDMA */
600	#define M821_CR_OP_START_DSP (12<<8) /* DSP */
601	#define M821_CR_OP_INIT_DSP (13<<8) /* DSP */
602
603	#define M821_CR_CHAN_SCC1 (0<<4) /* Channel selection */
604	#define M821_CR_CHAN_I2C (1<<4)
605	#define M821_CR_CHAN_IDMA1 (1<<4)
606	#define M821_CR_CHAN_SCC2 (4<<4)
607	#define M821_CR_CHAN_SPI (5<<4)
608	#define M821_CR_CHAN_IDMA2 (5<<4)
609	#define M821_CR_CHAN_TIMER (5<<4)
610	#define M821_CR_CHAN_SCC3 (8<<4)
611	#define M821_CR_CHAN_SMC1 (9<<4)
612	#define M821_CR_CHAN_DSP1 (9<<4)
613	#define M821_CR_CHAN_SCC4 (12<<4)
614	#define M821_CR_CHAN_SMC2 (13<<4)
615	#define M821_CR_CHAN_DSP2 (13<<4)
616	#define M821_CR_FLG (1<<0) /* Command flag */
617
618	/*
619	*************************************************************************
620	* System Protection Control Register (SYPCR) *
621	*************************************************************************
622	*/
623	#define M821_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
624	#define M821_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
625	#define M821_SYPCR_BME (1<<7) /* Bus monitor enable */
626	#define M821_SYPCR_SWF (1<<3) /* Software watchdog freeze */
627	#define M821_SYPCR_SWE (1<<2) /* Software watchdog enable */
628	#define M821_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
629	#define M821_SYPCR_SWP (1<<0) /* Software watchdog prescale */
630
631	/*
632	*************************************************************************
633	* Memory Control Registers *
634	*************************************************************************
635	*/
636	#define M821_UPM_AMX_8col (0<<20) /* 8 column DRAM */
637	#define M821_UPM_AMX_9col (1<<20) /* 9 column DRAM */
638	#define M821_UPM_AMX_10col (2<<20) /* 10 column DRAM */
639	#define M821_UPM_AMX_11col (3<<20) /* 11 column DRAM */
640	#define M821_UPM_AMX_12col (4<<20) /* 12 column DRAM */
641	#define M821_UPM_AMX_13col (5<<20) /* 13 column DRAM */
642	#define M821_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
643	#define M821_MSR_WPER (1<<7) /* Write protection error */
644	#define M821_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
645	#define M821_BR_BA(x) ((x)&0xffff8000) /* Base address */
646	#define M821_BR_AT(x) ((x)<<12) /* Address type */
647	#define M821_BR_PS8 (1<<10) /* 8 bit port */
648	#define M821_BR_PS16 (2<<10) /* 16 bit port */
649	#define M821_BR_PS32 (0<<10) /* 32 bit port */
650	#define M821_BR_PARE (1<<9) /* Parity checking enable */
651	#define M821_BR_WP (1<<8) /* Write protect */
652	#define M821_BR_MS_GPCM (0<<6) /* GPCM */
653	#define M821_BR_MS_UPMA (2<<6) /* UPM A */
654	#define M821_BR_MS_UPMB (3<<6) /* UPM B */
655	#define M821_MEMC_BR_V (1<<0) /* Base/Option register are valid */
656
657	#define M821_MEMC_OR_32K 0xffff8000 /* Address range */
658	#define M821_MEMC_OR_64K 0xffff0000
659	#define M821_MEMC_OR_128K 0xfffe0000
660	#define M821_MEMC_OR_256K 0xfffc0000
661	#define M821_MEMC_OR_512K 0xfff80000
662	#define M821_MEMC_OR_1M 0xfff00000
663	#define M821_MEMC_OR_2M 0xffe00000
664	#define M821_MEMC_OR_4M 0xffc00000
665	#define M821_MEMC_OR_8M 0xff800000
666	#define M821_MEMC_OR_16M 0xff000000
667	#define M821_MEMC_OR_32M 0xfe000000
668	#define M821_MEMC_OR_64M 0xfc000000
669	#define M821_MEMC_OR_128 0xf8000000
670	#define M821_MEMC_OR_256M 0xf0000000
671	#define M821_MEMC_OR_512M 0xe0000000
672	#define M821_MEMC_OR_1G 0xc0000000
673	#define M821_MEMC_OR_2G 0x80000000
674	#define M821_MEMC_OR_4G 0x00000000
675	#define M821_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
676	#define M821_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
677	#define M821_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
678	#define M821_MEMC_OR_ACS_NORM (0<<9) /* CS asserted with addr lines /
679	#define M821_MEMC_OR_ACS_QRTR (2<<9) /* CS asserted 1/4 after addr /
680	#define M821_MEMC_OR_ACS_HALF (3<<9) /* CS asserted 1/2 after addr /
681	#define M821_MEMC_OR_BI (1<8) /* Burst inhibit */
682	#define M821_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
683	#define M821_MEMC_OR_SETA (1<<3) /* TA generated externally /
684	#define M821_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
685	#define M821_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
686
687	/*
688	*************************************************************************
689	* UPM Registers (MxMR) *
690	*************************************************************************
691	*/
692	#define M821_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
693	#define M821_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
694	#define M821_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
695	#define M821_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
696	#define M821_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
697	#define M821_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
698	#define M821_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
699	#define M821_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
700	/*
701	*************************************************************************
702	* Memory Command Register (MCR) *
703	*************************************************************************
704	*/
705	#define M821_MEMC_MCR_WRITE (0<<30) /* WRITE command */
706	#define M821_MEMC_MCR_READ (1<<30) /* READ command */
707	#define M821_MEMC_MCR_RUN (2<<30) /* RUN command */
708	#define M821_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
709	#define M821_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
710	#define M821_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
711	#define M821_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
712	#define M821_MEMC_MCR_MAD(x) (x) /* Machine address */
713
714
715
716	/*
717	*************************************************************************
718	* SI Mode Register (SIMODE) *
719	*************************************************************************
720	*/
721	#define M821_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
722	#define M821_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
723	#define M821_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
724	#define M821_SI_SMC2_BRG2 (1<<28)
725	#define M821_SI_SMC2_BRG3 (2<<28)
726	#define M821_SI_SMC2_BRG4 (3<<28)
727	#define M821_SI_SMC2_CLK5 (0<<28)
728	#define M821_SI_SMC2_CLK6 (1<<28)
729	#define M821_SI_SMC2_CLK7 (2<<28)
730	#define M821_SI_SMC2_CLK8 (3<<28)
731	#define M821_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
732	#define M821_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
733	#define M821_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
734	#define M821_SI_SMC1_BRG2 (1<<12)
735	#define M821_SI_SMC1_BRG3 (2<<12)
736	#define M821_SI_SMC1_BRG4 (3<<12)
737	#define M821_SI_SMC1_CLK1 (0<<12)
738	#define M821_SI_SMC1_CLK2 (1<<12)
739	#define M821_SI_SMC1_CLK3 (2<<12)
740	#define M821_SI_SMC1_CLK4 (3<<12)
741
742	/*
743	*************************************************************************
744	* SDMA Configuration Register (SDCR) *
745	*************************************************************************
746	*/
747	#define M821_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
748	#define M821_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
749
750	/*
751	*************************************************************************
752	* SDMA Status Register (SDSR) *
753	*************************************************************************
754	*/
755	#define M821_SDSR_SBER (1<<7) /* SDMA Channel bus error */
756	#define M821_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
757	#define M821_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
758
759	/*
760	*************************************************************************
761	* Baud (sic) Rate Generators *
762	*************************************************************************
763	*/
764	#define M821_BRG_RST (1<<17) /* Reset generator */
765	#define M821_BRG_EN (1<<16) /* Enable generator */
766	#define M821_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
767	#define M821_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
768	#define M821_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
769	#define M821_BRG_ATB (1<<13) /* Autobaud */
770	#define M821_BRG_115200 (21<<1) /* Assume 40 MHz clock */
771	#define M821_BRG_57600 (32<<1)
772	#define M821_BRG_38400 (64<<1)
773	#define M821_BRG_19200 (129<<1)
774	#define M821_BRG_9600 (259<<1)
775	#define M821_BRG_4800 (520<<1)
776	#define M821_BRG_2400 (1040<<1)
777	#define M821_BRG_1200 (2082<<1)
778	#define M821_BRG_600 ((259<<1) \| 1)
779	#define M821_BRG_300 ((520<<1) \| 1)
780	#define M821_BRG_150 ((1040<<1) \| 1)
781	#define M821_BRG_75 ((2080<<1) \| 1)
782
783	#define M821_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
784	#define M821_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
785	#define M821_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
786	#define M821_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
787	#define M821_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
788	#define M821_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
789	#define M821_TGCR_STP1 (1<<1) /* Stop timer */
790	#define M821_TGCR_STP2 (1<<5) /* Stop timer */
791	#define M821_TGCR_STP3 (1<<9) /* Stop timer */
792	#define M821_TGCR_STP4 (1<<13) /* Stop timer */
793	#define M821_TGCR_RST1 (1<<0) /* Enable timer */
794	#define M821_TGCR_RST2 (1<<4) /* Enable timer */
795	#define M821_TGCR_RST3 (1<<8) /* Enable timer */
796	#define M821_TGCR_RST4 (1<<12) /* Enable timer */
797	#define M821_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
798	#define M821_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
799
800	#define M821_TMR_PS(x) ((x)<<8) /* Timer prescaler */
801	#define M821_TMR_CE_RISE (1<<6) /* Capture on rising edge */
802	#define M821_TMR_CE_FALL (2<<6) /* Capture on falling edge */
803	#define M821_TMR_CE_ANY (3<<6) /* Capture on any edge */
804	#define M821_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
805	#define M821_TMR_ORI (1<<4) /* Interrupt on reaching reference */
806	#define M821_TMR_RESTART (1<<3) /* Restart timer after reference */
807	#define M821_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
808	#define M821_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
809	#define M821_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
810	#define M821_TMR_TGATE (1<<0) /* TGATE controls timer */
811
812	#define M821_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
813	#define M821_PISCR_PS (1<<7) /* PIT Interrupt state */
814	#define M821_PISCR_PIE (1<<2) /* PIT interrupt enable */
815	#define M821_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
816	#define M821_PISCR_PTE (1<<0) /* PIT enable */
817
818	#define M821_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
819	#define M821_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
820	#define M821_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
821	#define M821_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
822	#define M821_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
823	#define M821_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
824	#define M821_TBSCR_TBE (1<<0) /* enable TB and decrementer */
825
826	#define M821_SIMASK_IRM0 (1<<31)
827	#define M821_SIMASK_LVM0 (1<<30)
828	#define M821_SIMASK_IRM1 (1<<29)
829	#define M821_SIMASK_LVM1 (1<<28)
830	#define M821_SIMASK_IRM2 (1<<27)
831	#define M821_SIMASK_LVM2 (1<<26)
832	#define M821_SIMASK_IRM3 (1<<25)
833	#define M821_SIMASK_LVM3 (1<<24)
834	#define M821_SIMASK_IRM4 (1<<23)
835	#define M821_SIMASK_LVM4 (1<<22)
836	#define M821_SIMASK_IRM5 (1<<21)
837	#define M821_SIMASK_LVM5 (1<<20)
838	#define M821_SIMASK_IRM6 (1<<19)
839	#define M821_SIMASK_LVM6 (1<<18)
840	#define M821_SIMASK_IRM7 (1<<17)
841	#define M821_SIMASK_LVM7 (1<<16)
842
843	#define M821_SIUMCR_EARB (1<<31)
844	#define M821_SIUMCR_EARP0 (0<<28)
845	#define M821_SIUMCR_EARP1 (1<<28)
846	#define M821_SIUMCR_EARP2 (2<<28)
847	#define M821_SIUMCR_EARP3 (3<<28)
848	#define M821_SIUMCR_EARP4 (4<<28)
849	#define M821_SIUMCR_EARP5 (5<<28)
850	#define M821_SIUMCR_EARP6 (6<<28)
851	#define M821_SIUMCR_EARP7 (7<<28)
852	#define M821_SIUMCR_DSHW (1<<23)
853	#define M821_SIUMCR_DBGC0 (0<<21)
854	#define M821_SIUMCR_DBGC1 (1<<21)
855	#define M821_SIUMCR_DBGC2 (2<<21)
856	#define M821_SIUMCR_DBGC3 (3<<21)
857	#define M821_SIUMCR_DBPC0 (0<<19)
858	#define M821_SIUMCR_DBPC1 (1<<19)
859	#define M821_SIUMCR_DBPC2 (2<<19)
860	#define M821_SIUMCR_DBPC3 (3<<19)
861	#define M821_SIUMCR_FRC (1<<17)
862	#define M821_SIUMCR_DLK (1<<16)
863	#define M821_SIUMCR_PNCS (1<<15)
864	#define M821_SIUMCR_OPAR (1<<14)
865	#define M821_SIUMCR_DPC (1<<13)
866	#define M821_SIUMCR_MPRE (1<<12)
867	#define M821_SIUMCR_MLRC0 (0<<10)
868	#define M821_SIUMCR_MLRC1 (1<<10)
869	#define M821_SIUMCR_MLRC2 (2<<10)
870	#define M821_SIUMCR_MLRC3 (3<<10)
871	#define M821_SIUMCR_AEME (1<<9)
872	#define M821_SIUMCR_SEME (1<<8)
873	#define M821_SIUMCR_BSC (1<<7)
874	#define M821_SIUMCR_GB5E (1<<6)
875	#define M821_SIUMCR_B2DD (1<<5)
876	#define M821_SIUMCR_B3DD (1<<4)
877	/*
878	*************************************************************************
879	* MPC821 DUAL-PORT RAM AND REGISTERS *
880	*************************************************************************
881	*/
882	typedef struct m821_ {
883
884	/*
885	* SIU Block
886	*/
887	rtems_unsigned32 siumcr;
888	rtems_unsigned32 sypcr;
889	rtems_unsigned32 _pad70;
890	rtems_unsigned16 _pad0;
891	rtems_unsigned16 swsr;
892	rtems_unsigned32 sipend;
893	rtems_unsigned32 simask;
894	rtems_unsigned32 siel;
895	rtems_unsigned32 sivec;
896	rtems_unsigned32 tesr;
897	rtems_unsigned32 _pad1[3];
898	rtems_unsigned32 sdcr;
899	rtems_unsigned8 _pad2[0x80-0x34];
900
901	/*
902	* PCMCIA Block
903	*/
904	rtems_unsigned32 pbr0;
905	rtems_unsigned32 por0;
906	rtems_unsigned32 pbr1;
907	rtems_unsigned32 por1;
908	rtems_unsigned32 pbr2;
909	rtems_unsigned32 por2;
910	rtems_unsigned32 pbr3;
911	rtems_unsigned32 por3;
912	rtems_unsigned32 pbr4;
913	rtems_unsigned32 por4;
914	rtems_unsigned32 pbr5;
915	rtems_unsigned32 por5;
916	rtems_unsigned32 pbr6;
917	rtems_unsigned32 por6;
918	rtems_unsigned32 pbr7;
919	rtems_unsigned32 por7;
920	rtems_unsigned8 _pad3[0xe0-0xc0];
921	rtems_unsigned32 pgcra;
922	rtems_unsigned32 pgcrb;
923	rtems_unsigned32 pscr;
924	rtems_unsigned32 _pad4;
925	rtems_unsigned32 pipr;
926	rtems_unsigned32 _pad5;
927	rtems_unsigned32 per;
928	rtems_unsigned32 _pad6;
929
930	/*
931	* MEMC Block
932	*/
933	m821MEMCRegisters_t memc[8];
934	rtems_unsigned8 _pad7[0x164-0x140];
935	rtems_unsigned32 mar;
936	rtems_unsigned32 mcr;
937	rtems_unsigned32 _pad8;
938	rtems_unsigned32 mamr;
939	rtems_unsigned32 mbmr;
940	rtems_unsigned16 mstat;
941	rtems_unsigned16 mptpr;
942	rtems_unsigned32 mdr;
943	rtems_unsigned8 _pad9[0x200-0x180];
944
945	/*
946	* System integration timers
947	*/
948	rtems_unsigned16 tbscr;
949	rtems_unsigned16 _pad10;
950	rtems_unsigned32 tbreff0;
951	rtems_unsigned32 tbreff1;
952	rtems_unsigned8 _pad11[0x220-0x20c];
953	rtems_unsigned16 rtcsc;
954	rtems_unsigned16 _pad12;
955	rtems_unsigned32 rtc;
956	rtems_unsigned32 rtsec;
957	rtems_unsigned32 rtcal;
958	rtems_unsigned32 _pad13[4];
959	rtems_unsigned16 piscr;
960	rtems_unsigned16 _pad14;
961	rtems_unsigned16 pitc;
962	rtems_unsigned16 _pad_14_1;
963	rtems_unsigned16 pitr;
964	rtems_unsigned16 _pad_14_2;
965	rtems_unsigned8 _pad15[0x280-0x24c];
966
967
968	/*
969	* Clocks and Reset
970	*/
971	rtems_unsigned32 sccr;
972	rtems_unsigned32 plprcr;
973	rtems_unsigned32 rsr;
974	rtems_unsigned8 _pad16[0x300-0x28c];
975
976
977	/*
978	* System integration timers keys
979	*/
980	rtems_unsigned32 tbscrk;
981	rtems_unsigned32 tbreff0k;
982	rtems_unsigned32 tbreff1k;
983	rtems_unsigned32 tbk;
984	rtems_unsigned32 _pad17[4];
985	rtems_unsigned32 rtcsk;
986	rtems_unsigned32 rtck;
987	rtems_unsigned32 rtseck;
988	rtems_unsigned32 rtcalk;
989	rtems_unsigned32 _pad18[4];
990	rtems_unsigned32 piscrk;
991	rtems_unsigned32 pitck;
992	rtems_unsigned8 _pad19[0x380-0x348];
993
994	/*
995	* Clocks and Reset Keys
996	*/
997	rtems_unsigned32 sccrk;
998	rtems_unsigned32 plprck;
999	rtems_unsigned32 rsrk;
1000	rtems_unsigned8 _pad20[0x400-0x38c];
1001	rtems_unsigned8 _pad21[0x800-0x400];
1002	rtems_unsigned8 _pad22[0x860-0x800];
1003
1004
1005	/*
1006	* I2C
1007	*/
1008	rtems_unsigned8 i2mod;
1009	rtems_unsigned8 _pad23[3];
1010	rtems_unsigned8 i2add;
1011	rtems_unsigned8 _pad24[3];
1012	rtems_unsigned8 i2brg;
1013	rtems_unsigned8 _pad25[3];
1014	rtems_unsigned8 i2com;
1015	rtems_unsigned8 _pad26[3];
1016	rtems_unsigned8 i2cer;
1017	rtems_unsigned8 _pad27[3];
1018	rtems_unsigned8 i2cmr;
1019	rtems_unsigned8 _pad28[0x900-0x875];
1020
1021	/*
1022	* DMA Block
1023	*/
1024	rtems_unsigned32 _pad29;
1025	rtems_unsigned32 sdar;
1026	rtems_unsigned8 sdsr;
1027	rtems_unsigned8 _pad30[3];
1028	rtems_unsigned8 sdmr;
1029	rtems_unsigned8 _pad31[3];
1030	rtems_unsigned8 idsr1;
1031	rtems_unsigned8 _pad32[3];
1032	rtems_unsigned8 idmr1;
1033	rtems_unsigned8 _pad33[3];
1034	rtems_unsigned8 idsr2;
1035	rtems_unsigned8 _pad34[3];
1036	rtems_unsigned8 idmr2;
1037	rtems_unsigned8 _pad35[0x930-0x91d];
1038
1039
1040
1041	/*
1042	* CPM Interrupt Control Block
1043	*/
1044	rtems_unsigned16 civr;
1045	rtems_unsigned8 _pad36[14];
1046	rtems_unsigned32 cicr;
1047	rtems_unsigned32 cipr;
1048	rtems_unsigned32 cimr;
1049	rtems_unsigned32 cisr;
1050
1051	/*
1052	* I/O Port Block
1053	*/
1054	rtems_unsigned16 padir;
1055	rtems_unsigned16 papar;
1056	rtems_unsigned16 paodr;
1057	rtems_unsigned16 padat;
1058	rtems_unsigned8 _pad37[8];
1059	rtems_unsigned16 pcdir;
1060	rtems_unsigned16 pcpar;
1061	rtems_unsigned16 pcso;
1062	rtems_unsigned16 pcdat;
1063	rtems_unsigned16 pcint;
1064	rtems_unsigned8 _pad39[6];
1065	rtems_unsigned16 pddir;
1066	rtems_unsigned16 pdpar;
1067	rtems_unsigned16 _pad40;
1068	rtems_unsigned16 pddat;
1069	rtems_unsigned8 _pad41[8];
1070
1071	/*
1072	* CPM Timers Block
1073	*/
1074	rtems_unsigned16 tgcr;
1075	rtems_unsigned8 _pad42[14];
1076	rtems_unsigned16 tmr1;
1077	rtems_unsigned16 tmr2;
1078	rtems_unsigned16 trr1;
1079	rtems_unsigned16 trr2;
1080	rtems_unsigned16 tcr1;
1081	rtems_unsigned16 tcr2;
1082	rtems_unsigned16 tcn1;
1083	rtems_unsigned16 tcn2;
1084	rtems_unsigned16 tmr3;
1085	rtems_unsigned16 tmr4;
1086	rtems_unsigned16 trr3;
1087	rtems_unsigned16 trr4;
1088	rtems_unsigned16 tcr3;
1089	rtems_unsigned16 tcr4;
1090	rtems_unsigned16 tcn3;
1091	rtems_unsigned16 tcn4;
1092	rtems_unsigned16 ter1;
1093	rtems_unsigned16 ter2;
1094	rtems_unsigned16 ter3;
1095	rtems_unsigned16 ter4;
1096	rtems_unsigned8 _pad43[8];
1097
1098
1099
1100	/*
1101	* CPM Block
1102	*/
1103	rtems_unsigned16 cpcr;
1104	rtems_unsigned16 _pad44;
1105	rtems_unsigned16 rccr;
1106	rtems_unsigned8 _pad45;
1107	rtems_unsigned8 rmds;
1108	rtems_unsigned32 rmdr;
1109	rtems_unsigned16 rctr1;
1110	rtems_unsigned16 rctr2;
1111	rtems_unsigned16 rctr3;
1112	rtems_unsigned16 rctr4;
1113	rtems_unsigned16 _pad46;
1114	rtems_unsigned16 rter;
1115	rtems_unsigned16 _pad47;
1116	rtems_unsigned16 rtmr;
1117	rtems_unsigned8 _pad48[0x9f0-0x9dc];
1118
1119	/*
1120	* BRG Block
1121	*/
1122	rtems_unsigned32 brgc1;
1123	rtems_unsigned32 brgc2;
1124	rtems_unsigned32 brgc3;
1125	rtems_unsigned32 brgc4;
1126
1127	/*
1128	* SCC Block
1129	*/
1130	m821SCCRegisters_t scc1;
1131	m821SCCRegisters_t scc2;
1132	rtems_unsigned8 _pad72[0xa80-0xa40];
1133
1134	/*
1135	* SMC Block
1136	*/
1137	m821SMCRegisters_t smc1;
1138	m821SMCRegisters_t smc2;
1139
1140	/*
1141	* SPI Block
1142	*/
1143	rtems_unsigned16 spmode;
1144	rtems_unsigned16 _pad49[2];
1145	rtems_unsigned8 spie;
1146	rtems_unsigned8 _pad50;
1147	rtems_unsigned16 _pad51;
1148	rtems_unsigned8 spim;
1149	rtems_unsigned8 _pad52[2];
1150	rtems_unsigned8 spcom;
1151	rtems_unsigned16 _pad53[2];
1152
1153	/*
1154	* PIP Block
1155	*/
1156	rtems_unsigned16 pipc;
1157	rtems_unsigned16 _pad54;
1158	rtems_unsigned16 ptpr;
1159	rtems_unsigned32 pbdir;
1160	rtems_unsigned32 pbpar;
1161	rtems_unsigned16 _pad55;
1162	rtems_unsigned16 pbodr;
1163	rtems_unsigned32 pbdat;
1164	rtems_unsigned32 _pad56[6];
1165
1166	/*
1167	* SI Block
1168	*/
1169	rtems_unsigned32 simode;
1170	rtems_unsigned8 sigmr;
1171	rtems_unsigned8 _pad57;
1172	rtems_unsigned8 sistr;
1173	rtems_unsigned8 sicmr;
1174	rtems_unsigned32 _pad58;
1175	rtems_unsigned32 sicr;
1176	rtems_unsigned16 sirp[2];
1177	rtems_unsigned32 _pad59[3];
1178	rtems_unsigned8 _pad60[0xc00-0xb00];
1179	rtems_unsigned8 siram[512];
1180	rtems_unsigned8 lcdram[512];
1181
1182	rtems_unsigned8 _pad62[0x2000-0x1000];
1183	/*
1184	* Dual-port RAM
1185	*/
1186	rtems_unsigned8 dpram0[0x200]; /* BD/DATA/UCODE */
1187	rtems_unsigned8 dpram1[0x200]; /* BD/DATA/UCODE */
1188	rtems_unsigned8 dpram2[0x400]; /* BD/DATA/UCODE */
1189	rtems_unsigned8 dpram3[0x600]; /* BD/DATA*/
1190	rtems_unsigned8 dpram4[0x200]; /* BD/DATA/UCODE */
1191	rtems_unsigned8 _pad63[0x3c00-0x3000];
1192
1193	/* When using SCC1 for ethernet, we lose the use of I2C since
1194	* their parameters would overlap. Motorola has a microcode
1195	* patch to move parameters around so that both can be used
1196	* together. It is available on their web site somewhere
1197	* under http://www.mot.com/mpc821. If ethernet is used on
1198	* one (or more) of the other SCCs, then other CPM features
1199	* will be unavailable:
1200	* SCC2 -> lose SPI
1201	* However, Ethernet only works on SCC1 on the 821.
1202	*/
1203	m821SCCENparms_t scc1p;
1204	rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m821SCCENparms_t)];
1205	m821MiscParms_t miscp;
1206	rtems_unsigned8 _rsv2[0xcc0-0xCB0-sizeof(m821MiscParms_t)];
1207	m821IDMAparms_t idma1p;
1208	rtems_unsigned8 _rsv3[0xd00-0xcc0-sizeof(m821IDMAparms_t)];
1209
1210	m821SCCparms_t scc2p;
1211	rtems_unsigned8 _rsv4[0xD80-0xD00-sizeof(m821SCCparms_t)];
1212	m821SPIparms_t spip;
1213	rtems_unsigned8 _rsv5[0xDB0-0xD80-sizeof(m821SPIparms_t)];
1214	m821TimerParms_t tmp;
1215	rtems_unsigned8 _rsv6[0xDC0-0xDB0-sizeof(m821TimerParms_t)];
1216	m821IDMAparms_t idma2p;
1217	rtems_unsigned8 _rsv7[0xE00-0xDC0-sizeof(m821IDMAparms_t)];
1218
1219	m821SCCparms_t scc3p; /* Not used */
1220	rtems_unsigned8 _rsv8[0xE80-0xE00-sizeof(m821SCCparms_t)];
1221	m821SMCparms_t smc1p;
1222	rtems_unsigned8 _rsv9[0xEC0-0xE80-sizeof(m821SMCparms_t)];
1223	m821DSPparms_t dsp1p;
1224	rtems_unsigned8 _rsv10[0xF00-0xEC0-sizeof(m821DSPparms_t)];
1225
1226	m821SCCparms_t scc4p; /* Not used */
1227	rtems_unsigned8 _rsv11[0xF80-0xF00-sizeof(m821SCCparms_t)];
1228	m821SMCparms_t smc2p;
1229	rtems_unsigned8 _rsv12[0xFC0-0xF80-sizeof(m821SMCparms_t)];
1230	m821DSPparms_t dsp2p;
1231	rtems_unsigned8 _rsv13[0x1000-0xFC0-sizeof(m821DSPparms_t)];
1232	} m821_t;
1233
1234	extern volatile m821_t m821;
1235	#endif /* ASM */
1236
1237	#endif /* __MPC821_h */

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source: rtems/c/src/lib/libcpu/powerpc/mpc821/include/mpc821.h @ 817466c

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