1 | /* |
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2 | * General Serial I/O functions. |
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3 | * |
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4 | * This file contains the functions for performing serial I/O. |
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5 | * The actual system calls (console_*) should be in the BSP part |
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6 | * of the source tree. That way different BSPs can use whichever |
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7 | * SMCs and SCCs they want. Originally, all the stuff was in |
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8 | * this file, and it caused problems with one BSP using SCC2 |
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9 | * as /dev/console, others using SMC1 for /dev/console, etc. |
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10 | * |
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11 | * On-chip resources used: |
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12 | * resource minor note |
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13 | * SMC1 0 |
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14 | * SMC2 1 |
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15 | * SCC1 2 (shared with ethernet driver) |
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16 | * SCC2 3 |
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17 | * BRG1 |
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18 | * BRG2 |
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19 | * BRG3 |
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20 | * BRG4 |
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21 | * Author: Jay Monkman (jmonkman@frasca.com) |
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22 | * Copyright (C) 1998 by Frasca International, Inc. |
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23 | * |
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24 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: |
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25 | * |
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26 | * Author: |
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27 | * W. Eric Norum |
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28 | * Saskatchewan Accelerator Laboratory |
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29 | * University of Saskatchewan |
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30 | * Saskatoon, Saskatchewan, CANADA |
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31 | * eric@skatter.usask.ca |
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32 | * |
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33 | * COPYRIGHT (c) 1989-1999. |
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34 | * On-Line Applications Research Corporation (OAR). |
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35 | * |
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36 | * The license and distribution terms for this file may be |
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37 | * found in the file LICENSE in this distribution or at |
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38 | * |
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39 | * http://www.OARcorp.com/rtems/license.html. |
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40 | * |
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41 | * $Id$ |
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42 | */ |
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43 | |
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44 | #include <rtems/libio.h> |
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45 | #include <mpc821.h> |
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46 | #include <mpc821/console.h> |
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47 | #include <stdlib.h> |
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48 | #include <unistd.h> |
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49 | #include <termios.h> |
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50 | |
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51 | #define NIFACES 4 /* number of console devices (serial ports) */ |
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52 | |
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53 | static Buf_t *rxBufList[NIFACES]; |
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54 | static Buf_t *rxBufListTail[NIFACES]; |
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55 | |
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56 | /* |
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57 | * Interrupt-driven input buffer |
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58 | */ |
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59 | #define RXBUFSIZE 16 |
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60 | |
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61 | |
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62 | /* |
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63 | * I/O buffers and pointers to buffer descriptors |
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64 | */ |
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65 | static volatile char txBuf[NIFACES]; |
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66 | |
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67 | static volatile m821BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; |
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68 | |
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69 | /* |
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70 | * Device-specific routines |
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71 | */ |
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72 | static int m821_get_brg_cd(int); |
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73 | unsigned char m821_get_brg_clk(int); |
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74 | void m821_console_reserve_resources(rtems_configuration_table *); |
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75 | unsigned char m821_get_brg_clk(int); |
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76 | |
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77 | |
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78 | /* |
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79 | * Compute baud-rate-generator configuration register value |
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80 | */ |
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81 | static int |
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82 | m821_get_brg_cd (int baud) |
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83 | { |
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84 | int divisor; |
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85 | int div16 = 0; |
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86 | |
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87 | divisor = ((rtems_cpu_configuration_get_clock_speed() / 16) + |
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88 | (baud / 2)) / baud; |
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89 | if (divisor > 4096) { |
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90 | div16 = 1; |
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91 | divisor = (divisor + 8) / 16; |
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92 | } |
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93 | return M821_BRG_EN | M821_BRG_EXTC_BRGCLK | |
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94 | ((divisor - 1) << 1) | div16; |
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95 | } |
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96 | |
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97 | |
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98 | /* this function will fail if more that 4 baud rates have been selected */ |
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99 | /* at any time since the OS started. It needs to be fixed. FIXME */ |
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100 | unsigned char m821_get_brg_clk(int baud) |
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101 | { |
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102 | static int brg_spd[4]; |
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103 | static char brg_used[4]; |
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104 | int i; |
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105 | |
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106 | /* first try to find a BRG that is already at the right speed */ |
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107 | for (i=0; i<4; i++) { |
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108 | if (brg_spd[i] == baud) { |
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109 | break; |
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110 | } |
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111 | } |
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112 | |
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113 | if (i==4) { /* I guess we didn't find one */ |
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114 | for (i=0; i<4; i++) { |
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115 | if (brg_used[i] == 0) { |
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116 | break; |
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117 | } |
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118 | } |
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119 | } |
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120 | if (i != 4) { |
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121 | brg_used[i]++; |
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122 | brg_spd[i]=baud; |
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123 | switch (i) { |
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124 | case 0: |
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125 | m821.brgc1 = M821_BRG_RST; |
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126 | m821.brgc1 = m821_get_brg_cd(baud); |
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127 | break; |
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128 | case 1: |
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129 | m821.brgc2 = M821_BRG_RST; |
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130 | m821.brgc2 = m821_get_brg_cd(baud); |
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131 | break; |
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132 | case 2: |
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133 | m821.brgc3 = M821_BRG_RST; |
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134 | m821.brgc3 = m821_get_brg_cd(baud); |
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135 | break; |
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136 | case 3: |
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137 | m821.brgc4 = M821_BRG_RST; |
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138 | m821.brgc4 = m821_get_brg_cd(baud); |
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139 | break; |
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140 | } |
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141 | return i; |
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142 | } |
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143 | |
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144 | else |
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145 | return 0xff; |
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146 | } |
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147 | |
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148 | /* |
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149 | * Hardware-dependent portion of tcsetattr(). |
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150 | */ |
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151 | int |
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152 | m821_smc_set_attributes (int minor, const struct termios *t) |
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153 | { |
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154 | /* |
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155 | * minor must be 0 or 1 |
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156 | */ |
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157 | int baud; |
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158 | int brg; |
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159 | switch (t->c_cflag & CBAUD) { |
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160 | default: baud = -1; break; |
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161 | case B50: baud = 50; break; |
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162 | case B75: baud = 75; break; |
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163 | case B110: baud = 110; break; |
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164 | case B134: baud = 134; break; |
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165 | case B150: baud = 150; break; |
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166 | case B200: baud = 200; break; |
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167 | case B300: baud = 300; break; |
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168 | case B600: baud = 600; break; |
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169 | case B1200: baud = 1200; break; |
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170 | case B1800: baud = 1800; break; |
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171 | case B2400: baud = 2400; break; |
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172 | case B4800: baud = 4800; break; |
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173 | case B9600: baud = 9600; break; |
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174 | case B19200: baud = 19200; break; |
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175 | case B38400: baud = 38400; break; |
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176 | case B57600: baud = 57600; break; |
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177 | case B115200: baud = 115200; break; |
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178 | case B230400: baud = 230400; break; |
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179 | case B460800: baud = 460800; break; |
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180 | } |
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181 | if (baud > 0) { |
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182 | brg = m821_get_brg_clk(baud); /* 4 BRGs, 4 serial ports - hopefully */ |
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183 | /* at least 2 ports will be the same */ |
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184 | m821.simode |= brg << (12 + ((minor) * 16)); |
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185 | } |
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186 | return 0; |
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187 | } |
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188 | |
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189 | int |
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190 | m821_scc_set_attributes (int minor, const struct termios *t) |
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191 | { |
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192 | /* |
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193 | * minor must be 2, or 3 |
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194 | */ |
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195 | int baud; |
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196 | int brg; |
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197 | switch (t->c_cflag & CBAUD) { |
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198 | default: baud = -1; break; |
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199 | case B50: baud = 50; break; |
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200 | case B75: baud = 75; break; |
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201 | case B110: baud = 110; break; |
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202 | case B134: baud = 134; break; |
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203 | case B150: baud = 150; break; |
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204 | case B200: baud = 200; break; |
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205 | case B300: baud = 300; break; |
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206 | case B600: baud = 600; break; |
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207 | case B1200: baud = 1200; break; |
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208 | case B1800: baud = 1800; break; |
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209 | case B2400: baud = 2400; break; |
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210 | case B4800: baud = 4800; break; |
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211 | case B9600: baud = 9600; break; |
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212 | case B19200: baud = 19200; break; |
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213 | case B38400: baud = 38400; break; |
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214 | case B57600: baud = 57600; break; |
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215 | case B115200: baud = 115200; break; |
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216 | case B230400: baud = 230400; break; |
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217 | case B460800: baud = 460800; break; |
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218 | } |
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219 | if (baud > 0) { |
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220 | brg = m821_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ |
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221 | /* at least 2 ports will be the same */ |
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222 | m821.sicr |= (brg << (3 + ((minor-2) * 8))) | |
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223 | (brg << ((minor-2) * 8)); |
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224 | } |
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225 | return 0; |
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226 | } |
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227 | |
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228 | void |
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229 | m821_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ |
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230 | { |
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231 | unsigned char brg; |
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232 | volatile m821SCCparms_t *sccparms; |
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233 | volatile m821SCCRegisters_t *sccregs; |
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234 | |
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235 | /* |
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236 | * Allocate buffer descriptors |
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237 | */ |
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238 | RxBd[port+1] = M821AllocateBufferDescriptors(1); |
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239 | TxBd[port+1] = M821AllocateBufferDescriptors(1); |
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240 | |
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241 | /* |
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242 | * Configure ports A and B to enable TXDx and RXDx pins |
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243 | */ |
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244 | m821.papar |= (0xC << ((port-2) * 2)); |
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245 | m821.padir &= ~(0xC << ((port-2) * 2)); |
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246 | m821.pbdir |= (0x04 << (port-2)); |
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247 | m821.paodr &= ~(0x8 << ((port-2) * 2)); |
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248 | m821.pbdat &= ~(0x04 << (port-2)); |
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249 | |
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250 | /* SCC2 is the only one with handshaking lines */ |
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251 | /* |
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252 | if (port == 2) { |
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253 | m821.pcpar |= (0x02); |
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254 | m821.pcpar &= ~(0xc0); |
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255 | m821.pcdir &= ~(0xc2); |
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256 | m821.pcso |= (0xc0); |
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257 | } |
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258 | */ |
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259 | |
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260 | brg = m821_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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261 | /* at least 2 ports will be the same */ |
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262 | |
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263 | /* |
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264 | * Set up SDMA |
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265 | */ |
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266 | m821.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC821UM/AD */ |
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267 | |
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268 | |
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269 | m821.sicr &= ~(0xff << ((port-1) * 8)); |
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270 | m821.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); |
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271 | |
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272 | /* |
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273 | * Set up SCC1 parameter RAM common to all protocols |
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274 | */ |
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275 | if (port == 1) { |
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276 | sccparms = (m821SCCparms_t*)&m821.scc1p; |
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277 | sccregs = &m821.scc1; |
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278 | } |
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279 | else if (port == 2) { |
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280 | sccparms = &m821.scc2p; |
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281 | sccregs = &m821.scc2; |
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282 | } |
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283 | |
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284 | sccparms->rbase = (char *)RxBd[port+1] - (char *)&m821; |
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285 | sccparms->tbase = (char *)TxBd[port+1] - (char *)&m821; |
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286 | |
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287 | if (port == 1) |
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288 | M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SCC1); |
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289 | else if (port == 2) |
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290 | M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SCC2); |
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291 | |
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292 | sccparms->rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); |
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293 | sccparms->tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); |
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294 | sccparms->mrblr = RXBUFSIZE; |
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295 | |
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296 | sccparms->un.uart.max_idl = 10; |
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297 | sccparms->un.uart.brklen = 0; |
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298 | sccparms->un.uart.brkec = 0; |
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299 | sccparms->un.uart.brkcr = 1; |
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300 | |
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301 | sccparms->un.uart.parec = 0; |
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302 | sccparms->un.uart.frmec = 0; |
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303 | sccparms->un.uart.nosec = 0; |
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304 | |
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305 | sccparms->un.uart.uaddr[0] = 0; |
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306 | sccparms->un.uart.uaddr[1] = 0; |
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307 | sccparms->un.uart.toseq = 0; |
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308 | |
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309 | sccparms->un.uart.character[0] = 0x8000; |
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310 | sccparms->un.uart.character[1] = 0x8000; |
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311 | sccparms->un.uart.character[2] = 0x8000; |
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312 | sccparms->un.uart.character[3] = 0x8000; |
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313 | sccparms->un.uart.character[4] = 0x8000; |
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314 | sccparms->un.uart.character[5] = 0x8000; |
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315 | sccparms->un.uart.character[6] = 0x8000; |
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316 | sccparms->un.uart.character[7] = 0x8000; |
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317 | |
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318 | sccparms->un.uart.rccm = 0xc0ff; |
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319 | |
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320 | /* |
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321 | * Set up the Receive Buffer Descriptor |
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322 | */ |
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323 | RxBd[port+1]->status = M821_BD_EMPTY | M821_BD_WRAP | |
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324 | M821_BD_INTERRUPT; |
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325 | RxBd[port+1]->length = 0; |
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326 | RxBd[port+1]->buffer = malloc(RXBUFSIZE); |
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327 | |
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328 | /* |
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329 | * Setup the Transmit Buffer Descriptor |
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330 | */ |
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331 | TxBd[port+1]->status = M821_BD_WRAP; |
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332 | |
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333 | /* |
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334 | * Set up SCCx general and protocol-specific mode registers |
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335 | */ |
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336 | sccregs->scce = 0xffff; |
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337 | sccregs->sccm = 0x0000; |
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338 | sccregs->gsmr_h = 0x00000020; |
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339 | sccregs->gsmr_l = 0x00028004; |
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340 | sccregs->psmr = 0x3000; |
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341 | sccregs->gsmr_l = 0x00028034; |
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342 | } |
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343 | |
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344 | void |
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345 | m821_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ |
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346 | { |
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347 | unsigned char brg; |
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348 | |
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349 | /* |
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350 | * Allocate buffer descriptors |
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351 | */ |
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352 | RxBd[port-1] = M821AllocateBufferDescriptors (1); |
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353 | TxBd[port-1] = M821AllocateBufferDescriptors (1); |
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354 | |
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355 | /* |
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356 | * Configure port B pins to enable SMTXDx and SMRXDx pins |
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357 | */ |
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358 | m821.pbpar |= (0xC0 << ((port-1) * 4)); |
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359 | m821.pbdir &= ~(0xC0 << ((port-1) * 4)); |
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360 | m821.pbdir |= (0x01 << (port-1)); |
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361 | m821.pbodr &= ~(0xC0 << ((port-1) * 4)); |
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362 | m821.pbdat &= ~(0x01 << (port-1)); |
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363 | |
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364 | /* |
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365 | * Set up BRG1 (9,600 baud) |
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366 | */ |
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367 | brg = m821_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ |
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368 | /* at least 2 ports will be the same */ |
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369 | |
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370 | /* |
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371 | * Put SMC in NMSI mode, connect SMC to BRG |
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372 | */ |
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373 | m860.simode &= ~(0x7000 << ((port-1) * 16)); |
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374 | m860.simode |= brg << (12 + ((port-1) * 16)); |
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375 | |
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376 | /* |
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377 | * Set up SMC1 parameter RAM common to all protocols |
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378 | */ |
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379 | if (port == 1) { |
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380 | m821.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m821; |
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381 | m821.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m821; |
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382 | m821.smc1p.rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); |
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383 | m821.smc1p.tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); |
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384 | m821.smc1p.mrblr = RXBUFSIZE; |
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385 | |
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386 | /* |
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387 | * Set up SMC1 parameter RAM UART-specific parameters |
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388 | */ |
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389 | m821.smc1p.un.uart.max_idl = 10; |
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390 | m821.smc1p.un.uart.brklen = 0; |
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391 | m821.smc1p.un.uart.brkec = 0; |
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392 | m821.smc1p.un.uart.brkcr = 0; |
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393 | |
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394 | } |
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395 | else { |
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396 | m821.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m821; |
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397 | m821.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m821; |
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398 | m821.smc2p.rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); |
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399 | m821.smc2p.tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); |
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400 | m821.smc2p.mrblr = RXBUFSIZE; |
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401 | |
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402 | /* |
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403 | * Set up SMC2 parameter RAM UART-specific parameters |
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404 | */ |
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405 | m821.smc2p.un.uart.max_idl = 10; |
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406 | m821.smc2p.un.uart.brklen = 0; |
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407 | m821.smc2p.un.uart.brkec = 0; |
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408 | m821.smc2p.un.uart.brkcr = 0; |
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409 | } |
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410 | |
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411 | /* |
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412 | * Set up the Receive Buffer Descriptor |
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413 | */ |
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414 | RxBd[port-1]->status = M821_BD_EMPTY | M821_BD_WRAP | |
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415 | M821_BD_INTERRUPT; |
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416 | RxBd[port-1]->length = 0; |
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417 | RxBd[port-1]->buffer = malloc(RXBUFSIZE); |
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418 | |
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419 | /* |
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420 | * Setup the Transmit Buffer Descriptor |
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421 | */ |
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422 | TxBd[port-1]->status = M821_BD_WRAP; |
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423 | |
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424 | /* |
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425 | * Set up SMCx general and protocol-specific mode registers |
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426 | */ |
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427 | if (port == 1) { |
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428 | m821.smc1.smce = ~0; /* Clear any pending events */ |
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429 | m821.smc1.smcm = 0; /* Mask all interrupt/event sources */ |
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430 | m821.smc1.smcmr = M821_SMCMR_CLEN(9) | M821_SMCMR_SM_UART; |
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431 | |
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432 | /* |
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433 | * Send "Init parameters" command |
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434 | */ |
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435 | M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SMC1); |
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436 | |
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437 | /* |
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438 | * Enable receiver and transmitter |
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439 | */ |
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440 | m821.smc1.smcmr |= M821_SMCMR_TEN | M821_SMCMR_REN; |
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441 | } |
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442 | else { |
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443 | m821.smc2.smce = ~0; /* Clear any pending events */ |
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444 | m821.smc2.smcm = 0; /* Mask all interrupt/event sources */ |
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445 | m821.smc2.smcmr = M821_SMCMR_CLEN(9) | M821_SMCMR_SM_UART; |
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446 | |
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447 | /* |
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448 | * Send "Init parameters" command |
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449 | */ |
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450 | M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SMC2); |
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451 | |
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452 | /* |
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453 | * Enable receiver and transmitter |
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454 | */ |
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455 | m821.smc2.smcmr |= M821_SMCMR_TEN | M821_SMCMR_REN; |
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456 | } |
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457 | } |
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458 | |
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459 | int |
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460 | m821_char_poll_read (int minor) |
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461 | { |
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462 | unsigned char c; |
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463 | rtems_unsigned32 level; |
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464 | |
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465 | _CPU_ISR_Disable(level); |
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466 | if (RxBd[minor]->status & M821_BD_EMPTY) { |
---|
467 | _CPU_ISR_Enable(level); |
---|
468 | return -1; |
---|
469 | } |
---|
470 | c = ((char *)RxBd[minor]->buffer)[0]; |
---|
471 | RxBd[minor]->status = M821_BD_EMPTY | M821_BD_WRAP; |
---|
472 | _CPU_ISR_Enable(level); |
---|
473 | return c; |
---|
474 | } |
---|
475 | |
---|
476 | int |
---|
477 | m821_char_poll_write (int minor, const char *buf, int len) |
---|
478 | { |
---|
479 | while (len--) { |
---|
480 | while (TxBd[minor]->status & M821_BD_READY) |
---|
481 | continue; |
---|
482 | txBuf[minor] = *buf++; |
---|
483 | TxBd[minor]->buffer = &txBuf[minor]; |
---|
484 | TxBd[minor]->length = 1; |
---|
485 | TxBd[minor]->status = M821_BD_READY | M821_BD_WRAP; |
---|
486 | } |
---|
487 | return 0; |
---|
488 | } |
---|
489 | |
---|
490 | /* |
---|
491 | * Interrupt handler |
---|
492 | */ |
---|
493 | rtems_isr |
---|
494 | m821_scc1_console_interrupt_handler (rtems_vector_number v) |
---|
495 | { |
---|
496 | /* |
---|
497 | * Buffer received? |
---|
498 | */ |
---|
499 | if ((m821.scc1.sccm & 0x1) && (m821.scc1.scce & 0x1)) { |
---|
500 | m821.scc1.scce = 0x1; |
---|
501 | /* m821.scc1.sccm &= ~0x1;*/ |
---|
502 | |
---|
503 | while ((RxBd[SCC1_MINOR]->status & M821_BD_EMPTY) == 0) { |
---|
504 | rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
505 | if (rxBufListTail[SCC1_MINOR]->next) { |
---|
506 | rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; |
---|
507 | rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; |
---|
508 | rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; |
---|
509 | rxBufListTail[SCC1_MINOR]->pos = 0; |
---|
510 | rxBufListTail[SCC1_MINOR]->next = 0; |
---|
511 | |
---|
512 | RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
513 | } |
---|
514 | RxBd[SCC1_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | |
---|
515 | M821_BD_INTERRUPT; |
---|
516 | } |
---|
517 | } |
---|
518 | |
---|
519 | /* |
---|
520 | * Buffer transmitted? |
---|
521 | */ |
---|
522 | #if 0 |
---|
523 | if (m821.smc1.smce & 0x2) { |
---|
524 | m821.smc1.smce = 0x2; |
---|
525 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
526 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
527 | } |
---|
528 | #endif |
---|
529 | m821.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ |
---|
530 | } |
---|
531 | |
---|
532 | rtems_isr |
---|
533 | m821_scc2_console_interrupt_handler (rtems_vector_number v) |
---|
534 | { |
---|
535 | /* |
---|
536 | * Buffer received? |
---|
537 | */ |
---|
538 | if ((m821.scc2.sccm & 0x1) && (m821.scc2.scce & 0x1)) { |
---|
539 | m821.scc2.scce = 0x1; |
---|
540 | /* m821.scc2.sccm &= ~0x1;*/ |
---|
541 | |
---|
542 | while ((RxBd[SCC2_MINOR]->status & M821_BD_EMPTY) == 0) { |
---|
543 | rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
544 | if (rxBufListTail[SCC2_MINOR]->next) { |
---|
545 | rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; |
---|
546 | rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; |
---|
547 | rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; |
---|
548 | rxBufListTail[SCC2_MINOR]->pos = 0; |
---|
549 | rxBufListTail[SCC2_MINOR]->next = 0; |
---|
550 | |
---|
551 | RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
552 | } |
---|
553 | RxBd[SCC2_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | |
---|
554 | M821_BD_INTERRUPT; |
---|
555 | } |
---|
556 | } |
---|
557 | |
---|
558 | /* |
---|
559 | * Buffer transmitted? |
---|
560 | */ |
---|
561 | #if 0 |
---|
562 | if (m821.smc1.smce & 0x2) { |
---|
563 | m821.smc1.smce = 0x2; |
---|
564 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
565 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
566 | } |
---|
567 | #endif |
---|
568 | m821.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ |
---|
569 | } |
---|
570 | |
---|
571 | rtems_isr |
---|
572 | m821_smc1_console_interrupt_handler (rtems_vector_number v) |
---|
573 | { |
---|
574 | /* |
---|
575 | * Buffer received? |
---|
576 | */ |
---|
577 | if (m821.smc1.smce & 0x1) { |
---|
578 | m821.smc1.smce = 0x1; |
---|
579 | /* m821.scc2.sccm &= ~0x1;*/ |
---|
580 | |
---|
581 | while ((RxBd[SMC1_MINOR]->status & M821_BD_EMPTY) == 0) { |
---|
582 | rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
583 | if (rxBufListTail[SMC1_MINOR]->next) { |
---|
584 | rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; |
---|
585 | rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; |
---|
586 | rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; |
---|
587 | rxBufListTail[SMC1_MINOR]->pos = 0; |
---|
588 | rxBufListTail[SMC1_MINOR]->next = 0; |
---|
589 | |
---|
590 | RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
591 | } |
---|
592 | RxBd[SMC1_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | |
---|
593 | M821_BD_INTERRUPT; |
---|
594 | } |
---|
595 | } |
---|
596 | |
---|
597 | /* |
---|
598 | * Buffer transmitted? |
---|
599 | */ |
---|
600 | #if 0 |
---|
601 | if (m821.smc1.smce & 0x2) { |
---|
602 | m821.smc1.smce = 0x2; |
---|
603 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
604 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
605 | } |
---|
606 | #endif |
---|
607 | m821.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ |
---|
608 | } |
---|
609 | |
---|
610 | rtems_isr |
---|
611 | m821_smc2_console_interrupt_handler (rtems_vector_number v) |
---|
612 | { |
---|
613 | /* |
---|
614 | * Buffer received? |
---|
615 | */ |
---|
616 | if (m821.smc2.smce & 0x1) { |
---|
617 | m821.smc2.smce = 0x1; |
---|
618 | |
---|
619 | while ((RxBd[SMC2_MINOR]->status & M821_BD_EMPTY) == 0) { |
---|
620 | rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); |
---|
621 | if (rxBufListTail[SMC2_MINOR]->next) { |
---|
622 | rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; |
---|
623 | rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; |
---|
624 | rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; |
---|
625 | rxBufListTail[SMC2_MINOR]->pos = 0; |
---|
626 | rxBufListTail[SMC2_MINOR]->next = 0; |
---|
627 | |
---|
628 | RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); |
---|
629 | } |
---|
630 | RxBd[SMC2_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | |
---|
631 | M821_BD_INTERRUPT; |
---|
632 | } |
---|
633 | } |
---|
634 | |
---|
635 | /* |
---|
636 | * Buffer transmitted? |
---|
637 | */ |
---|
638 | #if 0 |
---|
639 | if (m821.smc1.smce & 0x2) { |
---|
640 | m821.smc1.smce = 0x2; |
---|
641 | if ((smcTxBd->status & M360_BD_READY) == 0) |
---|
642 | rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); |
---|
643 | } |
---|
644 | #endif |
---|
645 | m821.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ |
---|
646 | } |
---|
647 | |
---|
648 | |
---|
649 | int |
---|
650 | m821_buf_poll_read (int minor, char **buf) |
---|
651 | { |
---|
652 | int len; |
---|
653 | |
---|
654 | if (RxBd[minor]->status & M821_BD_EMPTY) |
---|
655 | return -1; |
---|
656 | |
---|
657 | RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ |
---|
658 | len = RxBd[minor]->length; |
---|
659 | RxBd[minor]->status = M821_BD_EMPTY | M821_BD_WRAP; |
---|
660 | |
---|
661 | return len; |
---|
662 | } |
---|
663 | |
---|
664 | int |
---|
665 | m821_buf_poll_write (int minor, char *buf, int len) |
---|
666 | { |
---|
667 | static char *last_buf[6]; |
---|
668 | |
---|
669 | while (TxBd[minor]->status & M821_BD_READY) |
---|
670 | continue; |
---|
671 | if (last_buf[minor]) |
---|
672 | free(last_buf[minor]); |
---|
673 | last_buf[minor] = buf; |
---|
674 | TxBd[minor]->buffer = buf; |
---|
675 | TxBd[minor]->length = len; |
---|
676 | TxBd[minor]->status = M821_BD_READY | M821_BD_WRAP; |
---|
677 | return 0; |
---|
678 | } |
---|
679 | |
---|
680 | /* |
---|
681 | * This is needed in case we use TERMIOS |
---|
682 | */ |
---|
683 | void m821_console_reserve_resources(rtems_configuration_table *configuration) |
---|
684 | { |
---|
685 | rtems_termios_reserve_resources (configuration, 1); |
---|
686 | } |
---|
687 | |
---|
688 | void m821_console_initialize(void) |
---|
689 | { |
---|
690 | int i; |
---|
691 | |
---|
692 | for (i=0; i < NIFACES; i++) { |
---|
693 | rxBufList[i] = malloc(sizeof(Buf_t)); |
---|
694 | rxBufListTail[i] = rxBufList[i]; |
---|
695 | rxBufList[i]->buf = 0; |
---|
696 | rxBufList[i]->len = 0; |
---|
697 | rxBufList[i]->pos = 0; |
---|
698 | rxBufList[i]->next = 0; |
---|
699 | } |
---|
700 | } |
---|
701 | |
---|
702 | rtems_device_driver m821_console_read(rtems_device_major_number major, |
---|
703 | rtems_device_minor_number minor, |
---|
704 | void *arg) |
---|
705 | { |
---|
706 | rtems_libio_rw_args_t *rw_args; |
---|
707 | char *buffer; |
---|
708 | int maximum; |
---|
709 | int count; |
---|
710 | Buf_t *tmp_buf; |
---|
711 | rtems_unsigned32 level; |
---|
712 | |
---|
713 | /* |
---|
714 | * Set up interrupts |
---|
715 | * FIXME: DANGER: WARNING: |
---|
716 | * CICR and SIMASK must be set in any module that uses |
---|
717 | * the CPM. Currently those are console-generic.c and |
---|
718 | * network.c. If the registers are not set the same |
---|
719 | * in both places, strange things may happen. |
---|
720 | * If they are only set in one place, then an application |
---|
721 | * that used the other module won't work correctly. |
---|
722 | * Put this comment in each module that sets these 2 registers |
---|
723 | */ |
---|
724 | m821.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
725 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
726 | m821.simask |= M821_SIMASK_LVM1; |
---|
727 | |
---|
728 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
729 | buffer = rw_args->buffer; |
---|
730 | maximum = rw_args->count; |
---|
731 | count = 0; |
---|
732 | |
---|
733 | while (count == 0) { |
---|
734 | if (rxBufList[minor]->len) { |
---|
735 | while ((count < maximum) && |
---|
736 | (rxBufList[minor]->pos < rxBufList[minor]->len)) { |
---|
737 | buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; |
---|
738 | } |
---|
739 | _CPU_ISR_Disable(level); |
---|
740 | if (rxBufList[minor]->pos == rxBufList[minor]->len) { |
---|
741 | if (rxBufList[minor]->next) { |
---|
742 | tmp_buf=rxBufList[minor]->next; |
---|
743 | free (rxBufList[minor]->buf); |
---|
744 | free (rxBufList[minor]); |
---|
745 | rxBufList[minor]=tmp_buf; |
---|
746 | } |
---|
747 | else { |
---|
748 | free(rxBufList[minor]->buf); |
---|
749 | rxBufList[minor]->buf=0; |
---|
750 | rxBufList[minor]->len=0; |
---|
751 | rxBufList[minor]->pos=0; |
---|
752 | } |
---|
753 | } |
---|
754 | _CPU_ISR_Enable(level); |
---|
755 | } |
---|
756 | else |
---|
757 | if(rxBufList[minor]->next && !rxBufList[minor]->len) { |
---|
758 | tmp_buf = rxBufList[minor]; |
---|
759 | rxBufList[minor] = rxBufList[minor]->next; |
---|
760 | free(tmp_buf); |
---|
761 | } |
---|
762 | /* sleep(1);*/ |
---|
763 | } |
---|
764 | rw_args->bytes_moved = count; |
---|
765 | return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; |
---|
766 | } |
---|
767 | |
---|
768 | rtems_device_driver m821_console_write(rtems_device_major_number major, |
---|
769 | rtems_device_minor_number minor, |
---|
770 | void *arg) |
---|
771 | { |
---|
772 | int count; |
---|
773 | int maximum; |
---|
774 | rtems_libio_rw_args_t *rw_args; |
---|
775 | char *in_buffer; |
---|
776 | char *out_buffer; |
---|
777 | int n; |
---|
778 | |
---|
779 | /* |
---|
780 | * Set up interrupts |
---|
781 | * FIXME: DANGER: WARNING: |
---|
782 | * CICR and SIMASK must be set in any module that uses |
---|
783 | * the CPM. Currently those are console-generic.c and |
---|
784 | * network.c. If the registers are not set the same |
---|
785 | * in both places, strange things may happen. |
---|
786 | * If they are only set in one place, then an application |
---|
787 | * that used the other module won't work correctly. |
---|
788 | * Put this comment in each module that sets these 2 registers |
---|
789 | */ |
---|
790 | /* m821.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, |
---|
791 | SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ |
---|
792 | /* m821.simask |= M821_SIMASK_LVM1; */ |
---|
793 | |
---|
794 | rw_args = (rtems_libio_rw_args_t *) arg; |
---|
795 | |
---|
796 | in_buffer = rw_args->buffer; |
---|
797 | maximum = rw_args->count; |
---|
798 | |
---|
799 | out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ |
---|
800 | /* be too small */ |
---|
801 | |
---|
802 | if (!out_buffer) { |
---|
803 | rw_args->bytes_moved = 0; |
---|
804 | return RTEMS_NO_MEMORY; |
---|
805 | } |
---|
806 | n=0; |
---|
807 | for (count = 0; count < maximum; count++) { |
---|
808 | if ( in_buffer[ count ] == '\n') { |
---|
809 | out_buffer[count + n] = '\r'; |
---|
810 | n++; |
---|
811 | } |
---|
812 | out_buffer[count + n] = in_buffer[count]; |
---|
813 | } |
---|
814 | m821_buf_poll_write(minor, out_buffer, maximum+n); |
---|
815 | rw_args->bytes_moved = maximum; |
---|
816 | return RTEMS_SUCCESSFUL; |
---|
817 | } |
---|
818 | |
---|
819 | |
---|
820 | /* |
---|
821 | * How to use the console. |
---|
822 | * In your BSP, have the following functions: |
---|
823 | * |
---|
824 | * rtems_device_driver console_initialize(rtems_device_major_number major, |
---|
825 | * rtems_device_minor_number minor, |
---|
826 | * void *arg) |
---|
827 | * rtems_device_driver console_open(rtems_device_major_number major, |
---|
828 | * rtems_device_minor_number minor, |
---|
829 | * void *arg) |
---|
830 | * rtems_device_driver console_close(rtems_device_major_number major, |
---|
831 | * rtems_device_minor_number minor, |
---|
832 | * void *arg) |
---|
833 | * rtems_device_driver console_read(rtems_device_major_number major, |
---|
834 | * rtems_device_minor_number minor, |
---|
835 | * void *arg) |
---|
836 | * rtems_device_driver console_write(rtems_device_major_number major, |
---|
837 | * rtems_device_minor_number minor, |
---|
838 | * void *arg) |
---|
839 | * rtems_device_driver console_control(rtems_device_major_number major, |
---|
840 | * rtems_device_minor_number minor, |
---|
841 | * void *arg) |
---|
842 | * |
---|
843 | */ |
---|