source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h @ d3d9ef37

4.104.114.84.95
Last change on this file since d3d9ef37 was a859df85, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/13/05 at 05:00:15

New header guards.

  • Property mode set to 100644
File size: 5.4 KB
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1#ifndef _LIBCPU_PTE121_H
2#define _LIBCPU_PTE121_H
3/* $Id$ */
4
5/* Rudimentary page/hash table support for Powerpc
6 *
7 * A simple, static (i.e. no 'per-process' virtual
8 * address space etc.) page table providing
9 * one-to-one effective <-> virtual <-> physical
10 * address mapping.
11 *
12 * PURPOSE:
13 *    1) allow write-protection of text/read-only data areas
14 *    2) provide more effective-address space in case
15 *       the BATs are not enough
16 * LIMITATIONS:
17 *    -  once activated, the page table cannot be changed
18 *    -  no PTE replacement (makes no sense in a real-time
19 *       environment, anyway) -> the page table just MUST
20 *       be big enough!.
21 *    -  only one page table supported.
22 */
23
24/* Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 */
25
26/* Abstract handle for a page table */
27typedef struct Triv121PgTblRec_ *Triv121PgTbl;
28
29/* Initialize a trivial page table
30 * using 2^ldSize bytes of memory starting at
31 * 'base'.
32 *
33 * RETURNS: a handle to the internal data structure
34 *          used to manage the page table. NULL on
35 *          error.
36 *         
37 * NOTES:   - 'base' must be aligned to the size
38 *          - minimal ldSize is 16 (== 64k)
39 *          - this routine maps the page table itself
40 *            with read-only access. While this prevents
41 *            the CPU from overwriting the page table,
42 *            it can still be corrupted by PCI bus masters
43 *            (like DMA engines, [VME] bridges etc.) and
44 *                        even by this CPU if either the MMU is off
45 *                        or if there is a DBAT mapping granting write
46 *            access...
47 */
48Triv121PgTbl
49triv121PgTblInit(unsigned long base, unsigned ldSize);
50
51/* get the log2 of the minimal page table size needed
52 * for mapping 'size' bytes.
53 *
54 * EXAMPLE: create a page table which maps the entire
55 *          physical memory. The page table itself shall
56 *          be allocated at the top of the available
57 *          memory (assuming 'memsize' is a power of two):
58 *
59 *      ldSize = triv121PgTblLdMinSize(memsize);
60 *  memsize -= (1<<ldSize);     / * reduce memory available to RTEMS * /
61 *  pgTbl  = triv121PgTblInit(memsize,ldSize);
62 *
63 */
64unsigned long
65triv121PgTblLdMinSize(unsigned long size);
66
67/* Map an address range 1:1 in pgTbl with the given protection;
68 *
69 * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index
70 *          for which no PTE could be allocated, on failure.
71 *
72 * NOTES:   - This routine returns MINUS ONE ON SUCCESS
73 *          - (parts) of a mapping which overlap with
74 *            already existing PTEs are silently ignored.
75 *
76 *            Therefore, you can e.g. first create
77 *            a couple of write protected maps and
78 *            finally map the entire memory r/w. This
79 *            will leave the write protected maps
80 *            intact.
81 */
82long
83triv121PgTblMap(
84                                Triv121PgTbl  pgTbl,                    /* handle, returned by Init or Get */
85
86                                long          vsid,                             /* vsid for this mapping (contains topmost 4 bits of EA);
87                                                                                                 *
88                                                                                                 * NOTE: it is allowed to pass a VSID < 0 to tell this
89                                                                                                 *       routine it should use a VSID corresponding to a
90                                                                                                 *       1:1:1  effective - virtual - physical  mapping
91                                                                                                 */
92
93                                unsigned long start,                    /* segment offset (lowermost 28 bits of EA) of address range
94                                                                                                 *
95                                                                                                 * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
96                                                                                                 *       preted as an effective address (EA), i.e. all 32
97                                                                                                 *       bits are used - the most significant four going into
98                                                                                                 *       to the VSID...
99                                                                                                 */
100
101                                unsigned long numPages,                 /* number of pages to map */
102
103                                unsigned wimgAttr,                              /* 'wimg' attributes
104                                                                                                 * (Write thru, cache Inhibit, coherent Memory,
105                                                                                                 *  Guarded memory)
106                                                                                                 */
107
108                                unsigned protection                             /* 'pp' access protection: Super      User
109                                                                                                 *
110                                                                                                 *   0                      r/w       none
111                                                                                                 *   1                      r/w       ro   
112                                                                                                 *   2                      r/w       r/w
113                                                                                                 *   3                      ro        ro
114                                                                                                 */
115                                );
116
117#define TRIV121_ATTR_W  8       
118#define TRIV121_ATTR_I  4
119#define TRIV121_ATTR_M  2
120#define TRIV121_ATTR_G  1
121
122/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
123 * and guarded pages. RTM about the 'eieio' instruction!
124 */
125#define TRIV121_ATTR_IO_PAGE    (TRIV121_ATTR_I|TRIV121_ATTR_G)
126
127#define TRIV121_PP_RO_PAGE              (3)  /* read-only for everyone */
128#define TRIV121_PP_RW_PAGE              (2)  /* read-write for everyone */
129
130#define TRIV121_121_VSID                (-1) /* use 1:1 effective<->virtual address mapping */
131
132#define TRIV121_MAP_SUCCESS             (-1) /* triv121PgTblMap() returns this on SUCCESS */
133
134/* get a handle to the one and only page table
135 * (must have been initialized/allocated)
136 *
137 * RETURNS: NULL if the page table has not been initialized/allocated.
138 */
139Triv121PgTbl
140triv121PgTblGet(void);
141
142/*
143 * compute the SDR1 register value for the page table
144 */
145
146unsigned long
147triv121PgTblSDR1(Triv121PgTbl pgTbl);
148
149/*
150 * Activate the page table:
151 *      - set up the segment registers for a 1:1 effective <-> virtual address mapping,
152 *    give user and supervisor keys.
153 *  - set up the SDR1 register
154 *  - flush all tlbs
155 *  - 'lock' pgTbl, i.e. prevent all further modifications.
156 *
157 * NOTE: This routine does not change any BATs. Since these
158 *       have priority over the page table, the user
159 *       may have to switch overlapping BATs OFF in order
160 *       for the page table mappings to take effect.
161 */
162void
163triv121PgTblActivate(Triv121PgTbl pgTbl);
164
165#endif
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