1 | #ifndef _LIBCPU_PTE121_H |
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2 | #define _LIBCPU_PTE121_H |
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3 | /* $Id$ */ |
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4 | |
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5 | /* Rudimentary page/hash table support for Powerpc |
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6 | * |
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7 | * A simple, static (i.e. no 'per-process' virtual |
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8 | * address space etc.) page table providing |
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9 | * one-to-one effective <-> virtual <-> physical |
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10 | * address mapping. |
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11 | * |
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12 | * PURPOSE: |
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13 | * 1) allow write-protection of text/read-only data areas |
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14 | * 2) provide more effective-address space in case |
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15 | * the BATs are not enough |
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16 | * LIMITATIONS: |
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17 | * - once activated, the page table cannot be changed |
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18 | * - no PTE replacement (makes no sense in a real-time |
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19 | * environment, anyway) -> the page table just MUST |
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20 | * be big enough!. |
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21 | * - only one page table supported. |
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22 | */ |
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23 | |
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24 | /* Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 */ |
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25 | |
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26 | /* Abstract handle for a page table */ |
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27 | typedef struct Triv121PgTblRec_ *Triv121PgTbl; |
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28 | |
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29 | /* Initialize a trivial page table |
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30 | * using 2^ldSize bytes of memory starting at |
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31 | * 'base'. |
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32 | * |
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33 | * RETURNS: a handle to the internal data structure |
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34 | * used to manage the page table. NULL on |
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35 | * error. |
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36 | * |
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37 | * NOTES: - 'base' must be aligned to the size |
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38 | * - minimal ldSize is 16 (== 64k) |
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39 | * - this routine maps the page table itself |
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40 | * with read-only access. While this prevents |
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41 | * the CPU from overwriting the page table, |
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42 | * it can still be corrupted by PCI bus masters |
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43 | * (like DMA engines, [VME] bridges etc.) and |
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44 | * even by this CPU if either the MMU is off |
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45 | * or if there is a DBAT mapping granting write |
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46 | * access... |
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47 | */ |
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48 | Triv121PgTbl |
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49 | triv121PgTblInit(unsigned long base, unsigned ldSize); |
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50 | |
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51 | /* get the log2 of the minimal page table size needed |
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52 | * for mapping 'size' bytes. |
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53 | * |
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54 | * EXAMPLE: create a page table which maps the entire |
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55 | * physical memory. The page table itself shall |
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56 | * be allocated at the top of the available |
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57 | * memory (assuming 'memsize' is a power of two): |
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58 | * |
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59 | * ldSize = triv121PgTblLdMinSize(memsize); |
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60 | * memsize -= (1<<ldSize); / * reduce memory available to RTEMS * / |
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61 | * pgTbl = triv121PgTblInit(memsize,ldSize); |
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62 | * |
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63 | */ |
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64 | unsigned long |
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65 | triv121PgTblLdMinSize(unsigned long size); |
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66 | |
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67 | /* Map an address range 1:1 in pgTbl with the given protection; |
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68 | * |
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69 | * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index |
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70 | * for which no PTE could be allocated, on failure. |
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71 | * |
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72 | * NOTES: - This routine returns MINUS ONE ON SUCCESS |
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73 | * - (parts) of a mapping which overlap with |
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74 | * already existing PTEs are silently ignored. |
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75 | * |
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76 | * Therefore, you can e.g. first create |
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77 | * a couple of write protected maps and |
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78 | * finally map the entire memory r/w. This |
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79 | * will leave the write protected maps |
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80 | * intact. |
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81 | */ |
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82 | long |
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83 | triv121PgTblMap( |
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84 | Triv121PgTbl pgTbl, /* handle, returned by Init or Get */ |
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85 | |
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86 | long vsid, /* vsid for this mapping (contains topmost 4 bits of EA); |
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87 | * |
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88 | * NOTE: it is allowed to pass a VSID < 0 to tell this |
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89 | * routine it should use a VSID corresponding to a |
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90 | * 1:1:1 effective - virtual - physical mapping |
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91 | */ |
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92 | |
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93 | unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range |
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94 | * |
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95 | * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter- |
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96 | * preted as an effective address (EA), i.e. all 32 |
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97 | * bits are used - the most significant four going into |
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98 | * to the VSID... |
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99 | */ |
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100 | |
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101 | unsigned long numPages, /* number of pages to map */ |
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102 | |
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103 | unsigned wimgAttr, /* 'wimg' attributes |
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104 | * (Write thru, cache Inhibit, coherent Memory, |
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105 | * Guarded memory) |
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106 | */ |
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107 | |
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108 | unsigned protection /* 'pp' access protection: Super User |
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109 | * |
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110 | * 0 r/w none |
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111 | * 1 r/w ro |
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112 | * 2 r/w r/w |
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113 | * 3 ro ro |
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114 | */ |
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115 | ); |
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116 | |
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117 | #define TRIV121_ATTR_W 8 |
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118 | #define TRIV121_ATTR_I 4 |
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119 | #define TRIV121_ATTR_M 2 |
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120 | #define TRIV121_ATTR_G 1 |
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121 | |
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122 | /* for I/O pages (e.g. PCI, VME addresses) use cache inhibited |
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123 | * and guarded pages. RTM about the 'eieio' instruction! |
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124 | */ |
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125 | #define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G) |
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126 | |
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127 | #define TRIV121_PP_RO_PAGE (3) /* read-only for everyone */ |
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128 | #define TRIV121_PP_RW_PAGE (2) /* read-write for everyone */ |
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129 | |
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130 | #define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */ |
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131 | |
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132 | #define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */ |
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133 | |
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134 | /* get a handle to the one and only page table |
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135 | * (must have been initialized/allocated) |
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136 | * |
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137 | * RETURNS: NULL if the page table has not been initialized/allocated. |
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138 | */ |
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139 | Triv121PgTbl |
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140 | triv121PgTblGet(void); |
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141 | |
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142 | /* |
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143 | * compute the SDR1 register value for the page table |
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144 | */ |
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145 | |
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146 | unsigned long |
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147 | triv121PgTblSDR1(Triv121PgTbl pgTbl); |
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148 | |
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149 | /* |
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150 | * Activate the page table: |
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151 | * - set up the segment registers for a 1:1 effective <-> virtual address mapping, |
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152 | * give user and supervisor keys. |
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153 | * - set up the SDR1 register |
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154 | * - flush all tlbs |
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155 | * - 'lock' pgTbl, i.e. prevent all further modifications. |
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156 | * |
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157 | * NOTE: This routine does not change any BATs. Since these |
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158 | * have priority over the page table, the user |
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159 | * may have to switch overlapping BATs OFF in order |
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160 | * for the page table mappings to take effect. |
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161 | */ |
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162 | void |
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163 | triv121PgTblActivate(Triv121PgTbl pgTbl); |
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164 | |
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165 | #endif |
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