1 | #ifndef _LIBCPU_PTE121_H |
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2 | #define _LIBCPU_PTE121_H |
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3 | |
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4 | /* |
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5 | * Authorship |
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6 | * ---------- |
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7 | * This software was created by |
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8 | * Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004, |
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9 | * Stanford Linear Accelerator Center, Stanford University. |
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10 | * |
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11 | * Acknowledgement of sponsorship |
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12 | * ------------------------------ |
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13 | * This software was produced by |
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14 | * the Stanford Linear Accelerator Center, Stanford University, |
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15 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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16 | * |
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17 | * Government disclaimer of liability |
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18 | * ---------------------------------- |
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19 | * Neither the United States nor the United States Department of Energy, |
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20 | * nor any of their employees, makes any warranty, express or implied, or |
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21 | * assumes any legal liability or responsibility for the accuracy, |
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22 | * completeness, or usefulness of any data, apparatus, product, or process |
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23 | * disclosed, or represents that its use would not infringe privately owned |
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24 | * rights. |
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25 | * |
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26 | * Stanford disclaimer of liability |
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27 | * -------------------------------- |
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28 | * Stanford University makes no representations or warranties, express or |
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29 | * implied, nor assumes any liability for the use of this software. |
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30 | * |
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31 | * Stanford disclaimer of copyright |
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32 | * -------------------------------- |
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33 | * Stanford University, owner of the copyright, hereby disclaims its |
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34 | * copyright and all other rights in this software. Hence, anyone may |
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35 | * freely use it for any purpose without restriction. |
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36 | * |
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37 | * Maintenance of notices |
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38 | * ---------------------- |
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39 | * In the interest of clarity regarding the origin and status of this |
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40 | * SLAC software, this and all the preceding Stanford University notices |
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41 | * are to remain affixed to any copy or derivative of this software made |
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42 | * or distributed by the recipient and are to be affixed to any copy of |
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43 | * software made or distributed by the recipient that contains a copy or |
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44 | * derivative of this software. |
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45 | * |
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46 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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47 | */ |
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48 | |
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49 | /* Rudimentary page/hash table support for Powerpc |
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50 | * |
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51 | * A simple, static (i.e. no 'per-process' virtual |
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52 | * address space etc.) page table providing |
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53 | * one-to-one effective <-> virtual <-> physical |
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54 | * address mapping. |
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55 | * |
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56 | * PURPOSE: |
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57 | * 1) allow write-protection of text/read-only data areas |
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58 | * 2) provide more effective-address space in case |
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59 | * the BATs are not enough |
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60 | * 3) allow 'alias' mappings. Such aliases can only use |
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61 | * the upper bits of the VSID since VSID & 0xf and the |
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62 | * PI are always mapped 1:1 to the RPN. |
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63 | * LIMITATIONS: |
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64 | * - no PTE replacement (makes no sense in a real-time |
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65 | * environment, anyway) -> the page table just MUST |
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66 | * be big enough!. |
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67 | * - only one page table supported. |
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68 | * - no locking implemented. If multiple threads modify |
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69 | * the page table, it is the user's responsibility to |
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70 | * implement exclusive access. |
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71 | */ |
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72 | |
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73 | |
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74 | /* I don't include mmu.h here because it says it's derived from linux |
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75 | * and I want to avoid licensing problems |
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76 | */ |
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77 | |
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78 | /* Abstract handle for a page table */ |
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79 | typedef struct Triv121PgTblRec_ *Triv121PgTbl; |
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80 | |
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81 | /* A PTE entry */ |
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82 | typedef struct PTERec_ { |
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83 | volatile unsigned long v:1, vsid:24, h:1, api: 6; |
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84 | volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2; |
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85 | } PTERec, *APte; |
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86 | |
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87 | /* Initialize a trivial page table |
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88 | * using 2^ldSize bytes of memory starting at |
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89 | * 'base'. |
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90 | * |
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91 | * RETURNS: a handle to the internal data structure |
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92 | * used to manage the page table. NULL on |
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93 | * error. |
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94 | * |
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95 | * NOTES: - 'base' must be aligned to the size |
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96 | * - minimal ldSize is 16 (== 64k) |
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97 | * - this routine maps the page table itself |
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98 | * with read-only access. While this prevents |
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99 | * the CPU from overwriting the page table, |
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100 | * it can still be corrupted by PCI bus masters |
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101 | * (like DMA engines, [VME] bridges etc.) and |
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102 | * even by this CPU if either the MMU is off |
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103 | * or if there is a DBAT mapping granting write |
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104 | * access... |
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105 | */ |
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106 | Triv121PgTbl |
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107 | triv121PgTblInit(unsigned long base, unsigned ldSize); |
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108 | |
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109 | /* get the log2 of the minimal page table size needed |
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110 | * for mapping 'size' bytes. |
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111 | * |
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112 | * EXAMPLE: create a page table which maps the entire |
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113 | * physical memory. The page table itself shall |
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114 | * be allocated at the top of the available |
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115 | * memory (assuming 'memsize' is a power of two): |
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116 | * |
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117 | * ldSize = triv121PgTblLdMinSize(memsize); |
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118 | * memsize -= (1<<ldSize); / * reduce memory available to RTEMS * / |
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119 | * pgTbl = triv121PgTblInit(memsize,ldSize); |
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120 | * |
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121 | */ |
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122 | unsigned long |
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123 | triv121PgTblLdMinSize(unsigned long size); |
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124 | |
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125 | /* Map an address range 1:1 in pgTbl with the given protection; |
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126 | * |
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127 | * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index |
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128 | * for which no PTE could be allocated, on failure. |
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129 | * |
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130 | * NOTES: - This routine returns MINUS ONE ON SUCCESS |
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131 | * - (parts) of a mapping which overlap with |
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132 | * already existing PTEs are silently ignored. |
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133 | * |
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134 | * Therefore, you can e.g. first create |
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135 | * a couple of write protected maps and |
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136 | * finally map the entire memory r/w. This |
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137 | * will leave the write protected maps |
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138 | * intact. |
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139 | */ |
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140 | long |
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141 | triv121PgTblMap( |
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142 | Triv121PgTbl pgTbl, /* handle, returned by Init or Get */ |
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143 | |
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144 | long vsid, /* vsid for this mapping (contains topmost 4 bits of EA); |
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145 | * |
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146 | * NOTE: it is allowed to pass a VSID < 0 to tell this |
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147 | * routine it should use a VSID corresponding to a |
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148 | * 1:1:1 effective - virtual - physical mapping |
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149 | */ |
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150 | |
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151 | unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range |
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152 | * |
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153 | * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter- |
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154 | * preted as an effective address (EA), i.e. all 32 |
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155 | * bits are used - the most significant four going into |
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156 | * to the VSID... |
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157 | */ |
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158 | |
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159 | unsigned long numPages, /* number of pages to map */ |
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160 | |
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161 | unsigned wimgAttr, /* 'wimg' attributes |
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162 | * (Write thru, cache Inhibit, coherent Memory, |
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163 | * Guarded memory) |
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164 | */ |
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165 | |
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166 | unsigned protection /* 'pp' access protection: Super User |
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167 | * |
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168 | * 0 r/w none |
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169 | * 1 r/w ro |
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170 | * 2 r/w r/w |
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171 | * 3 ro ro |
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172 | */ |
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173 | ); |
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174 | |
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175 | #define TRIV121_ATTR_W 8 |
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176 | #define TRIV121_ATTR_I 4 |
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177 | #define TRIV121_ATTR_M 2 |
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178 | #define TRIV121_ATTR_G 1 |
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179 | |
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180 | /* for I/O pages (e.g. PCI, VME addresses) use cache inhibited |
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181 | * and guarded pages. RTM about the 'eieio' instruction! |
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182 | */ |
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183 | #define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G) |
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184 | |
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185 | #define TRIV121_PP_RO_PAGE (1) /* read-only for key = 1, unlocked by key=0 */ |
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186 | #define TRIV121_PP_RW_PAGE (2) /* read-write for key = 1/0 */ |
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187 | |
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188 | #define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */ |
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189 | #define TRIV121_SEG_VSID (-2) /* lookup VSID in the segment register */ |
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190 | |
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191 | #define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */ |
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192 | |
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193 | /* get a handle to the one and only page table |
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194 | * (must have been initialized/allocated) |
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195 | * |
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196 | * RETURNS: NULL if the page table has not been initialized/allocated. |
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197 | */ |
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198 | Triv121PgTbl |
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199 | triv121PgTblGet(void); |
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200 | |
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201 | /* |
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202 | * compute the SDR1 register value for the page table |
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203 | */ |
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204 | |
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205 | unsigned long |
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206 | triv121PgTblSDR1(Triv121PgTbl pgTbl); |
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207 | |
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208 | /* |
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209 | * Activate the page table: |
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210 | * - set up the segment registers for a 1:1 effective <-> virtual address mapping, |
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211 | * give user and supervisor keys. |
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212 | * - set up the SDR1 register |
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213 | * - flush all tlbs |
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214 | * - 'lock' pgTbl, i.e. prevent all further modifications. |
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215 | * |
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216 | * NOTE: This routine does not change any BATs. Since these |
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217 | * have priority over the page table, the user |
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218 | * may have to switch overlapping BATs OFF in order |
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219 | * for the page table mappings to take effect. |
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220 | */ |
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221 | void triv121PgTblActivate(Triv121PgTbl pgTbl); |
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222 | |
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223 | /* Find the PTE for a EA and print its contents to stdout |
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224 | * RETURNS: pte for EA or NULL if no entry was found. |
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225 | */ |
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226 | APte triv121DumpEa(unsigned long ea); |
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227 | |
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228 | /* Find and return a PTE for a vsid/pi combination |
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229 | * RETURNS: pte or NULL if no entry was found |
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230 | */ |
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231 | APte triv121FindPte(unsigned long vsid, unsigned long pi); |
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232 | |
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233 | /* |
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234 | * Unmap an effective address |
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235 | * |
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236 | * RETURNS: pte that mapped the ea or NULL if no |
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237 | * mapping existed. |
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238 | */ |
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239 | APte triv121UnmapEa(unsigned long ea); |
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240 | |
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241 | /* |
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242 | * Change the WIMG and PP attributes of the page containing 'ea' |
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243 | * |
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244 | * NOTES: The 'wimg' and 'pp' may be <0 to indicate that no |
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245 | * change is desired. |
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246 | * |
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247 | * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped. |
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248 | */ |
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249 | APte triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp); |
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250 | |
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251 | /* Make the whole page table writable |
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252 | * NOTES: If the page table has not been initialized yet, |
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253 | * this routine has no effect (i.e., after |
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254 | * initialization the page table will still be read-only). |
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255 | */ |
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256 | void triv121MakePgTblRW(void); |
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257 | |
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258 | /* Make the whole page table read-only |
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259 | */ |
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260 | void triv121MakePgTblRO(void); |
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261 | |
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262 | /* Dump a pte to stdout */ |
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263 | long triv121DumpPte(APte pte); |
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264 | |
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265 | #endif |
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