source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h @ 531aa81

4.104.114.84.9
Last change on this file since 531aa81 was 531aa81, checked in by Till Straumann <strauman@…>, on Jan 17, 2007 at 5:57:29 AM

2007-01-16 Till Straumann <strauman@…>

  • mpc6xx/mmu/pte121.h, mpc6xx/mmu/pte121.c: Added SLAC/Stanford Authorship Note / Copyright + Liability Disclaimer.
  • Property mode set to 100644
File size: 9.4 KB
Line 
1#ifndef _LIBCPU_PTE121_H
2#define _LIBCPU_PTE121_H
3/* $Id$ */
4
5/*
6 * Authorship
7 * ----------
8 * This software was created by
9 *     Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004,
10 *         Stanford Linear Accelerator Center, Stanford University.
11 *
12 * Acknowledgement of sponsorship
13 * ------------------------------
14 * This software was produced by
15 *     the Stanford Linear Accelerator Center, Stanford University,
16 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
17 *
18 * Government disclaimer of liability
19 * ----------------------------------
20 * Neither the United States nor the United States Department of Energy,
21 * nor any of their employees, makes any warranty, express or implied, or
22 * assumes any legal liability or responsibility for the accuracy,
23 * completeness, or usefulness of any data, apparatus, product, or process
24 * disclosed, or represents that its use would not infringe privately owned
25 * rights.
26 *
27 * Stanford disclaimer of liability
28 * --------------------------------
29 * Stanford University makes no representations or warranties, express or
30 * implied, nor assumes any liability for the use of this software.
31 *
32 * Stanford disclaimer of copyright
33 * --------------------------------
34 * Stanford University, owner of the copyright, hereby disclaims its
35 * copyright and all other rights in this software.  Hence, anyone may
36 * freely use it for any purpose without restriction. 
37 *
38 * Maintenance of notices
39 * ----------------------
40 * In the interest of clarity regarding the origin and status of this
41 * SLAC software, this and all the preceding Stanford University notices
42 * are to remain affixed to any copy or derivative of this software made
43 * or distributed by the recipient and are to be affixed to any copy of
44 * software made or distributed by the recipient that contains a copy or
45 * derivative of this software.
46 *
47 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
48 */ 
49
50/* Rudimentary page/hash table support for Powerpc
51 *
52 * A simple, static (i.e. no 'per-process' virtual
53 * address space etc.) page table providing
54 * one-to-one effective <-> virtual <-> physical
55 * address mapping.
56 *
57 * PURPOSE:
58 *    1) allow write-protection of text/read-only data areas
59 *    2) provide more effective-address space in case
60 *       the BATs are not enough
61 *    3) allow 'alias' mappings. Such aliases can only use
62 *       the upper bits of the VSID since VSID & 0xf and the
63 *       PI are always mapped 1:1 to the RPN.
64 * LIMITATIONS:
65 *    -  no PTE replacement (makes no sense in a real-time
66 *       environment, anyway) -> the page table just MUST
67 *       be big enough!.
68 *    -  only one page table supported.
69 *    -  no locking implemented. If multiple threads modify
70 *       the page table, it is the user's responsibility to
71 *       implement exclusive access.
72 */
73
74
75/* I don't include mmu.h here because it says it's derived from linux
76 * and I want to avoid licensing problems
77 */
78
79/* Abstract handle for a page table */
80typedef struct Triv121PgTblRec_ *Triv121PgTbl;
81
82/* A PTE entry */
83typedef struct PTERec_ {
84  volatile unsigned long v:1,    vsid:24, h:1, api: 6;
85  volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2;
86} PTERec, *APte;
87
88/* Initialize a trivial page table
89 * using 2^ldSize bytes of memory starting at
90 * 'base'.
91 *
92 * RETURNS: a handle to the internal data structure
93 *          used to manage the page table. NULL on
94 *          error.
95 *         
96 * NOTES:   - 'base' must be aligned to the size
97 *          - minimal ldSize is 16 (== 64k)
98 *          - this routine maps the page table itself
99 *            with read-only access. While this prevents
100 *            the CPU from overwriting the page table,
101 *            it can still be corrupted by PCI bus masters
102 *            (like DMA engines, [VME] bridges etc.) and
103 *            even by this CPU if either the MMU is off
104 *            or if there is a DBAT mapping granting write
105 *            access...
106 */
107Triv121PgTbl
108triv121PgTblInit(unsigned long base, unsigned ldSize);
109
110/* get the log2 of the minimal page table size needed
111 * for mapping 'size' bytes.
112 *
113 * EXAMPLE: create a page table which maps the entire
114 *          physical memory. The page table itself shall
115 *          be allocated at the top of the available
116 *          memory (assuming 'memsize' is a power of two):
117 *
118 *  ldSize = triv121PgTblLdMinSize(memsize);
119 *  memsize -= (1<<ldSize);  / * reduce memory available to RTEMS * /
120 *  pgTbl  = triv121PgTblInit(memsize,ldSize);
121 *
122 */
123unsigned long
124triv121PgTblLdMinSize(unsigned long size);
125
126/* Map an address range 1:1 in pgTbl with the given protection;
127 *
128 * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index
129 *          for which no PTE could be allocated, on failure.
130 *
131 * NOTES:   - This routine returns MINUS ONE ON SUCCESS
132 *          - (parts) of a mapping which overlap with
133 *            already existing PTEs are silently ignored.
134 *
135 *            Therefore, you can e.g. first create
136 *            a couple of write protected maps and
137 *            finally map the entire memory r/w. This
138 *            will leave the write protected maps
139 *            intact.
140 */
141long
142triv121PgTblMap(
143  Triv121PgTbl  pgTbl,     /* handle, returned by Init or Get */
144
145  long          vsid,      /* vsid for this mapping (contains topmost 4 bits of EA);
146                            *
147                            * NOTE: it is allowed to pass a VSID < 0 to tell this
148                            *       routine it should use a VSID corresponding to a
149                            *       1:1:1  effective - virtual - physical  mapping
150                            */
151
152  unsigned long start,     /* segment offset (lowermost 28 bits of EA) of address range
153                            *
154                            * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
155                            *       preted as an effective address (EA), i.e. all 32
156                            *       bits are used - the most significant four going into
157                            *       to the VSID...
158                            */
159
160  unsigned long numPages,  /* number of pages to map */
161
162  unsigned wimgAttr,       /* 'wimg' attributes
163                            * (Write thru, cache Inhibit, coherent Memory,
164                            *  Guarded memory)
165                            */
166
167  unsigned protection      /* 'pp' access protection: Super      User
168                            *
169                            *   0                      r/w       none
170                            *   1                      r/w       ro   
171                            *   2                      r/w       r/w
172                            *   3                      ro        ro
173                            */
174);
175
176#define TRIV121_ATTR_W  8
177#define TRIV121_ATTR_I  4
178#define TRIV121_ATTR_M  2
179#define TRIV121_ATTR_G  1
180
181/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
182 * and guarded pages. RTM about the 'eieio' instruction!
183 */
184#define TRIV121_ATTR_IO_PAGE    (TRIV121_ATTR_I|TRIV121_ATTR_G)
185
186#define TRIV121_PP_RO_PAGE      (1)  /* read-only for key = 1, unlocked by key=0 */
187#define TRIV121_PP_RW_PAGE      (2)  /* read-write for key = 1/0                 */
188
189#define TRIV121_121_VSID        (-1) /* use 1:1 effective<->virtual address mapping */
190#define TRIV121_SEG_VSID        (-2) /* lookup VSID in the segment register         */
191
192#define TRIV121_MAP_SUCCESS     (-1) /* triv121PgTblMap() returns this on SUCCESS */
193
194/* get a handle to the one and only page table
195 * (must have been initialized/allocated)
196 *
197 * RETURNS: NULL if the page table has not been initialized/allocated.
198 */
199Triv121PgTbl
200triv121PgTblGet(void);
201
202/*
203 * compute the SDR1 register value for the page table
204 */
205
206unsigned long
207triv121PgTblSDR1(Triv121PgTbl pgTbl);
208
209/*
210 * Activate the page table:
211 *  - set up the segment registers for a 1:1 effective <-> virtual address mapping,
212 *    give user and supervisor keys.
213 *  - set up the SDR1 register
214 *  - flush all tlbs
215 *  - 'lock' pgTbl, i.e. prevent all further modifications.
216 *
217 * NOTE: This routine does not change any BATs. Since these
218 *       have priority over the page table, the user
219 *       may have to switch overlapping BATs OFF in order
220 *       for the page table mappings to take effect.
221 */
222void
223triv121PgTblActivate(Triv121PgTbl pgTbl);
224
225/* Find the PTE for a EA and print its contents to stdout
226 * RETURNS: pte for EA or NULL if no entry was found.
227 */
228APte
229triv121DumpEa(unsigned long ea);
230
231/* Find and return a PTE for a vsid/pi combination
232 * RETURNS: pte or NULL if no entry was found
233 */
234APte
235triv121FindPte(unsigned long vsid, unsigned long pi);
236
237/*
238 * Unmap an effective address
239 *
240 * RETURNS: pte that mapped the ea or NULL if no
241 *          mapping existed.
242 */
243APte
244triv121UnmapEa(unsigned long ea);
245
246/*
247 * Change the WIMG and PP attributes of the page containing 'ea'
248 *
249 * NOTES:   The 'wimg' and 'pp' may be <0 to indicate that no
250 *          change is desired.
251 *
252 * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped.
253 */
254APte
255triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp);
256
257/* Make the whole page table writable
258 * NOTES:   If the page table has not been initialized yet,
259 *          this routine has no effect (i.e., after
260 *          initialization the page table will still be read-only).
261 */
262void
263triv121MakePgTblRW();
264
265/* Make the whole page table read-only
266 */
267void
268triv121MakePgTblRO();
269
270/* Dump a pte to stdout */
271long
272triv121DumpPte(APte pte);
273
274#endif
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