source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h @ 1b1b43cc

4.104.114.84.9
Last change on this file since 1b1b43cc was 1b1b43cc, checked in by Till Straumann <strauman@…>, on Nov 3, 2005 at 2:26:08 AM

2005-11-02 straumanatslacdotstanford.edu

  • mpc6xx/mmu/pte121.c, mpc6xx/mmu/pte121.h: enhancements to mpc6xx page table support - PTEs can now be modified even if the page table is already active; bugfix: address range crossing 256MB boundary was not handled correctly
  • Property mode set to 100644
File size: 7.6 KB
Line 
1#ifndef _LIBCPU_PTE121_H
2#define _LIBCPU_PTE121_H
3/* $Id$ */
4
5/* Rudimentary page/hash table support for Powerpc
6 *
7 * A simple, static (i.e. no 'per-process' virtual
8 * address space etc.) page table providing
9 * one-to-one effective <-> virtual <-> physical
10 * address mapping.
11 *
12 * PURPOSE:
13 *    1) allow write-protection of text/read-only data areas
14 *    2) provide more effective-address space in case
15 *       the BATs are not enough
16 *    3) allow 'alias' mappings. Such aliases can only use
17 *       the upper bits of the VSID since VSID & 0xf and the
18 *       PI are always mapped 1:1 to the RPN.
19 * LIMITATIONS:
20 *    -  no PTE replacement (makes no sense in a real-time
21 *       environment, anyway) -> the page table just MUST
22 *       be big enough!.
23 *    -  only one page table supported.
24 *    -  no locking implemented. If multiple threads modify
25 *       the page table, it is the user's responsibility to
26 *       implement exclusive access.
27 */
28
29/* Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 - 2004 */
30
31/* I don't include mmu.h here because it says it's derived from linux
32 * and I want to avoid licensing problems
33 */
34
35/* Abstract handle for a page table */
36typedef struct Triv121PgTblRec_ *Triv121PgTbl;
37
38/* A PTE entry */
39typedef struct PTERec_ {
40  volatile unsigned long v:1,    vsid:24, h:1, api: 6;
41  volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2;
42} PTERec, *APte;
43
44/* Initialize a trivial page table
45 * using 2^ldSize bytes of memory starting at
46 * 'base'.
47 *
48 * RETURNS: a handle to the internal data structure
49 *          used to manage the page table. NULL on
50 *          error.
51 *         
52 * NOTES:   - 'base' must be aligned to the size
53 *          - minimal ldSize is 16 (== 64k)
54 *          - this routine maps the page table itself
55 *            with read-only access. While this prevents
56 *            the CPU from overwriting the page table,
57 *            it can still be corrupted by PCI bus masters
58 *            (like DMA engines, [VME] bridges etc.) and
59 *            even by this CPU if either the MMU is off
60 *            or if there is a DBAT mapping granting write
61 *            access...
62 */
63Triv121PgTbl
64triv121PgTblInit(unsigned long base, unsigned ldSize);
65
66/* get the log2 of the minimal page table size needed
67 * for mapping 'size' bytes.
68 *
69 * EXAMPLE: create a page table which maps the entire
70 *          physical memory. The page table itself shall
71 *          be allocated at the top of the available
72 *          memory (assuming 'memsize' is a power of two):
73 *
74 *  ldSize = triv121PgTblLdMinSize(memsize);
75 *  memsize -= (1<<ldSize);  / * reduce memory available to RTEMS * /
76 *  pgTbl  = triv121PgTblInit(memsize,ldSize);
77 *
78 */
79unsigned long
80triv121PgTblLdMinSize(unsigned long size);
81
82/* Map an address range 1:1 in pgTbl with the given protection;
83 *
84 * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index
85 *          for which no PTE could be allocated, on failure.
86 *
87 * NOTES:   - This routine returns MINUS ONE ON SUCCESS
88 *          - (parts) of a mapping which overlap with
89 *            already existing PTEs are silently ignored.
90 *
91 *            Therefore, you can e.g. first create
92 *            a couple of write protected maps and
93 *            finally map the entire memory r/w. This
94 *            will leave the write protected maps
95 *            intact.
96 */
97long
98triv121PgTblMap(
99  Triv121PgTbl  pgTbl,     /* handle, returned by Init or Get */
100
101  long          vsid,      /* vsid for this mapping (contains topmost 4 bits of EA);
102                            *
103                            * NOTE: it is allowed to pass a VSID < 0 to tell this
104                            *       routine it should use a VSID corresponding to a
105                            *       1:1:1  effective - virtual - physical  mapping
106                            */
107
108  unsigned long start,     /* segment offset (lowermost 28 bits of EA) of address range
109                            *
110                            * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
111                            *       preted as an effective address (EA), i.e. all 32
112                            *       bits are used - the most significant four going into
113                            *       to the VSID...
114                            */
115
116  unsigned long numPages,  /* number of pages to map */
117
118  unsigned wimgAttr,       /* 'wimg' attributes
119                            * (Write thru, cache Inhibit, coherent Memory,
120                            *  Guarded memory)
121                            */
122
123  unsigned protection      /* 'pp' access protection: Super      User
124                            *
125                            *   0                      r/w       none
126                            *   1                      r/w       ro   
127                            *   2                      r/w       r/w
128                            *   3                      ro        ro
129                            */
130);
131
132#define TRIV121_ATTR_W  8
133#define TRIV121_ATTR_I  4
134#define TRIV121_ATTR_M  2
135#define TRIV121_ATTR_G  1
136
137/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
138 * and guarded pages. RTM about the 'eieio' instruction!
139 */
140#define TRIV121_ATTR_IO_PAGE    (TRIV121_ATTR_I|TRIV121_ATTR_G)
141
142#define TRIV121_PP_RO_PAGE      (1)  /* read-only for key = 1, unlocked by key=0 */
143#define TRIV121_PP_RW_PAGE      (2)  /* read-write for key = 1/0                 */
144
145#define TRIV121_121_VSID        (-1) /* use 1:1 effective<->virtual address mapping */
146#define TRIV121_SEG_VSID        (-2) /* lookup VSID in the segment register         */
147
148#define TRIV121_MAP_SUCCESS     (-1) /* triv121PgTblMap() returns this on SUCCESS */
149
150/* get a handle to the one and only page table
151 * (must have been initialized/allocated)
152 *
153 * RETURNS: NULL if the page table has not been initialized/allocated.
154 */
155Triv121PgTbl
156triv121PgTblGet(void);
157
158/*
159 * compute the SDR1 register value for the page table
160 */
161
162unsigned long
163triv121PgTblSDR1(Triv121PgTbl pgTbl);
164
165/*
166 * Activate the page table:
167 *  - set up the segment registers for a 1:1 effective <-> virtual address mapping,
168 *    give user and supervisor keys.
169 *  - set up the SDR1 register
170 *  - flush all tlbs
171 *  - 'lock' pgTbl, i.e. prevent all further modifications.
172 *
173 * NOTE: This routine does not change any BATs. Since these
174 *       have priority over the page table, the user
175 *       may have to switch overlapping BATs OFF in order
176 *       for the page table mappings to take effect.
177 */
178void
179triv121PgTblActivate(Triv121PgTbl pgTbl);
180
181/* Find the PTE for a EA and print its contents to stdout
182 * RETURNS: pte for EA or NULL if no entry was found.
183 */
184APte
185triv121DumpEa(unsigned long ea);
186
187/* Find and return a PTE for a vsid/pi combination
188 * RETURNS: pte or NULL if no entry was found
189 */
190APte
191triv121FindPte(unsigned long vsid, unsigned long pi);
192
193/*
194 * Unmap an effective address
195 *
196 * RETURNS: pte that mapped the ea or NULL if no
197 *          mapping existed.
198 */
199APte
200triv121UnmapEa(unsigned long ea);
201
202/*
203 * Change the WIMG and PP attributes of the page containing 'ea'
204 *
205 * NOTES:   The 'wimg' and 'pp' may be <0 to indicate that no
206 *          change is desired.
207 *
208 * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped.
209 */
210APte
211triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp);
212
213/* Make the whole page table writable
214 * NOTES:   If the page table has not been initialized yet,
215 *          this routine has no effect (i.e., after
216 *          initialization the page table will still be read-only).
217 */
218void
219triv121MakePgTblRW();
220
221/* Make the whole page table read-only
222 */
223void
224triv121MakePgTblRO();
225
226/* Dump a pte to stdout */
227long
228triv121DumpPte(APte pte);
229
230#endif
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