source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h

4.11
Last change on this file was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

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1#ifndef _LIBCPU_PTE121_H
2#define _LIBCPU_PTE121_H
3
4/*
5 * Authorship
6 * ----------
7 * This software was created by
8 *     Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004,
9 *         Stanford Linear Accelerator Center, Stanford University.
10 *
11 * Acknowledgement of sponsorship
12 * ------------------------------
13 * This software was produced by
14 *     the Stanford Linear Accelerator Center, Stanford University,
15 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
16 *
17 * Government disclaimer of liability
18 * ----------------------------------
19 * Neither the United States nor the United States Department of Energy,
20 * nor any of their employees, makes any warranty, express or implied, or
21 * assumes any legal liability or responsibility for the accuracy,
22 * completeness, or usefulness of any data, apparatus, product, or process
23 * disclosed, or represents that its use would not infringe privately owned
24 * rights.
25 *
26 * Stanford disclaimer of liability
27 * --------------------------------
28 * Stanford University makes no representations or warranties, express or
29 * implied, nor assumes any liability for the use of this software.
30 *
31 * Stanford disclaimer of copyright
32 * --------------------------------
33 * Stanford University, owner of the copyright, hereby disclaims its
34 * copyright and all other rights in this software.  Hence, anyone may
35 * freely use it for any purpose without restriction.
36 *
37 * Maintenance of notices
38 * ----------------------
39 * In the interest of clarity regarding the origin and status of this
40 * SLAC software, this and all the preceding Stanford University notices
41 * are to remain affixed to any copy or derivative of this software made
42 * or distributed by the recipient and are to be affixed to any copy of
43 * software made or distributed by the recipient that contains a copy or
44 * derivative of this software.
45 *
46 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
47 */
48
49/* Rudimentary page/hash table support for Powerpc
50 *
51 * A simple, static (i.e. no 'per-process' virtual
52 * address space etc.) page table providing
53 * one-to-one effective <-> virtual <-> physical
54 * address mapping.
55 *
56 * PURPOSE:
57 *    1) allow write-protection of text/read-only data areas
58 *    2) provide more effective-address space in case
59 *       the BATs are not enough
60 *    3) allow 'alias' mappings. Such aliases can only use
61 *       the upper bits of the VSID since VSID & 0xf and the
62 *       PI are always mapped 1:1 to the RPN.
63 * LIMITATIONS:
64 *    -  no PTE replacement (makes no sense in a real-time
65 *       environment, anyway) -> the page table just MUST
66 *       be big enough!.
67 *    -  only one page table supported.
68 *    -  no locking implemented. If multiple threads modify
69 *       the page table, it is the user's responsibility to
70 *       implement exclusive access.
71 */
72
73
74/* I don't include mmu.h here because it says it's derived from linux
75 * and I want to avoid licensing problems
76 */
77
78/* Abstract handle for a page table */
79typedef struct Triv121PgTblRec_ *Triv121PgTbl;
80
81/* A PTE entry */
82typedef struct PTERec_ {
83  volatile unsigned long v:1,    vsid:24, h:1, api: 6;
84  volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2;
85} PTERec, *APte;
86
87/* Initialize a trivial page table
88 * using 2^ldSize bytes of memory starting at
89 * 'base'.
90 *
91 * RETURNS: a handle to the internal data structure
92 *          used to manage the page table. NULL on
93 *          error.
94 *
95 * NOTES:   - 'base' must be aligned to the size
96 *          - minimal ldSize is 16 (== 64k)
97 *          - this routine maps the page table itself
98 *            with read-only access. While this prevents
99 *            the CPU from overwriting the page table,
100 *            it can still be corrupted by PCI bus masters
101 *            (like DMA engines, [VME] bridges etc.) and
102 *            even by this CPU if either the MMU is off
103 *            or if there is a DBAT mapping granting write
104 *            access...
105 */
106Triv121PgTbl
107triv121PgTblInit(unsigned long base, unsigned ldSize);
108
109/* get the log2 of the minimal page table size needed
110 * for mapping 'size' bytes.
111 *
112 * EXAMPLE: create a page table which maps the entire
113 *          physical memory. The page table itself shall
114 *          be allocated at the top of the available
115 *          memory (assuming 'memsize' is a power of two):
116 *
117 *  ldSize = triv121PgTblLdMinSize(memsize);
118 *  memsize -= (1<<ldSize);  / * reduce memory available to RTEMS * /
119 *  pgTbl  = triv121PgTblInit(memsize,ldSize);
120 *
121 */
122unsigned long
123triv121PgTblLdMinSize(unsigned long size);
124
125/* Map an address range 1:1 in pgTbl with the given protection;
126 *
127 * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index
128 *          for which no PTE could be allocated, on failure.
129 *
130 * NOTES:   - This routine returns MINUS ONE ON SUCCESS
131 *          - (parts) of a mapping which overlap with
132 *            already existing PTEs are silently ignored.
133 *
134 *            Therefore, you can e.g. first create
135 *            a couple of write protected maps and
136 *            finally map the entire memory r/w. This
137 *            will leave the write protected maps
138 *            intact.
139 */
140long
141triv121PgTblMap(
142  Triv121PgTbl  pgTbl,     /* handle, returned by Init or Get */
143
144  long          vsid,      /* vsid for this mapping (contains topmost 4 bits of EA);
145                            *
146                            * NOTE: it is allowed to pass a VSID < 0 to tell this
147                            *       routine it should use a VSID corresponding to a
148                            *       1:1:1  effective - virtual - physical  mapping
149                            */
150
151  unsigned long start,     /* segment offset (lowermost 28 bits of EA) of address range
152                            *
153                            * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
154                            *       preted as an effective address (EA), i.e. all 32
155                            *       bits are used - the most significant four going into
156                            *       to the VSID...
157                            */
158
159  unsigned long numPages,  /* number of pages to map */
160
161  unsigned wimgAttr,       /* 'wimg' attributes
162                            * (Write thru, cache Inhibit, coherent Memory,
163                            *  Guarded memory)
164                            */
165
166  unsigned protection      /* 'pp' access protection: Super      User
167                            *
168                            *   0                      r/w       none
169                            *   1                      r/w       ro
170                            *   2                      r/w       r/w
171                            *   3                      ro        ro
172                            */
173);
174
175#define TRIV121_ATTR_W  8
176#define TRIV121_ATTR_I  4
177#define TRIV121_ATTR_M  2
178#define TRIV121_ATTR_G  1
179
180/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
181 * and guarded pages. RTM about the 'eieio' instruction!
182 */
183#define TRIV121_ATTR_IO_PAGE    (TRIV121_ATTR_I|TRIV121_ATTR_G)
184
185#define TRIV121_PP_RO_PAGE      (1)  /* read-only for key = 1, unlocked by key=0 */
186#define TRIV121_PP_RW_PAGE      (2)  /* read-write for key = 1/0                 */
187
188#define TRIV121_121_VSID        (-1) /* use 1:1 effective<->virtual address mapping */
189#define TRIV121_SEG_VSID        (-2) /* lookup VSID in the segment register         */
190
191#define TRIV121_MAP_SUCCESS     (-1) /* triv121PgTblMap() returns this on SUCCESS */
192
193/* get a handle to the one and only page table
194 * (must have been initialized/allocated)
195 *
196 * RETURNS: NULL if the page table has not been initialized/allocated.
197 */
198Triv121PgTbl
199triv121PgTblGet(void);
200
201/*
202 * compute the SDR1 register value for the page table
203 */
204
205unsigned long
206triv121PgTblSDR1(Triv121PgTbl pgTbl);
207
208/*
209 * Activate the page table:
210 *  - set up the segment registers for a 1:1 effective <-> virtual address mapping,
211 *    give user and supervisor keys.
212 *  - set up the SDR1 register
213 *  - flush all tlbs
214 *  - 'lock' pgTbl, i.e. prevent all further modifications.
215 *
216 * NOTE: This routine does not change any BATs. Since these
217 *       have priority over the page table, the user
218 *       may have to switch overlapping BATs OFF in order
219 *       for the page table mappings to take effect.
220 */
221void triv121PgTblActivate(Triv121PgTbl pgTbl);
222
223/* Find the PTE for a EA and print its contents to stdout
224 * RETURNS: pte for EA or NULL if no entry was found.
225 */
226APte triv121DumpEa(unsigned long ea);
227
228/* Find and return a PTE for a vsid/pi combination
229 * RETURNS: pte or NULL if no entry was found
230 */
231APte triv121FindPte(unsigned long vsid, unsigned long pi);
232
233/*
234 * Unmap an effective address
235 *
236 * RETURNS: pte that mapped the ea or NULL if no
237 *          mapping existed.
238 */
239APte triv121UnmapEa(unsigned long ea);
240
241/*
242 * Change the WIMG and PP attributes of the page containing 'ea'
243 *
244 * NOTES:   The 'wimg' and 'pp' may be <0 to indicate that no
245 *          change is desired.
246 *
247 * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped.
248 */
249APte triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp);
250
251/* Make the whole page table writable
252 * NOTES:   If the page table has not been initialized yet,
253 *          this routine has no effect (i.e., after
254 *          initialization the page table will still be read-only).
255 */
256void triv121MakePgTblRW(void);
257
258/* Make the whole page table read-only
259 */
260void triv121MakePgTblRO(void);
261
262/* Dump a pte to stdout */
263long triv121DumpPte(APte pte);
264
265#endif
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