[11f894cc] | 1 | /* $Id$ */ |
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| 2 | |
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| 3 | /* Trivial page table setup for RTEMS |
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| 4 | * Purpose: allow write protection of text/ro-data |
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| 5 | * |
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| 6 | * Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002 |
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| 7 | */ |
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| 8 | |
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| 9 | /* Chose debugging options */ |
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| 10 | #undef DEBUG_MAIN /* create a standalone (host) program for basic testing */ |
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| 11 | #undef DEBUG /* target debugging and consistency checking */ |
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| 12 | #undef DEBUG_EXC /* add exception handler which reenables BAT0 and recovers from a page fault */ |
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| 13 | |
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| 14 | #ifdef DEBUG_MAIN |
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| 15 | #undef DEBUG /* must not use these together with DEBUG_MAIN */ |
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| 16 | #undef DEBUG_EXC |
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| 17 | #endif |
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| 18 | |
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| 19 | /***************************** INCLUDE HEADERS ****************************/ |
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| 20 | |
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| 21 | #ifndef DEBUG_MAIN |
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| 22 | #include <rtems.h> |
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| 23 | #include <rtems/bspIo.h> |
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[c0af822e] | 24 | #include <libcpu/cpuIdent.h> |
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[11f894cc] | 25 | #ifdef DEBUG_EXC |
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[d49389a] | 26 | #include <bsp.h> |
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[11f894cc] | 27 | #include <bsp/vectors.h> |
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| 28 | #include <libcpu/raw_exception.h> |
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| 29 | #endif |
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| 30 | #endif |
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| 31 | |
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| 32 | #include <stdio.h> |
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| 33 | #include <assert.h> |
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[d5fa21ef] | 34 | #include <string.h> |
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[11f894cc] | 35 | |
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| 36 | #include "pte121.h" |
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| 37 | |
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| 38 | /************************** CONSTANT DEFINITIONS **************************/ |
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| 39 | |
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| 40 | /* Base 2 logs of some sizes */ |
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| 41 | |
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| 42 | #ifndef DEBUG_MAIN |
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| 43 | |
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| 44 | #define LD_PHYS_SIZE 32 /* physical address space */ |
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| 45 | #define LD_PG_SIZE 12 /* page size */ |
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| 46 | #define LD_PTEG_SIZE 6 /* PTEG size */ |
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| 47 | #define LD_PTE_SIZE 3 /* PTE size */ |
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| 48 | #define LD_SEG_SIZE 28 /* segment size */ |
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| 49 | #define LD_MIN_PT_SIZE 16 /* minimal size of a page table */ |
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| 50 | #define LD_HASH_SIZE 19 /* lengh of a hash */ |
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| 51 | |
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| 52 | #else /* DEBUG_MAIN */ |
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| 53 | |
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| 54 | /* Reduced 'fantasy' sizes for testing */ |
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| 55 | #define LD_PHYS_SIZE 32 /* physical address space */ |
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| 56 | #define LD_PG_SIZE 6 /* page size */ |
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| 57 | #define LD_PTEG_SIZE 5 /* PTEG size */ |
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| 58 | #define LD_PTE_SIZE 3 /* PTE size */ |
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| 59 | #define LD_SEG_SIZE 28 /* segment size */ |
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| 60 | #define LD_MIN_PT_SIZE 7 /* minimal size of a page table */ |
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| 61 | #define LD_HASH_SIZE 19 /* lengh of a hash */ |
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| 62 | |
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| 63 | #endif /* DEBUG_MAIN */ |
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| 64 | |
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| 65 | /* Derived sizes */ |
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| 66 | |
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| 67 | /* Size of a page index */ |
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| 68 | #define LD_PI_SIZE ((LD_SEG_SIZE) - (LD_PG_SIZE)) |
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| 69 | |
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| 70 | /* Number of PTEs in a PTEG */ |
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| 71 | #define PTE_PER_PTEG (1<<((LD_PTEG_SIZE)-(LD_PTE_SIZE))) |
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| 72 | |
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| 73 | /* Segment register bits */ |
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| 74 | #define KEY_SUP (1<<30) /* supervisor mode key */ |
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| 75 | #define KEY_USR (1<<29) /* user mode key */ |
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| 76 | |
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| 77 | /* The range of effective addresses to scan with 'tlbie' |
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| 78 | * instructions in order to flush all TLBs. |
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| 79 | * On the 750 and 7400, there are 128 two way I and D TLBs, |
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| 80 | * indexed by EA[14:19]. Hence calling |
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| 81 | * tlbie rx |
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| 82 | * where rx scans 0x00000, 0x01000, 0x02000, ... 0x3f000 |
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| 83 | * is sufficient to do the job |
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| 84 | */ |
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| 85 | #define NUM_TLB_PER_WAY 64 /* 750 and 7400 have 128 two way TLBs */ |
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| 86 | #define FLUSH_EA_RANGE (NUM_TLB_PER_WAY<<LD_PG_SIZE) |
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| 87 | |
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| 88 | /*************************** MACRO DEFINITIONS ****************************/ |
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| 89 | |
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| 90 | /* Macros to split a (32bit) 'effective' address into |
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| 91 | * VSID (virtual segment id) and PI (page index) |
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| 92 | * using a 1:1 mapping of 'effective' to 'virtual' |
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| 93 | * addresses. |
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| 94 | * |
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| 95 | * For 32bit addresses this looks like follows |
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| 96 | * (each 'x' or '0' stands for a 'nibble' [4bits]): |
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| 97 | * |
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| 98 | * 32bit effective address (EA) |
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| 99 | * |
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| 100 | * x x x x x x x x |
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| 101 | * | | |
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| 102 | * 0 0 0 0 0 x|x x x x|x x x |
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| 103 | * VSID | PI | PO (page offset) |
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| 104 | * | | |
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| 105 | */ |
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| 106 | /* 1:1 VSID of an EA */ |
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| 107 | #define VSID121(ea) (((ea)>>LD_SEG_SIZE) & ((1<<(LD_PHYS_SIZE-LD_SEG_SIZE))-1)) |
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| 108 | /* page index of an EA */ |
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| 109 | #define PI121(ea) (((ea)>>LD_PG_SIZE) & ((1<<LD_PI_SIZE)-1)) |
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| 110 | |
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| 111 | |
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| 112 | /* Primary and secondary PTE hash functions */ |
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| 113 | |
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| 114 | /* Compute the primary hash from a VSID and a PI */ |
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| 115 | #define PTE_HASH1(vsid, pi) (((vsid)^(pi))&((1<<LD_HASH_SIZE)-1)) |
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| 116 | |
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| 117 | /* Compute the secondary hash from a primary hash */ |
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| 118 | #define PTE_HASH2(hash1) ((~(hash1))&((1<<LD_HASH_SIZE)-1)) |
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| 119 | |
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| 120 | /* Extract the abbreviated page index (which is the |
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| 121 | * part of the PI which does not go into the hash |
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| 122 | * under all circumstances [10 bits to -> 6bit API]) |
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| 123 | */ |
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| 124 | #define API(pi) ((pi)>>((LD_MIN_PT_SIZE)-(LD_PTEG_SIZE))) |
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| 125 | |
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| 126 | |
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| 127 | /* Horrible Macros */ |
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[d49389a] | 128 | #ifdef __rtems__ |
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[11f894cc] | 129 | /* must not use printf until multitasking is up */ |
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| 130 | typedef void (*PrintF)(char *,...); |
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| 131 | static PrintF whatPrintf(void) |
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| 132 | { |
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| 133 | return _Thread_Executing ? |
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| 134 | (PrintF)printf : |
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| 135 | printk; |
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| 136 | } |
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| 137 | |
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| 138 | #define PRINTF(args...) ((void)(whatPrintf())(args)) |
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| 139 | #else |
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| 140 | #define PRINTF(args...) printf(args) |
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| 141 | #endif |
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| 142 | |
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| 143 | #ifdef DEBUG |
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| 144 | unsigned long |
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| 145 | triv121PgTblConsistency(Triv121PgTbl pt, int pass, int expect); |
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| 146 | |
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| 147 | static int consistencyPass=0; |
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| 148 | #define CONSCHECK(expect) triv121PgTblConsistency(&pgTbl,consistencyPass++,(expect)) |
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| 149 | #else |
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| 150 | #define CONSCHECK(expect) do {} while (0) |
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| 151 | #endif |
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| 152 | |
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| 153 | /**************************** TYPE DEFINITIONS ****************************/ |
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| 154 | |
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| 155 | /* A PTE entry */ |
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| 156 | typedef struct PTERec_ { |
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| 157 | unsigned long v:1, vsid:24, h:1, api: 6; |
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| 158 | unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2; |
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| 159 | } PTERec, *PTE; |
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| 160 | |
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| 161 | /* internal description of a trivial page table */ |
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| 162 | typedef struct Triv121PgTblRec_ { |
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| 163 | PTE base; |
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| 164 | unsigned long size; |
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| 165 | int active; |
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| 166 | } Triv121PgTblRec; |
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| 167 | |
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| 168 | |
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| 169 | /************************** FORWARD DECLARATIONS *************************/ |
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| 170 | |
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| 171 | #ifdef DEBUG_EXC |
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| 172 | static void |
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| 173 | myhdl(BSP_Exception_frame* excPtr); |
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| 174 | #endif |
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| 175 | |
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| 176 | #if defined(DEBUG_MAIN) || defined(DEBUG) |
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| 177 | static void |
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| 178 | dumpPte(PTE pte); |
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| 179 | #endif |
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| 180 | |
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| 181 | #ifdef DEBUG |
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| 182 | static void |
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| 183 | dumpPteg(unsigned long vsid, unsigned long pi, unsigned long hash); |
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| 184 | unsigned long |
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| 185 | triv121IsRangeMapped(unsigned long start, unsigned long end); |
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| 186 | #endif |
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| 187 | |
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| 188 | /**************************** STATIC VARIABLES ****************************/ |
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| 189 | |
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| 190 | /* dont malloc - we might have to use this before |
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| 191 | * we have malloc or even RTEMS workspace available |
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| 192 | */ |
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| 193 | static Triv121PgTblRec pgTbl={0}; |
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| 194 | |
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| 195 | #ifdef DEBUG_EXC |
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| 196 | static void *ohdl; /* keep a pointer to the original handler */ |
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| 197 | #endif |
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| 198 | |
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| 199 | /*********************** INLINES & PRIVATE ROUTINES ***********************/ |
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| 200 | |
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| 201 | /* compute the page table entry group (PTEG) of a hash */ |
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| 202 | static inline PTE |
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| 203 | ptegOf(Triv121PgTbl pt, unsigned long hash) |
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| 204 | { |
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| 205 | hash &= ((1<<LD_HASH_SIZE)-1); |
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| 206 | return (PTE)(((unsigned long)pt->base) | ((hash<<LD_PTEG_SIZE) & (pt->size-1))); |
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| 207 | } |
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| 208 | |
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| 209 | /* see if a vsid/pi combination is already mapped |
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| 210 | * |
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| 211 | * RETURNS: PTE of mapping / NULL if none exists |
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| 212 | * |
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| 213 | * NOTE: a vsid<0 is legal and will tell this |
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| 214 | * routine that 'pi' is actually an EA to |
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| 215 | * be split into vsid and pi... |
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| 216 | */ |
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| 217 | static PTE |
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| 218 | alreadyMapped(Triv121PgTbl pt, long vsid, unsigned long pi) |
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| 219 | { |
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| 220 | int i; |
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| 221 | unsigned long hash,api; |
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| 222 | PTE pte; |
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| 223 | |
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| 224 | if (!pt->size) |
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| 225 | return 0; |
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| 226 | |
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| 227 | if (vsid<0) { |
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| 228 | vsid=VSID121(pi); |
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| 229 | pi=PI121(pi); |
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| 230 | } |
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| 231 | |
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| 232 | hash = PTE_HASH1(vsid,pi); |
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| 233 | api=API(pi); |
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| 234 | for (i=0, pte=ptegOf(pt,hash); i<PTE_PER_PTEG; i++,pte++) |
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| 235 | if (pte->v && pte->vsid==vsid && pte->api==api && 0==pte->h) |
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| 236 | return pte; |
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| 237 | /* try the secondary hash table */ |
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| 238 | hash = PTE_HASH2(hash); |
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| 239 | for (i=0, pte=ptegOf(pt,hash); i<PTE_PER_PTEG; i++,pte++) |
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| 240 | if (pte->v && pte->vsid==vsid && pte->api==api && 1==pte->h) |
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| 241 | return pte; |
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| 242 | return 0; |
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| 243 | } |
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| 244 | |
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| 245 | /* find the first available slot for vsid/pi |
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| 246 | * |
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| 247 | * NOTE: it is NOT legal to pass a vsid<0 / EA combination. |
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| 248 | * |
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| 249 | * RETURNS free slot with the 'marked' field set. The 'h' |
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| 250 | * field is set to 0 or one, depending on whether |
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| 251 | * the slot was allocated by using the primary or |
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| 252 | * the secondary hash, respectively. |
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| 253 | */ |
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| 254 | static PTE |
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| 255 | slotFor(Triv121PgTbl pt, unsigned long vsid, unsigned long pi) |
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| 256 | { |
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| 257 | int i; |
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| 258 | unsigned long hash,api; |
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| 259 | PTE pte; |
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| 260 | |
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| 261 | /* primary hash */ |
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| 262 | hash = PTE_HASH1(vsid,pi); |
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| 263 | api=API(pi); |
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| 264 | /* linear search thru all buckets for this hash */ |
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| 265 | for (i=0, pte=ptegOf(pt,hash); i<PTE_PER_PTEG; i++,pte++) { |
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| 266 | if (!pte->v && !pte->marked) { |
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| 267 | /* found a free PTE; mark it as potentially used and return */ |
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| 268 | pte->h=0; /* found by the primary hash fn */ |
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| 269 | pte->marked=1; |
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| 270 | return pte; |
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| 271 | } |
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| 272 | } |
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| 273 | |
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| 274 | #ifdef DEBUG |
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| 275 | /* Strange: if the hash table was allocated big enough, |
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| 276 | * this should not happen (when using a 1:1 mapping) |
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| 277 | * Give them some information... |
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| 278 | */ |
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| 279 | PRINTF("## First hash bucket full - "); |
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| 280 | dumpPteg(vsid,pi,hash); |
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| 281 | #endif |
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| 282 | |
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| 283 | hash = PTE_HASH2(hash); |
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| 284 | #ifdef DEBUG |
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| 285 | PRINTF(" Secondary pteg is 0x%08x\n", (unsigned)ptegOf(pt,hash)); |
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| 286 | #endif |
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| 287 | for (i=0, pte=ptegOf(pt,hash); i<PTE_PER_PTEG; i++,pte++) { |
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| 288 | if (!pte->v && !pte->marked) { |
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| 289 | /* mark this pte as potentially used */ |
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| 290 | pte->marked=1; |
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| 291 | pte->h=1; |
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| 292 | return pte; |
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| 293 | } |
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| 294 | } |
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| 295 | #ifdef DEBUG |
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| 296 | /* Even more strange - most likely, something is REALLY messed up */ |
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| 297 | PRINTF("## Second hash bucket full - "); |
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| 298 | dumpPteg(vsid,pi,hash); |
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| 299 | #endif |
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| 300 | return 0; |
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| 301 | } |
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| 302 | |
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| 303 | /* unmark all entries */ |
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| 304 | static void |
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| 305 | unmarkAll(Triv121PgTbl pt) |
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| 306 | { |
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| 307 | unsigned long n=pt->size / sizeof(PTERec); |
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| 308 | unsigned long i; |
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| 309 | PTE pte; |
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| 310 | for (i=0,pte=pt->base; i<n; i++,pte++) |
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| 311 | pte->marked=0; |
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| 312 | |
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| 313 | } |
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| 314 | |
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| 315 | /* calculate the minimal size of a page/hash table |
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| 316 | * to map a range of 'size' bytes in EA space. |
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| 317 | * |
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| 318 | * RETURNS: size in 'number of bits', i.e. the |
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| 319 | * integer part of LOGbase2(minsize) |
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| 320 | * is returned. |
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| 321 | * NOTE: G3/G4 machines need at least 16 bits |
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| 322 | * (64k). |
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| 323 | */ |
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| 324 | unsigned long |
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| 325 | triv121PgTblLdMinSize(unsigned long size) |
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| 326 | { |
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| 327 | unsigned long i; |
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| 328 | /* round 'size' up to the next page boundary */ |
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| 329 | size += (1<<LD_PG_SIZE)-1; |
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| 330 | size &= ~((1<<LD_PG_SIZE)-1); |
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| 331 | /* divide by number of PTEs and multiply |
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| 332 | * by the size of a PTE. |
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| 333 | */ |
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| 334 | size >>= LD_PG_SIZE - LD_PTE_SIZE; |
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| 335 | /* find the next power of 2 >= size */ |
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| 336 | for (i=0; i<LD_PHYS_SIZE; i++) { |
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| 337 | if ((1<<i) >= size) |
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| 338 | break; |
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| 339 | } |
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| 340 | /* pop up to the allowed minimum, if necessary */ |
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| 341 | if (i<LD_MIN_PT_SIZE) |
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| 342 | i=LD_MIN_PT_SIZE; |
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| 343 | return i; |
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| 344 | } |
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| 345 | |
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| 346 | /* initialize a trivial page table of 2^ldSize bytes |
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| 347 | * at 'base' in memory. |
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| 348 | * |
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| 349 | * RETURNS: OPAQUE HANDLE (not the hash table address) |
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| 350 | * or NULL on failure. |
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| 351 | */ |
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| 352 | Triv121PgTbl |
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| 353 | triv121PgTblInit(unsigned long base, unsigned ldSize) |
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| 354 | { |
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| 355 | if (pgTbl.size) { |
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| 356 | /* already initialized */ |
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| 357 | return 0; |
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| 358 | } |
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| 359 | |
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| 360 | if (ldSize < LD_MIN_PT_SIZE) |
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| 361 | return 0; /* too small */ |
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| 362 | |
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| 363 | if (base & ((1<<ldSize)-1)) |
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| 364 | return 0; /* misaligned */ |
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| 365 | |
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[d49389a] | 366 | /* This was tested on 604r, 750 and 7400. |
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| 367 | * On other CPUs, verify that the TLB invalidation works |
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[11f894cc] | 368 | * for a new CPU variant and that it has hardware PTE lookup/ |
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| 369 | * TLB replacement before adding it to this list. |
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| 370 | * |
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| 371 | * NOTE: The 603 features no hardware PTE lookup - and |
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| 372 | * hence the page tables should NOT be used. |
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| 373 | * Although lookup could be implemented in |
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| 374 | * software this is probably not desirable |
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| 375 | * as it could have an impact on hard realtime |
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| 376 | * performance, screwing deterministic latency! |
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| 377 | * (Could still be useful for debugging, though) |
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| 378 | */ |
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| 379 | if ( PPC_604 !=current_ppc_cpu && |
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| 380 | PPC_604e !=current_ppc_cpu && |
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| 381 | PPC_604r !=current_ppc_cpu && |
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| 382 | PPC_750 !=current_ppc_cpu && |
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| 383 | PPC_7400 !=current_ppc_cpu ) |
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| 384 | return 0; /* unsupported by this CPU */ |
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| 385 | |
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| 386 | pgTbl.base=(PTE)base; |
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| 387 | pgTbl.size=1<<ldSize; |
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| 388 | /* clear all page table entries */ |
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| 389 | memset(pgTbl.base, 0, pgTbl.size); |
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| 390 | |
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| 391 | CONSCHECK(0); |
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| 392 | |
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| 393 | /* map the page table itself 'm' and 'readonly' */ |
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| 394 | if (triv121PgTblMap(&pgTbl, |
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| 395 | TRIV121_121_VSID, |
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| 396 | base, |
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| 397 | (pgTbl.size >> LD_PG_SIZE), |
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| 398 | TRIV121_ATTR_M, |
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| 399 | TRIV121_PP_RO_PAGE) >= 0) |
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| 400 | return 0; |
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| 401 | |
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| 402 | CONSCHECK((pgTbl.size>>LD_PG_SIZE)); |
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| 403 | |
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| 404 | return &pgTbl; |
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| 405 | } |
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| 406 | |
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| 407 | /* return the handle of the (one and only) page table |
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| 408 | * or NULL if none has been initialized yet. |
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| 409 | */ |
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| 410 | Triv121PgTbl |
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| 411 | triv121PgTblGet(void) |
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| 412 | { |
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| 413 | return pgTbl.size ? &pgTbl : 0; |
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| 414 | } |
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| 415 | |
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| 416 | /* NOTE: this routine returns -1 on success; |
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| 417 | * on failure, the page table index for |
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| 418 | * which no PTE could be allocated is returned |
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| 419 | * |
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| 420 | * (Consult header about argument/return value |
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| 421 | * description) |
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| 422 | */ |
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| 423 | long |
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| 424 | triv121PgTblMap( |
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| 425 | Triv121PgTbl pt, |
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| 426 | long vsid, |
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| 427 | unsigned long start, |
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| 428 | unsigned long numPages, |
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| 429 | unsigned attributes, |
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| 430 | unsigned protection |
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| 431 | ) |
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| 432 | { |
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| 433 | int i,pass; |
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| 434 | unsigned long pi; |
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| 435 | PTE pte; |
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| 436 | |
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| 437 | /* already activated - no change allowed */ |
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| 438 | if (pt->active) |
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| 439 | return -1; |
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| 440 | |
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| 441 | if (vsid < 0) { |
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| 442 | /* use 1:1 mapping */ |
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| 443 | vsid = VSID121(start); |
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| 444 | } |
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| 445 | |
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| 446 | #ifdef DEBUG |
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| 447 | PRINTF("Mapping %i (0x%x) pages at 0x%08x for VSID 0x%08x\n", |
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| 448 | (unsigned)numPages, (unsigned)numPages, |
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| 449 | (unsigned)start, (unsigned)vsid); |
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| 450 | #endif |
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| 451 | |
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| 452 | /* map in two passes. During the first pass, we try |
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| 453 | * to claim entries as needed. The 'slotFor()' routine |
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| 454 | * will 'mark' the claimed entries without 'valid'ating |
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| 455 | * them. |
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| 456 | * If the mapping fails, all claimed entries are unmarked |
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| 457 | * and we return the PI for which allocation failed. |
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| 458 | * |
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| 459 | * Once we know that the allocation would succeed, we |
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| 460 | * do a second pass; during the second pass, the PTE |
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| 461 | * is actually written. |
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| 462 | * |
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| 463 | */ |
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| 464 | for (pass=0; pass<2; pass++) { |
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| 465 | /* check if we would succeed during the first pass */ |
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| 466 | for (i=0, pi=PI121(start); i<numPages; i++,pi++) { |
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| 467 | /* leave alone existing mappings for this EA */ |
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| 468 | if (!alreadyMapped(pt, vsid, pi)) { |
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| 469 | if (!(pte=slotFor(pt, vsid, pi))) { |
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| 470 | /* no free slot found for page index 'pi' */ |
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| 471 | unmarkAll(pt); |
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| 472 | return pi; |
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| 473 | } else { |
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| 474 | /* have a free slot; marked by slotFor() */ |
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| 475 | if (pass) { |
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| 476 | /* second pass; do the real work */ |
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| 477 | pte->vsid=vsid; |
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| 478 | /* H was set by slotFor() */ |
---|
| 479 | pte->api =API(pi); |
---|
| 480 | /* set up 1:1 mapping */ |
---|
| 481 | pte->rpn =((((unsigned long)vsid)&((1<<(LD_PHYS_SIZE-LD_SEG_SIZE))-1))<<LD_PI_SIZE) | pi; |
---|
| 482 | pte->wimg=attributes & 0xf; |
---|
| 483 | pte->pp=protection&0x3; |
---|
| 484 | /* mark it valid */ |
---|
| 485 | pte->v=1; |
---|
| 486 | pte->marked=0; |
---|
| 487 | #ifdef DEBUG |
---|
| 488 | /* add paranoia */ |
---|
| 489 | assert(alreadyMapped(pt, vsid, pi) == pte); |
---|
| 490 | #endif |
---|
| 491 | } |
---|
| 492 | } |
---|
| 493 | } |
---|
| 494 | } |
---|
| 495 | unmarkAll(pt); |
---|
| 496 | } |
---|
| 497 | #ifdef DEBUG |
---|
| 498 | { |
---|
| 499 | unsigned long failedat; |
---|
| 500 | CONSCHECK(-1); |
---|
| 501 | /* double check that the requested range is mapped */ |
---|
| 502 | failedat=triv121IsRangeMapped(start, start + (1<<LD_PG_SIZE)*numPages); |
---|
| 503 | if (0x0C0C != failedat) { |
---|
| 504 | PRINTF("triv121 mapping failed at 0x%08x\n",(unsigned)failedat); |
---|
| 505 | return PI121(failedat); |
---|
| 506 | } |
---|
| 507 | } |
---|
| 508 | #endif |
---|
| 509 | return TRIV121_MAP_SUCCESS; /* -1 !! */ |
---|
| 510 | } |
---|
| 511 | |
---|
| 512 | unsigned long |
---|
| 513 | triv121PgTblSDR1(Triv121PgTbl pt) |
---|
| 514 | { |
---|
| 515 | return (((unsigned long)pt->base) & ~(LD_MIN_PT_SIZE-1)) | |
---|
| 516 | ( ((pt->size-1) >> LD_MIN_PT_SIZE) & |
---|
| 517 | ((1<<(LD_HASH_SIZE-(LD_MIN_PT_SIZE-LD_PTEG_SIZE)))-1) |
---|
| 518 | ); |
---|
| 519 | } |
---|
| 520 | |
---|
| 521 | void |
---|
| 522 | triv121PgTblActivate(Triv121PgTbl pt) |
---|
| 523 | { |
---|
| 524 | #ifndef DEBUG_MAIN |
---|
| 525 | unsigned long sdr1=triv121PgTblSDR1(pt); |
---|
| 526 | #endif |
---|
| 527 | pt->active=1; |
---|
| 528 | |
---|
| 529 | #ifndef DEBUG_MAIN |
---|
| 530 | #ifdef DEBUG_EXC |
---|
| 531 | /* install our exception handler */ |
---|
| 532 | ohdl=globalExceptHdl; |
---|
| 533 | globalExceptHdl=myhdl; |
---|
| 534 | __asm__ __volatile__ ("sync"); |
---|
| 535 | #endif |
---|
| 536 | |
---|
| 537 | /* This section of assembly code takes care of the |
---|
| 538 | * following: |
---|
| 539 | * - get MSR and switch interrupts + MMU off |
---|
| 540 | * |
---|
| 541 | * - load up the segment registers with a |
---|
| 542 | * 1:1 effective <-> virtual mapping; |
---|
| 543 | * give user & supervisor keys |
---|
| 544 | * |
---|
| 545 | * - flush all TLBs; |
---|
| 546 | * NOTE: the TLB flushing code is probably |
---|
| 547 | * CPU dependent! |
---|
| 548 | * |
---|
| 549 | * - setup SDR1 |
---|
| 550 | * |
---|
| 551 | * - restore original MSR |
---|
| 552 | */ |
---|
| 553 | __asm__ __volatile( |
---|
| 554 | " mtctr %0\n" |
---|
| 555 | /* Get MSR and switch interrupts off - just in case. |
---|
| 556 | * Also switch the MMU off; the book |
---|
| 557 | * says that SDR1 must not be changed with either |
---|
| 558 | * MSR_IR or MSR_DR set. I would guess that it could |
---|
| 559 | * be safe as long as the IBAT & DBAT mappings override |
---|
| 560 | * the page table... |
---|
| 561 | */ |
---|
| 562 | " mfmsr %0\n" |
---|
| 563 | " andc %6, %0, %6\n" |
---|
| 564 | " mtmsr %6\n" |
---|
| 565 | " isync \n" |
---|
| 566 | /* set up the segment registers */ |
---|
| 567 | " li %6, 0\n" |
---|
| 568 | "1: mtsrin %1, %6\n" |
---|
| 569 | " addis %6, %6, 0x1000\n" /* address next SR */ |
---|
| 570 | " addi %1, %1, 1\n" /* increment VSID */ |
---|
| 571 | " bdnz 1b\n" |
---|
| 572 | /* Now flush all TLBs, starting with the topmost index */ |
---|
| 573 | " lis %6, %2@h\n" |
---|
| 574 | "2: addic. %6, %6, -%3\n" /* address the next one (decrementing) */ |
---|
| 575 | " tlbie %6\n" /* invalidate & repeat */ |
---|
| 576 | " bgt 2b\n" |
---|
| 577 | " tlbsync\n" |
---|
| 578 | " sync\n" |
---|
| 579 | /* set up SDR1 */ |
---|
| 580 | " mtspr %4, %5\n" |
---|
| 581 | /* restore original MSR */ |
---|
| 582 | " mtmsr %0\n" |
---|
| 583 | " isync \n" |
---|
| 584 | ::"r"(16), "b"(KEY_USR | KEY_SUP), |
---|
| 585 | "i"(FLUSH_EA_RANGE), "i"(1<<LD_PG_SIZE), |
---|
| 586 | "i"(SDR1), "r"(sdr1), |
---|
| 587 | "b"(MSR_EE | MSR_IR | MSR_DR) |
---|
| 588 | : "ctr","cc"); |
---|
| 589 | |
---|
| 590 | /* At this point, BAT0 is probably still active; it's the |
---|
| 591 | * caller's job to deactivate it... |
---|
| 592 | */ |
---|
| 593 | #endif |
---|
| 594 | } |
---|
| 595 | |
---|
| 596 | /************************** DEBUGGING ROUTINES *************************/ |
---|
| 597 | |
---|
| 598 | /* Exception handler to catch page faults */ |
---|
| 599 | #ifdef DEBUG_EXC |
---|
| 600 | |
---|
| 601 | #define BAT_VALID_BOTH 3 /* allow user + super access */ |
---|
| 602 | |
---|
| 603 | static void |
---|
| 604 | myhdl(BSP_Exception_frame* excPtr) |
---|
| 605 | { |
---|
| 606 | if (3==excPtr->_EXC_number) { |
---|
| 607 | unsigned long dsisr; |
---|
| 608 | |
---|
| 609 | /* reactivate DBAT0 and read DSISR */ |
---|
| 610 | __asm__ __volatile__( |
---|
| 611 | "mfspr %0, %1\n" |
---|
| 612 | "ori %0,%0,3\n" |
---|
| 613 | "mtspr %1, %0\n" |
---|
| 614 | "sync\n" |
---|
| 615 | "mfspr %0, %2\n" |
---|
| 616 | :"=r"(dsisr) |
---|
| 617 | :"i"(DBAT0U),"i"(DSISR),"i"(BAT_VALID_BOTH) |
---|
| 618 | ); |
---|
| 619 | |
---|
| 620 | printk("Data Access Exception (DSI) # 3\n"); |
---|
| 621 | printk("Reactivated DBAT0 mapping\n"); |
---|
| 622 | |
---|
| 623 | |
---|
| 624 | printk("DSISR 0x%08x\n",dsisr); |
---|
| 625 | |
---|
| 626 | printk("revectoring to prevent default handler panic().\n"); |
---|
| 627 | printk("NOTE: exception number %i below is BOGUS\n", |
---|
| 628 | ASM_DEC_VECTOR); |
---|
| 629 | /* make this exception 'recoverable' for |
---|
| 630 | * the default handler by faking a decrementer |
---|
| 631 | * exception. |
---|
| 632 | * Note that the default handler's message will be |
---|
| 633 | * wrong about the exception number. |
---|
| 634 | */ |
---|
| 635 | excPtr->_EXC_number = ASM_DEC_VECTOR; |
---|
| 636 | } |
---|
| 637 | /* now call the original handler */ |
---|
| 638 | ((void(*)())ohdl)(excPtr); |
---|
| 639 | } |
---|
| 640 | #endif |
---|
| 641 | |
---|
| 642 | |
---|
| 643 | #ifdef DEBUG |
---|
| 644 | |
---|
| 645 | /* test the consistency of the page table |
---|
| 646 | * |
---|
| 647 | * 'pass' is merely a number which will be printed |
---|
| 648 | * by this routine, so the caller may give some |
---|
| 649 | * context information. |
---|
| 650 | * |
---|
| 651 | * 'expected' is the number of valid (plus 'marked') |
---|
| 652 | * entries the caller believes the page table should |
---|
| 653 | * have. This routine complains if its count differs. |
---|
| 654 | * |
---|
| 655 | * It basically verifies that the topmost 20bits |
---|
| 656 | * of all VSIDs as well as the unused bits are all |
---|
| 657 | * zero. Then it counts all valid and all 'marked' |
---|
| 658 | * entries, adding them up and comparing them to the |
---|
| 659 | * 'expected' number of occupied slots. |
---|
| 660 | * |
---|
| 661 | * RETURNS: total number of valid plus 'marked' slots. |
---|
| 662 | */ |
---|
| 663 | unsigned long |
---|
| 664 | triv121PgTblConsistency(Triv121PgTbl pt, int pass, int expected) |
---|
| 665 | { |
---|
| 666 | PTE pte; |
---|
| 667 | int i; |
---|
| 668 | unsigned v,m; |
---|
| 669 | int warn=0; |
---|
| 670 | static int maxw=20; /* mute after detecting this many errors */ |
---|
| 671 | |
---|
| 672 | PRINTF("Checking page table at 0x%08x (size %i==0x%x)\n", |
---|
| 673 | (unsigned)pt->base, (unsigned)pt->size, (unsigned)pt->size); |
---|
| 674 | |
---|
| 675 | if (!pt->base || !pt->size) { |
---|
| 676 | PRINTF("Uninitialized Page Table!\n"); |
---|
| 677 | return 0; |
---|
| 678 | } |
---|
| 679 | |
---|
| 680 | v=m=0; |
---|
[d49389a] | 681 | #if 1 |
---|
| 682 | /* 10/9/2002: I had machine checks crashing after this loop |
---|
| 683 | * terminated. Maybe caused by speculative loads |
---|
| 684 | * from beyond the valid memory area (since the |
---|
| 685 | * page hash table sits at the top of physical |
---|
| 686 | * memory). |
---|
| 687 | * Very bizarre - the other loops in this file |
---|
| 688 | * seem to be fine. Maybe there is a compiler bug?? |
---|
| 689 | * For the moment, I let the loop run backwards... |
---|
| 690 | * |
---|
| 691 | * Also see the comment a couple of lines down. |
---|
| 692 | */ |
---|
| 693 | for (i=pt->size/sizeof(PTERec)-1, pte=pt->base + i; i>=0; i--,pte--) |
---|
| 694 | #else |
---|
| 695 | for (i=0, pte=pt->base; i<pt->size/sizeof(PTERec); i++,pte++) |
---|
| 696 | #endif |
---|
| 697 | { |
---|
[11f894cc] | 698 | int err=0; |
---|
| 699 | char buf[500]; |
---|
| 700 | unsigned long *lp=(unsigned long*)pte; |
---|
[d49389a] | 701 | #if 0 |
---|
| 702 | /* If I put this bogus while statement here (the body is |
---|
| 703 | * never reached), the original loop works OK |
---|
| 704 | */ |
---|
| 705 | while (pte >= pt->base + pt->size/sizeof(PTERec)) |
---|
| 706 | /* never reached */; |
---|
| 707 | #endif |
---|
| 708 | |
---|
[11f894cc] | 709 | if ( (*lp & (0xfffff0<<7)) || *(lp+1) & 0xe00 || (pte->v && pte->marked)) { |
---|
| 710 | /* check for vsid (without segment bits) == 0, unused bits == 0, valid && marked */ |
---|
| 711 | sprintf(buf,"invalid VSID , unused bits or v && m"); |
---|
| 712 | err=1; |
---|
| 713 | } else { |
---|
| 714 | if (pte->v) v++; |
---|
| 715 | if (pte->marked) m++; |
---|
| 716 | } |
---|
| 717 | if (err && maxw) { |
---|
| 718 | PRINTF("Pass %i -- strange PTE at 0x%08x found for page index %i == 0x%08x:\n", |
---|
| 719 | pass,(unsigned)pte,i,i); |
---|
| 720 | PRINTF("Reason: %s\n",buf); |
---|
| 721 | dumpPte(pte); |
---|
| 722 | warn++; |
---|
| 723 | maxw--; |
---|
| 724 | } |
---|
| 725 | } |
---|
| 726 | if (warn) { |
---|
| 727 | PRINTF("%i errors found; currently %i entries marked, %i are valid\n", |
---|
| 728 | warn, m, v); |
---|
| 729 | } |
---|
| 730 | v+=m; |
---|
| 731 | if (maxw && expected>=0 && expected != v) { |
---|
| 732 | /* number of occupied slots not what they expected */ |
---|
| 733 | PRINTF("Wrong # of occupied slots detected during pass"); |
---|
| 734 | PRINTF("%i; should be %i (0x%x) is %i (0x%x)\n", |
---|
| 735 | pass, expected, (unsigned)expected, v, (unsigned)v); |
---|
| 736 | maxw--; |
---|
| 737 | } |
---|
| 738 | return v; |
---|
| 739 | } |
---|
| 740 | |
---|
| 741 | /* Find the PTE for a EA and print its contents |
---|
| 742 | * RETURNS: pte for EA or NULL if no entry was found. |
---|
| 743 | */ |
---|
| 744 | PTE |
---|
| 745 | triv121DumpPte(unsigned long ea) |
---|
| 746 | { |
---|
| 747 | PTE pte; |
---|
| 748 | |
---|
| 749 | pte=alreadyMapped(&pgTbl,TRIV121_121_VSID,ea); |
---|
| 750 | |
---|
| 751 | if (pte) |
---|
| 752 | dumpPte(pte); |
---|
| 753 | return pte; |
---|
| 754 | } |
---|
| 755 | |
---|
| 756 | /* Dump an entire PTEG */ |
---|
| 757 | |
---|
| 758 | static void |
---|
| 759 | dumpPteg(unsigned long vsid, unsigned long pi, unsigned long hash) |
---|
| 760 | { |
---|
| 761 | PTE pte=ptegOf(&pgTbl,hash); |
---|
| 762 | int i; |
---|
| 763 | PRINTF("hash 0x%08x, pteg 0x%08x (vsid 0x%08x, pi 0x%08x)\n", |
---|
| 764 | (unsigned)hash, (unsigned)pte, |
---|
| 765 | (unsigned)vsid, (unsigned)pi); |
---|
| 766 | for (i=0; i<PTE_PER_PTEG; i++,pte++) { |
---|
| 767 | PRINTF("pte 0x%08x is 0x%08x : 0x%08x\n", |
---|
| 768 | (unsigned)pte, |
---|
| 769 | (unsigned)*(unsigned long*)pte, |
---|
| 770 | (unsigned)*(((unsigned long*)pte)+1)); |
---|
| 771 | } |
---|
| 772 | } |
---|
| 773 | |
---|
| 774 | /* Verify that a range of EAs is mapped the page table |
---|
| 775 | * |
---|
| 776 | * RETURNS: address of the first page for which no |
---|
| 777 | * PTE was found (i.e. page index * page size) |
---|
| 778 | * |
---|
| 779 | * ON SUCCESS, the special value 0x0C0C ("OKOK") |
---|
| 780 | * [which is not page aligned and hence is not |
---|
| 781 | * a valid page address]. |
---|
| 782 | */ |
---|
| 783 | unsigned long |
---|
| 784 | triv121IsRangeMapped(unsigned long start, unsigned long end) |
---|
| 785 | { |
---|
| 786 | start&=~((1<<LD_PG_SIZE)-1); |
---|
| 787 | while (start < end) { |
---|
| 788 | if (!alreadyMapped(&pgTbl,TRIV121_121_VSID,start)) |
---|
| 789 | return start; |
---|
| 790 | start+=1<<LD_PG_SIZE; |
---|
| 791 | } |
---|
| 792 | return 0x0C0C; /* OKOK - not on a page boundary */ |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | #endif |
---|
| 796 | |
---|
| 797 | |
---|
| 798 | #if defined(DEBUG_MAIN) || defined(DEBUG) |
---|
| 799 | #include <stdlib.h> |
---|
| 800 | |
---|
| 801 | /* print a PTE */ |
---|
| 802 | static void |
---|
| 803 | dumpPte(PTE pte) |
---|
| 804 | { |
---|
| 805 | if (0==((unsigned long)pte & ((1<<LD_PTEG_SIZE)-1))) |
---|
| 806 | PRINTF("PTEG--"); |
---|
| 807 | else |
---|
| 808 | PRINTF("......"); |
---|
| 809 | if (pte->v) { |
---|
| 810 | PRINTF("VSID: 0x%08x H:%1i API: 0x%02x\n", |
---|
| 811 | pte->vsid, pte->h, pte->api); |
---|
| 812 | PRINTF(" "); |
---|
| 813 | PRINTF("RPN: 0x%08x WIMG: 0x%1x, (m %1i), pp: 0x%1x\n", |
---|
| 814 | pte->rpn, pte->wimg, pte->marked, pte->pp); |
---|
| 815 | } else { |
---|
| 816 | PRINTF("xxxxxx\n"); |
---|
| 817 | PRINTF(" "); |
---|
| 818 | PRINTF("xxxxxx\n"); |
---|
| 819 | } |
---|
| 820 | } |
---|
| 821 | |
---|
| 822 | |
---|
| 823 | /* dump page table entries from index 'from' to 'to' |
---|
| 824 | * The special values (unsigned)-1 are allowed which |
---|
| 825 | * cause the routine to dump the entire table. |
---|
| 826 | * |
---|
| 827 | * RETURNS 0 |
---|
| 828 | */ |
---|
| 829 | int |
---|
| 830 | triv121PgTblDump(Triv121PgTbl pt, unsigned from, unsigned to) |
---|
| 831 | { |
---|
| 832 | int i; |
---|
| 833 | PTE pte; |
---|
| 834 | PRINTF("Dumping PT [size 0x%08x == %i] at 0x%08x\n", |
---|
| 835 | (unsigned)pt->size, (unsigned)pt->size, (unsigned)pt->base); |
---|
| 836 | if (from> pt->size>>LD_PTE_SIZE) |
---|
| 837 | from=0; |
---|
| 838 | if (to > pt->size>>LD_PTE_SIZE) |
---|
| 839 | to=(pt->size>>LD_PTE_SIZE); |
---|
| 840 | for (i=from,pte=pt->base+from; i<(long)to; i++, pte++) { |
---|
| 841 | dumpPte(pte); |
---|
| 842 | } |
---|
| 843 | return 0; |
---|
| 844 | } |
---|
| 845 | |
---|
| 846 | |
---|
| 847 | #if defined(DEBUG_MAIN) |
---|
| 848 | |
---|
| 849 | #define LD_DBG_PT_SIZE LD_MIN_PT_SIZE |
---|
| 850 | |
---|
| 851 | int |
---|
| 852 | main(int argc, char **argv) |
---|
| 853 | { |
---|
| 854 | unsigned long base,start,numPages; |
---|
| 855 | unsigned long size=1<<LD_DBG_PT_SIZE; |
---|
| 856 | Triv121PgTbl pt; |
---|
| 857 | |
---|
| 858 | base=(unsigned long)malloc(size<<1); |
---|
| 859 | |
---|
| 860 | assert(base); |
---|
| 861 | |
---|
| 862 | /* align pt */ |
---|
| 863 | base += size-1; |
---|
| 864 | base &= ~(size-1); |
---|
| 865 | |
---|
| 866 | assert(pt=triv121PgTblInit(base,LD_DBG_PT_SIZE)); |
---|
| 867 | |
---|
| 868 | triv121PgTblDump(pt,(unsigned)-1, (unsigned)-1); |
---|
| 869 | do { |
---|
| 870 | do { |
---|
| 871 | PRINTF("Start Address:"); fflush(stdout); |
---|
| 872 | } while (1!=scanf("%i",&start)); |
---|
| 873 | do { |
---|
| 874 | PRINTF("# pages:"); fflush(stdout); |
---|
| 875 | } while (1!=scanf("%i",&numPages)); |
---|
| 876 | } while (TRIV121_MAP_SUCCESS==triv121PgTblMap(pt,TRIV121_121_VSID,start,numPages, |
---|
| 877 | TRIV121_ATTR_IO_PAGE,2) && |
---|
| 878 | 0==triv121PgTblDump(pt,(unsigned)-1,(unsigned)-1)); |
---|
| 879 | } |
---|
| 880 | #endif |
---|
| 881 | #endif |
---|