| 1 | /* |
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| 2 | * mmuAsm.S |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 5 | * |
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| 6 | * This file contains the low-level support for various MMU |
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| 7 | * features. |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.rtems.org/license/LICENSE. |
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| 12 | * |
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| 13 | * T. Straumann - 11/2001: added support for 7400 (no AltiVec yet) |
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| 14 | * S.K. Feng - 10/2003: added support for 7455 (no AltiVec yet) |
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| 15 | * |
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| 16 | */ |
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| 17 | |
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| 18 | #include <rtems/asm.h> |
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| 19 | #include <rtems/score/cpu.h> |
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| 20 | #include <libcpu/io.h> |
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| 21 | #include <libcpu/bat.h> |
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| 22 | |
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| 23 | /* Unfortunately, the CPU types defined in cpu.h are |
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| 24 | * an 'enum' type and hence not available :-( |
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| 25 | */ |
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| 26 | #define PPC_601 0x1 |
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| 27 | #define PPC_603 0x3 |
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| 28 | #define PPC_604 0x4 |
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| 29 | #define PPC_603e 0x6 |
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| 30 | #define PPC_603ev 0x7 |
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| 31 | #define PPC_750 0x8 |
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| 32 | #define PPC_604e 0x9 |
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| 33 | #define PPC_604r 0xA |
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| 34 | #define PPC_7400 0xC |
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| 35 | #define PPC_7455 0x8001 |
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| 36 | #define PPC_7457 0x8002 |
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| 37 | #define PPC_620 0x16 |
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| 38 | #define PPC_860 0x50 |
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| 39 | #define PPC_821 PPC_860 |
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| 40 | #define PPC_8260 0x81 |
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| 41 | #define PPC_8240 PPC_8260 |
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| 42 | |
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| 43 | /* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */ |
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| 44 | #define DSSALL .long 0x7e00066c /* DSSALL altivec instruction opcode */ |
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| 45 | |
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| 46 | /* A couple of defines to make the code more readable */ |
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| 47 | #define CACHE_LINE_SIZE 32 |
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| 48 | |
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| 49 | #ifndef MSSCR0 |
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| 50 | #define MSSCR0 1014 |
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| 51 | #endif |
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| 52 | |
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| 53 | #define DL1HWF (1<<(31-8)) |
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| 54 | #define L2HWF (1<<(31-20)) |
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| 55 | |
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| 56 | #FIXME Should really move this to C code |
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| 57 | |
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| 58 | .globl L1_caches_enables |
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| 59 | .type L1_caches_enables, @function |
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| 60 | |
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| 61 | L1_caches_enables: |
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| 62 | /* |
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| 63 | * Enable caches and 604-specific features if necessary. |
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| 64 | */ |
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| 65 | mfspr r9,PPC_PVR |
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| 66 | rlwinm r9,r9,16,16,31 |
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| 67 | cmpi 0,r9,PPC_601 |
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| 68 | beq 4f /* not needed for 601 */ |
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| 69 | mfspr r11,HID0 |
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| 70 | andi. r0,r11,HID0_DCE |
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| 71 | ori r11,r11,HID0_ICE|HID0_DCE |
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| 72 | ori r8,r11,HID0_ICFI |
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| 73 | bne 3f /* don't invalidate the D-cache */ |
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| 74 | ori r8,r8,HID0_DCI /* unless it wasn't enabled */ |
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| 75 | 3: |
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| 76 | sync |
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| 77 | mtspr HID0,r8 /* enable and invalidate caches */ |
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| 78 | sync |
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| 79 | mtspr HID0,r11 /* enable caches */ |
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| 80 | sync |
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| 81 | isync |
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| 82 | cmpi 1,r9,PPC_604 /* check for 604 */ |
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| 83 | cmpi 2,r9,PPC_604e /* or 604e */ |
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| 84 | cmpi 3,r9,PPC_604r /* or mach5 */ |
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| 85 | cror 6,6,10 |
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| 86 | cror 6,6,14 |
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| 87 | cmpi 2,r9,PPC_750 /* or 750 */ |
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| 88 | cror 6,6,10 |
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| 89 | cmpi 2,r9,PPC_7400 /* or 7400 */ |
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| 90 | cror 6,6,10 |
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| 91 | cmpli 0,r9,PPC_7455 /* or 7455 */ |
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| 92 | beq 1f |
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| 93 | cmpli 0,r9,PPC_7457 /* or 7457 */ |
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| 94 | bne 2f |
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| 95 | 1: |
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| 96 | /* 7455:link register stack,branch folding & |
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| 97 | * TBEN : enable the time base and decrementer. |
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| 98 | * EMCP bit is defined in HID1. However, it's not used |
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| 99 | * in mvme5500 board because of GT64260 (e.g. it's connected |
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| 100 | * pull-up). |
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| 101 | */ |
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| 102 | oris r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@h |
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| 103 | ori r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@l |
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| 104 | 2: cror 2,2,10 |
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| 105 | bne 3f |
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| 106 | ori r11,r11,HID0_BTIC /* enable branch tgt cache on 7400 , 7455 , 7457 */ |
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| 107 | 3: cror 2,2,6 |
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| 108 | bne 4f |
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| 109 | /* on 7400 SIED is actually SGE (store gathering enable) */ |
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| 110 | ori r11,r11,HID0_SIED|HID0_BHTE /* for 604[e], enable */ |
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| 111 | bne 2,5f |
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| 112 | ori r11,r11,HID0_BTCD |
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| 113 | 5: mtspr HID0,r11 /* superscalar exec & br history tbl */ |
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| 114 | sync /* for SGE bit */ |
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| 115 | isync /* P2-17 to 2-22 in MPC7450UM */ |
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| 116 | 4: |
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| 117 | blr |
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| 118 | |
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| 119 | .globl get_L1CR |
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| 120 | .type get_L1CR, @function |
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| 121 | get_L1CR: |
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| 122 | mfspr r3,HID0 |
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| 123 | blr |
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| 124 | |
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| 125 | .globl get_L2CR |
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| 126 | .type get_L2CR, @function |
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| 127 | get_L2CR: |
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| 128 | /* Make sure this is a > 750 chip */ |
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| 129 | mfspr r3,PPC_PVR |
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| 130 | rlwinm r3,r3,16,16,31 |
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| 131 | cmplwi r3,PPC_750 /* it's a 750 */ |
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| 132 | beq 1f |
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| 133 | cmplwi r3,PPC_7400 /* it's a 7400 */ |
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| 134 | beq 1f |
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| 135 | cmplwi r3,PPC_7455 /* it's a 7455 */ |
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| 136 | beq 1f |
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| 137 | cmplwi r3,PPC_7457 /* it's a 7457 */ |
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| 138 | beq 1f |
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| 139 | li r3,-1 |
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| 140 | blr |
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| 141 | |
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| 142 | 1: |
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| 143 | /* Return the L2CR contents */ |
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| 144 | mfspr r3,L2CR |
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| 145 | blr |
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| 146 | |
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| 147 | .globl set_L2CR |
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| 148 | .type set_L2CR, @function |
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| 149 | set_L2CR: |
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| 150 | /* Usage: |
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| 151 | * When setting the L2CR register, you must do a few special things. |
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| 152 | * If you are enabling the cache, you must perform a global invalidate. |
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| 153 | * If you are disabling the cache, you must flush the cache contents first. |
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| 154 | * This routine takes care of doing these things. When first |
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| 155 | * enabling the cache, make sure you pass in the L2CR you want, as well as |
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| 156 | * passing in the global invalidate bit set. A global invalidate will |
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| 157 | * only be performed if the L2I bit is set in applyThis. When enabling |
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| 158 | * the cache, you should also set the L2E bit in applyThis. If you |
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| 159 | * want to modify the L2CR contents after the cache has been enabled, |
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| 160 | * the recommended procedure is to first call __setL2CR(0) to disable |
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| 161 | * the cache and then call it again with the new values for L2CR. Examples: |
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| 162 | * |
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| 163 | * _setL2CR(0) - disables the cache |
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| 164 | * _setL2CR(0xb9A14000) - enables my G3 MCP750 card: |
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| 165 | * - L2E set to turn on the cache |
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| 166 | * - L2SIZ set to 1MB |
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| 167 | * - L2CLK set to %2 |
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| 168 | * - L2RAM set to pipelined syncronous late-write |
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| 169 | * - L2I set to perform a global invalidation |
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| 170 | * - L2OH set to 1 nS |
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| 171 | * |
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| 172 | * A similar call should work for your card. You need to know the correct |
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| 173 | * setting for your card and then place them in the fields I have outlined |
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| 174 | * above. Other fields support optional features, such as L2DO which caches |
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| 175 | * only data, or L2TS which causes cache pushes from the L1 cache to go to |
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| 176 | *the L2 cache instead of to main memory. |
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| 177 | */ |
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| 178 | |
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| 179 | /* Make sure this is a > 750 chip */ |
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| 180 | mfspr r0,PPC_PVR |
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| 181 | rlwinm r0,r0,16,16,31 |
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| 182 | cmplwi r0,PPC_750 |
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| 183 | beq thisIs750 |
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| 184 | cmplwi r0,PPC_7400 |
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| 185 | beq thisIs750 |
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| 186 | cmplwi r0,PPC_7455 |
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| 187 | beq thisIs750 |
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| 188 | cmplwi r0,PPC_7457 |
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| 189 | beq thisIs750 |
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| 190 | li r3,-1 |
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| 191 | blr |
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| 192 | |
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| 193 | thisIs750: |
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| 194 | /* Get the current enable bit of the L2CR into r4 */ |
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| 195 | mfspr r4,L2CR |
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| 196 | rlwinm r4,r4,0,0,0 |
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| 197 | |
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| 198 | /* See if we want to perform a global inval this time. */ |
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| 199 | rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ |
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| 200 | rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ |
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| 201 | rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ |
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| 202 | rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ |
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| 203 | or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ |
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| 204 | mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ |
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| 205 | rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing |
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| 206 | the cache is fatal (comment this line and see!) */ |
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| 207 | mtmsr r4 |
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| 208 | bne dontDisableCache /* Only disable the cache if L2CRApply has the enable bit off */ |
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| 209 | |
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| 210 | cmplwi r0,PPC_7400 /* 7400 ? */ |
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| 211 | bne disableCache /* use traditional method */ |
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| 212 | |
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| 213 | /* On the 7400, they recommend using the hardware flush feature */ |
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| 214 | DSSALL /* stop all data streams */ |
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| 215 | sync |
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| 216 | /* we wouldn't have to flush L1, but for sake of consistency with the other code we do it anyway */ |
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| 217 | mfspr r4, MSSCR0 |
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| 218 | oris r4, r4, DL1HWF@h |
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| 219 | mtspr MSSCR0, r4 |
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| 220 | sync |
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| 221 | /* L1 flushed */ |
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| 222 | mfspr r4, L2CR |
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| 223 | ori r4, r4, L2HWF |
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| 224 | mtspr L2CR, r4 |
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| 225 | sync |
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| 226 | /* L2 flushed */ |
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| 227 | b flushDone |
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| 228 | |
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| 229 | disableCache: |
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| 230 | /* Disable the cache. First, we turn off data relocation. */ |
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| 231 | rlwinm r4,r4,0,28,26 /* Turn off DR bit */ |
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| 232 | cmplwi r0,PPC_7455 /* 7455 ? */ |
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| 233 | beq 1f |
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| 234 | cmplwi r0,PPC_7457 /* 7457 ? */ |
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| 235 | bne not745x |
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| 236 | 1: |
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| 237 | /* 745x:L1 Load/Flush, L2, L3 : hardware flush */ |
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| 238 | DSSALL |
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| 239 | mtmsr r4 |
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| 240 | sync |
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| 241 | isync |
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| 242 | mfspr r4, MSSCR0 |
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| 243 | rlwinm r4,r4,0,29,0 /* Turn off the L2PFE bits */ |
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| 244 | mtspr MSSCR0, r4 |
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| 245 | sync |
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| 246 | /* flush L1 first */ |
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| 247 | lis r4,0x0001 |
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| 248 | mtctr r4 |
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| 249 | li r4,0 |
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| 250 | li r0,0 |
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| 251 | loadFlush: |
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| 252 | lwzx r0,r0,r4 |
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| 253 | dcbf r0,r4 |
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| 254 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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| 255 | bdnz loadFlush |
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| 256 | sync |
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| 257 | /* Set the L2CR[L2IO & L2DO] bits to completely lock the L2 cache */ |
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| 258 | mfspr r0, L2CR |
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| 259 | lis r4,L2CR_LOCK_745x@h |
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| 260 | ori r4,r4,L2CR_LOCK_745x@l |
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| 261 | or r4,r0,r4 |
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| 262 | rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ |
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| 263 | mtspr L2CR, r4 |
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| 264 | sync |
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| 265 | ori r4, r4, L2HWF |
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| 266 | mtspr L2CR, r4 |
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| 267 | sync |
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| 268 | /* L2 flushed,L2IO & L2DO got cleared in the dontDisableCache: */ |
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| 269 | b reenableDR |
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| 270 | |
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| 271 | not745x: |
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| 272 | sync |
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| 273 | mtmsr r4 |
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| 274 | isync |
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| 275 | /* |
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| 276 | Now, read the first 2MB of memory to put new data in the cache. |
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| 277 | (Actually we only need the size of the L2 cache plus |
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| 278 | the size of the L1 cache, but 2MB will cover everything just to be safe). |
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| 279 | */ |
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| 280 | lis r4,0x0001 |
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| 281 | mtctr r4 |
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| 282 | li r4,0 |
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| 283 | loadLoop: |
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| 284 | lwzx r0,r0,r4 |
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| 285 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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| 286 | bdnz loadLoop |
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| 287 | |
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| 288 | /* Now, flush the first 2MB of memory */ |
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| 289 | lis r4,0x0001 |
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| 290 | mtctr r4 |
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| 291 | li r4,0 |
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| 292 | sync |
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| 293 | flushLoop: |
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| 294 | dcbf r0,r4 |
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| 295 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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| 296 | bdnz flushLoop |
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| 297 | reenableDR: |
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| 298 | rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ |
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| 299 | sync |
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| 300 | mtmsr r4 |
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| 301 | isync |
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| 302 | |
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| 303 | flushDone: |
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| 304 | |
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| 305 | /* Turn off the L2CR enable bit. */ |
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| 306 | rlwinm r3,r3,0,1,31 |
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| 307 | |
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| 308 | dontDisableCache: |
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| 309 | /* Set up the L2CR configuration bits */ |
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| 310 | sync |
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| 311 | mtspr L2CR,r3 |
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| 312 | sync |
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| 313 | cmplwi r6,0 |
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| 314 | beq noInval |
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| 315 | |
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| 316 | /* Perform a global invalidation */ |
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| 317 | oris r3,r3,0x0020 |
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| 318 | sync |
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| 319 | mtspr L2CR,r3 |
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| 320 | sync |
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| 321 | invalCompleteLoop: /* Wait for the invalidation to complete */ |
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| 322 | mfspr r3,L2CR |
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| 323 | rlwinm. r4,r3,0,31,31 |
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| 324 | bne invalCompleteLoop |
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| 325 | |
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| 326 | rlwinm r3,r3,0,11,9; /* Turn off the L2I bit */ |
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| 327 | sync |
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| 328 | mtspr L2CR,r3 |
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| 329 | |
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| 330 | noInval: |
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| 331 | sync |
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| 332 | /* re-enable interrupts, i.e. restore original MSR */ |
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| 333 | mtmsr r7 /* (no sync needed) */ |
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| 334 | /* See if we need to enable the cache */ |
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| 335 | cmplwi r5,0 |
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| 336 | beqlr |
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| 337 | |
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| 338 | enableCache: |
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| 339 | /* Enable the cache */ |
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| 340 | oris r3,r3,0x8000 |
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| 341 | mtspr L2CR,r3 |
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| 342 | sync |
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| 343 | blr |
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| 344 | |
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| 345 | |
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| 346 | .globl get_L3CR |
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| 347 | .type get_L3CR, @function |
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| 348 | get_L3CR: |
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| 349 | /* Make sure this is a 7455 chip */ |
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| 350 | mfspr r3,PPC_PVR |
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| 351 | rlwinm r3,r3,16,16,31 |
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| 352 | cmplwi r3,PPC_7455 /* it's a 7455 */ |
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| 353 | beq 1f |
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| 354 | cmplwi r3,PPC_7457 /* it's a 7457 */ |
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| 355 | beq 1f |
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| 356 | li r3,-1 |
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| 357 | blr |
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| 358 | |
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| 359 | 1: |
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| 360 | /* Return the L3CR contents */ |
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| 361 | mfspr r3,L3CR |
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| 362 | blr |
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| 363 | |
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| 364 | .globl set_L3CR |
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| 365 | .type set_L3CR, @function |
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| 366 | set_L3CR: |
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| 367 | /* Usage: |
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| 368 | * When setting the L3CR register, you must do a few special things. |
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| 369 | * If you are enabling the cache, you must perform a global invalidate. |
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| 370 | * Then call cpu_enable_l3cr(l3cr). |
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| 371 | * If you are disabling the cache, you must flush the cache contents first. |
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| 372 | * This routine takes care of doing these things. If you |
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| 373 | * want to modify the L3CR contents after the cache has been enabled, |
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| 374 | * the recommended procedure is to first call __setL3CR(0) to disable |
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| 375 | * the cache and then call cpu_enable_l3cr with the new values for |
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| 376 | * L3CR. |
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| 377 | */ |
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| 378 | |
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| 379 | /* Make sure this is a 7455 chip */ |
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| 380 | mfspr r0,PPC_PVR |
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| 381 | rlwinm r0,r0,16,16,31 |
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| 382 | cmplwi r0,PPC_7455 |
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| 383 | beq thisIs7455 |
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| 384 | cmplwi r0,PPC_7457 |
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| 385 | beq thisIs7455 |
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| 386 | li r3,-1 |
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| 387 | blr |
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| 388 | |
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| 389 | thisIs7455: |
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| 390 | /* Get the current enable bit of the L3CR into r4 */ |
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| 391 | mfspr r4,L3CR |
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| 392 | rlwinm r4,r4,0,0,0 |
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| 393 | |
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| 394 | /* See if we want to perform a global inval this time. */ |
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| 395 | rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ |
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| 396 | rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ |
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| 397 | rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ |
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| 398 | rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ |
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| 399 | or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ |
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| 400 | mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ |
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| 401 | rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing |
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| 402 | the cache is fatal (comment this line and see!) */ |
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| 403 | mtmsr r4 |
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| 404 | bne dontDisableL3Cache /* Only disable the cache if L3CRApply has the enable bit off */ |
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| 405 | /* Before the L3 is disabled, it must be flused to prevent coherency problems */ |
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| 406 | /* First, we turn off data relocation. */ |
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| 407 | rlwinm r4,r4,0,28,26 /* Turn off DR bit */ |
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| 408 | DSSALL |
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| 409 | sync |
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| 410 | mtmsr r4 |
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| 411 | isync /* make sure memory accesses have completed */ |
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| 412 | /* 7455: L3 : hardware flush |
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| 413 | * Set the L3CR[L3IO & L3DO] bits to completely lock the L3 cache */ |
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| 414 | mfspr r0, L3CR |
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| 415 | lis r4, L3CR_LOCK_745x@h |
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| 416 | ori r4,r4, L3CR_LOCK_745x@l |
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| 417 | or r4,r0,r4 |
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| 418 | rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ |
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| 419 | mtspr L3CR, r4 |
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| 420 | sync |
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| 421 | ori r4, r4, L3CR_L3HWF |
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| 422 | mtspr L3CR, r4 |
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| 423 | sync |
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| 424 | /* L3 flushed,L3IO & L3DO got cleared in the dontDisableL3Cache: */ |
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| 425 | rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ |
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| 426 | sync |
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| 427 | mtmsr r4 |
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| 428 | isync |
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| 429 | |
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| 430 | /* Turn off the L3CR enable bit. */ |
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| 431 | rlwinm r3,r3,0,1,31 |
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| 432 | |
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| 433 | dontDisableL3Cache: |
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| 434 | /* Set up the L3CR configuration bits */ |
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| 435 | sync |
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| 436 | mtspr L3CR,r3 |
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| 437 | sync |
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| 438 | ifL3Inval: |
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| 439 | cmplwi r6,0 |
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| 440 | beq noL3Inval |
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| 441 | |
|---|
| 442 | /* Perform a global invalidation */ |
|---|
| 443 | oris r3,r3,0x0020 |
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| 444 | sync |
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| 445 | mtspr L3CR,r3 |
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| 446 | sync |
|---|
| 447 | invalCompleteL3: /* Wait for the invalidation to complete */ |
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| 448 | mfspr r3,L3CR |
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| 449 | rlwinm. r4,r3,0,31,31 |
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| 450 | bne invalCompleteL3 |
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| 451 | |
|---|
| 452 | rlwinm r3,r3,0,11,9; /* Turn off the L3I bit */ |
|---|
| 453 | sync |
|---|
| 454 | mtspr L3CR,r3 |
|---|
| 455 | sync |
|---|
| 456 | |
|---|
| 457 | noL3Inval: |
|---|
| 458 | /* re-enable interrupts, i.e. restore original MSR */ |
|---|
| 459 | mtmsr r7 /* (no sync needed) */ |
|---|
| 460 | /* See if we need to enable the cache */ |
|---|
| 461 | cmplwi r5,0 |
|---|
| 462 | beqlr |
|---|
| 463 | |
|---|
| 464 | enableL3Cache: |
|---|
| 465 | /* Enable the cache */ |
|---|
| 466 | oris r3,r3,0x8000 |
|---|
| 467 | mtspr L3CR,r3 |
|---|
| 468 | sync |
|---|
| 469 | blr |
|---|
| 470 | |
|---|
| 471 | /* |
|---|
| 472 | * An undocumented "feature" of 604e requires that the v bit |
|---|
| 473 | * be cleared before changing BAT values. |
|---|
| 474 | * |
|---|
| 475 | * Also, newer IBM firmware does not clear bat3 and 4 so |
|---|
| 476 | * this makes sure it's done. |
|---|
| 477 | * -- Cort |
|---|
| 478 | */ |
|---|
| 479 | .globl CPU_clear_bats_early |
|---|
| 480 | .type CPU_clear_bats_early,@function |
|---|
| 481 | CPU_clear_bats_early: |
|---|
| 482 | li r3,0 |
|---|
| 483 | mfspr r4,PPC_PVR |
|---|
| 484 | rlwinm r4,r4,16,16,31 /* r4 = 1 for 601, 4 for 604 */ |
|---|
| 485 | cmpwi r4, 1 |
|---|
| 486 | sync |
|---|
| 487 | isync |
|---|
| 488 | beq 1f |
|---|
| 489 | cmplwi r4,0x8001 /* 7445, 7455 (0x8001), 7447, 7457 (0x8002) */ |
|---|
| 490 | blt 2f /* 7447a (0x8003) and 7448 (0x8004) have 16 bats */ |
|---|
| 491 | cmplwi r4,0x8004 |
|---|
| 492 | bgt 2f |
|---|
| 493 | mtspr DBAT4U,r3 |
|---|
| 494 | mtspr DBAT4L,r3 |
|---|
| 495 | mtspr DBAT5U,r3 |
|---|
| 496 | mtspr DBAT5L,r3 |
|---|
| 497 | mtspr DBAT6U,r3 |
|---|
| 498 | mtspr DBAT6L,r3 |
|---|
| 499 | mtspr DBAT7U,r3 |
|---|
| 500 | mtspr DBAT7L,r3 |
|---|
| 501 | mtspr IBAT4U,r3 |
|---|
| 502 | mtspr IBAT4L,r3 |
|---|
| 503 | mtspr IBAT5U,r3 |
|---|
| 504 | mtspr IBAT5L,r3 |
|---|
| 505 | mtspr IBAT6U,r3 |
|---|
| 506 | mtspr IBAT6L,r3 |
|---|
| 507 | mtspr IBAT7U,r3 |
|---|
| 508 | mtspr IBAT7L,r3 |
|---|
| 509 | 2: |
|---|
| 510 | mtspr DBAT0U,r3 |
|---|
| 511 | mtspr DBAT0L,r3 |
|---|
| 512 | mtspr DBAT1U,r3 |
|---|
| 513 | mtspr DBAT1L,r3 |
|---|
| 514 | mtspr DBAT2U,r3 |
|---|
| 515 | mtspr DBAT2L,r3 |
|---|
| 516 | mtspr DBAT3U,r3 |
|---|
| 517 | mtspr DBAT3L,r3 |
|---|
| 518 | 1: |
|---|
| 519 | mtspr IBAT0U,r3 |
|---|
| 520 | mtspr IBAT0L,r3 |
|---|
| 521 | mtspr IBAT1U,r3 |
|---|
| 522 | mtspr IBAT1L,r3 |
|---|
| 523 | mtspr IBAT2U,r3 |
|---|
| 524 | mtspr IBAT2L,r3 |
|---|
| 525 | mtspr IBAT3U,r3 |
|---|
| 526 | mtspr IBAT3L,r3 |
|---|
| 527 | sync |
|---|
| 528 | isync |
|---|
| 529 | blr |
|---|
| 530 | |
|---|
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