source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S @ a73a977

4.104.114.84.95
Last change on this file since a73a977 was a73a977, checked in by Joel Sherrill <joel.sherrill@…>, on 04/18/02 at 20:55:37

2002-04-18 Ralf Corsepius <corsepiu@…>

  • shared/include/cpu.h: Removed.
  • shared/include/Makefile.am: Reflect changes above.
  • shared/include/spr.h: Include rtems/powerpc/registers.h instead of libcpu/cpu.h.
  • mpc6xx/clock/c_clock.c: Reflect changes to <rtems/score/cpu.h>.
  • mpc6xx/exceptions/asm_utils.S: Ditto.
  • mpc6xx/exceptions/raw_exception.c: Ditto.
  • mpc6xx/mmu/mmuAsm.S: Ditto.
  • mpc6xx/timer/timer.c: Ditto.
  • mpc8260/exceptions/asm_utils.S: Ditto.
  • mpc8260/exceptions/raw_exception.c: Ditto.
  • mpc8xx/exceptions/asm_utils.S: Ditto.
  • mpc8xx/exceptions/raw_exception.c: Ditto.
  • ppc403/vectors/vectors.S: Include <asm.h> instead of "asm.h".
  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 *  mmuAsm.S
3 *
4 *  $Id$
5 *
6 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
7 *
8 *  This file contains the low-level support for various MMU
9 *  features.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *     
15 */
16
17#include <asm.h>
18#include <rtems/score/cpu.h>
19#include <libcpu/io.h>
20
21/*
22 * Each setdbat routine start by invalidating the DBAT as some
23 * proc (604e) request the valid bit set to 0 before accepting
24 * to write in BAT
25 */
26
27        .globl  asm_setdbat1
28        .type   asm_setdbat1,@function
29asm_setdbat1:
30        li      r20,0
31        SYNC
32        mtspr   DBAT1U,r20
33        mtspr   DBAT1L,r20
34        SYNC
35        mtspr DBAT1L, r4
36        mtspr DBAT1U, r3
37        SYNC
38        blr
39
40        .globl  asm_setdbat2
41        .type   asm_setdbat2,@function
42asm_setdbat2:   
43        li      r20,0
44        SYNC
45        mtspr   DBAT2U,r20
46        mtspr   DBAT2L,r20
47        SYNC
48        mtspr DBAT2L, r4
49        mtspr DBAT2U, r3
50        SYNC
51        blr
52
53        .globl  asm_setdbat3
54        .type   asm_setdbat3,@function
55asm_setdbat3:   
56        li      r20,0
57        SYNC
58        mtspr   DBAT3U,r20
59        mtspr   DBAT3L,r20
60        SYNC
61        mtspr DBAT3L, r4
62        mtspr DBAT3U, r3
63        SYNC
64        blr
65               
66        .globl L1_caches_enables
67        .type  L1_caches_enables, @function
68       
69L1_caches_enables:     
70        /*
71         * Enable caches and 604-specific features if necessary.
72         */
73        mfspr   r9,PVR
74        rlwinm  r9,r9,16,16,31
75        cmpi    0,r9,1
76        beq     4f                      /* not needed for 601 */
77        mfspr   r11,HID0
78        andi.   r0,r11,HID0_DCE
79        ori     r11,r11,HID0_ICE|HID0_DCE
80        ori     r8,r11,HID0_ICFI
81        bne     3f                      /* don't invalidate the D-cache */
82        ori     r8,r8,HID0_DCI          /* unless it wasn't enabled */
833:
84        sync
85        mtspr   HID0,r8                 /* enable and invalidate caches */
86        sync
87        mtspr   HID0,r11                /* enable caches */
88        sync
89        isync
90        cmpi    0,r9,4                  /* check for 604 */
91        cmpi    1,r9,9                  /* or 604e */
92        cmpi    2,r9,10                 /* or mach5 */
93        cror    2,2,6
94        cror    2,2,10
95        bne     4f
96        ori     r11,r11,HID0_SIED|HID0_BHTE /* for 604[e], enable */
97        bne     2,5f
98        ori     r11,r11,HID0_BTCD
995:      mtspr   HID0,r11                /* superscalar exec & br history tbl */
1004:
101        blr
102       
103        .globl get_L2CR
104        .type  get_L2CR, @function     
105get_L2CR:       
106        /* Make sure this is a 750 chip */
107        mfspr   r3,PVR
108        rlwinm  r3,r3,16,16,31
109        cmplwi  r3,0x0008
110        li      r3,0
111        bnelr
112       
113        /* Return the L2CR contents */
114        mfspr   r3,L2CR
115        blr
116
117        .globl set_L2CR
118        .type  set_L2CR, @function
119set_L2CR:       
120        /* Usage:
121         * When setting the L2CR register, you must do a few special things. 
122         * If you are enabling the cache, you must perform a global invalidate.
123         * If you are disabling the cache, you must flush the cache contents first.
124         * This routine takes care of doing these things.  When first
125         * enabling the cache, make sure you pass in the L2CR you want, as well as
126         * passing in the global invalidate bit set.  A global invalidate will
127         * only be performed if the L2I bit is set in applyThis.  When enabling
128         * the cache, you should also set the L2E bit in applyThis.  If you
129         * want to modify the L2CR contents after the cache has been enabled,
130         * the recommended procedure is to first call __setL2CR(0) to disable
131         * the cache and then call it again with the new values for L2CR.  Examples:
132         *
133         *      _setL2CR(0)             -       disables the cache
134         *      _setL2CR(0xb9A14000)    -       enables my G3 MCP750 card:
135         *                              -       L2E set to turn on the cache
136         *                              -       L2SIZ set to 1MB
137         *                              -       L2CLK set to %2
138         *                              -       L2RAM set to pipelined syncronous late-write
139         *                              -       L2I set to perform a global invalidation
140         *                              -       L2OH set to 1 nS
141         *
142         * A similar call should work for your card.  You need to know the correct
143         * setting for your card and then place them in the fields I have outlined
144         * above.  Other fields support optional features, such as L2DO which caches
145         * only data, or L2TS which causes cache pushes from the L1 cache to go to
146         *the L2 cache instead of to main memory.
147         */
148       
149        /* Make sure this is a 750 chip */
150        mfspr   r4,PVR
151        rlwinm  r4,r4,16,16,31
152        cmplwi  r4,0x0008
153        beq     thisIs750
154        li      r3,-1
155        blr
156       
157thisIs750:
158        /* Get the current enable bit of the L2CR into r4 */
159        mfspr   r4,L2CR
160        rlwinm  r4,r4,0,0,0
161       
162        /* See if we want to perform a global inval this time. */
163        rlwinm  r6,r3,0,10,10           /* r6 contains the new invalidate bit */
164        rlwinm. r5,r3,0,0,0             /* r5 contains the new enable bit */
165        rlwinm  r3,r3,0,11,9            /* Turn off the invalidate bit */
166        rlwinm  r3,r3,0,1,31            /* Turn off the enable bit */
167        or      r3,r3,r4                /* Keep the enable bit the same as it was for now. */
168        bne     dontDisableCache        /* Only disable the cache if L2CRApply has the enable bit off */
169
170disableCache:
171        /* Disable the cache.  First, we turn off data relocation. */
172        mfmsr   r7
173        rlwinm  r4,r7,0,28,26           /* Turn off DR bit */
174        rlwinm  r4,r4,0,17,15           /* Turn off EE bit - an external exception while we are flushing
175                                           the cache is fatal (comment this line and see!) */
176        sync
177        mtmsr   r4
178        sync
179       
180        /*
181                Now, read the first 2MB of memory to put new data in the cache.
182                (Actually we only need the size of the L2 cache plus
183                the size of the L1 cache, but 2MB will cover everything just to be safe).
184        */
185        lis     r4,0x0001
186        mtctr   r4
187        li      r4,0
188loadLoop:
189        lwzx    r0,r0,r4
190        addi    r4,r4,0x0020            /* Go to start of next cache line */
191        bdnz    loadLoop
192       
193        /* Now, flush the first 2MB of memory */
194        lis     r4,0x0001
195        mtctr   r4
196        li      r4,0
197        sync
198flushLoop:
199        dcbf    r0,r4
200        addi    r4,r4,0x0020    /* Go to start of next cache line */
201        bdnz    flushLoop
202       
203        /* Turn off the L2CR enable bit. */
204        rlwinm  r3,r3,0,1,31
205       
206        /* Reenable data relocation. */
207        sync
208        mtmsr   r7
209        sync
210       
211dontDisableCache:
212        /* Set up the L2CR configuration bits */
213        sync
214        mtspr   L2CR,r3
215        sync
216        cmplwi  r6,0
217        beq     noInval
218       
219        /* Perform a global invalidation */
220        oris    r3,r3,0x0020
221        sync
222        mtspr   1017,r3
223        sync
224invalCompleteLoop:                      /* Wait for the invalidation to complete */
225        mfspr   r3,1017
226        rlwinm. r4,r3,0,31,31
227        bne     invalCompleteLoop
228       
229        rlwinm  r3,r3,0,11,9;           /* Turn off the L2I bit */
230        sync
231        mtspr   L2CR,r3
232        sync
233       
234noInval:
235        /* See if we need to enable the cache */
236        cmplwi  r5,0
237        beqlr
238       
239enableCache:
240        /* Enable the cache */
241        oris    r3,r3,0x8000
242        mtspr   L2CR,r3
243        sync
244        blr
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